JP3161003B2 - Anodizing method for wiring surface - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor panel having a gate wiring, a data wiring and a thin film transistor formed on a substrate.

[0002]

2. Description of the Related Art A thin film transistor panel (hereinafter, referred to as a TFT panel) in which a gate wiring, a data wiring, and a thin film transistor (TFT) are formed on a substrate is used for, for example, an active matrix liquid crystal display device.

FIG. 8 is a plan view of a part of a TFT panel used in an active matrix liquid crystal display device. FIGS. 9 and 10 are enlarged sectional views taken along lines IX-IX and XX of FIG. The panel is composed of a gate wiring GL and a data wiring DL on a transparent substrate 1 made of glass or the like.
And a plurality of thin film transistors 2, and a pixel electrode 8 is formed corresponding to each thin film transistor 2.

The thin-film transistor 2 has a gate electrode G formed integrally with a gate line GL formed on the substrate 1.
And a gate insulating film 3 made of SiN (silicon nitride) or the like covering the gate electrode, and an i-Si (amorphous silicon) formed on the gate insulating film 3 so as to face the gate electrode G. It comprises a type semiconductor layer 4 and a source electrode S and a drain electrode D formed on the i-type semiconductor layer 4 via an n-type semiconductor layer 5 made of a-Si doped with an n-type impurity. Note that a blocking layer 6 made of SiN or the like is provided on the channel region of the i-type semiconductor layer 4.

The gate insulating film 3 of the thin film transistor 2
Is formed over substantially the entire surface of the substrate 1, and the gate wiring GL is covered with the gate insulating film 3.
Note that the terminal portion of the gate line GL is exposed by removing the gate insulating film 3 thereon.

[0006] A pixel electrode (transparent electrode) 8 is formed on the gate insulating film (transparent film) 12 so as to be located on the side of the thin film transistor 2.
Is connected to the source electrode S by forming one edge thereof on the source electrode S of the thin film transistor 2.

The thin-film transistor 2 is made of SiN
And the like. The interlayer insulating film 9 is also formed over the entire length of the region where the data wiring DL is formed, and the data wiring DL is formed on the interlayer insulating film 9.

The data wiring DL is connected to the drain electrode D of the thin film transistor 2 at a contact hole 9a provided in the interlayer insulating film 9. This data wiring DL
Are covered with a protective insulating film 10 made of SiN or the like.
This protective insulating film 10 is formed in the same pattern as the above-mentioned interlayer insulating film 9. Note that the terminal portion of the data wiring DL is exposed by removing the protective insulating film 10 thereon.

In the above-mentioned TFT panel, an interlayer short circuit between the gate line GL and the data line DL and an interlayer short circuit between the gate electrode G of the thin film transistor 2 and the source and drain electrodes S and D are reliably prevented. The surface of the gate wiring GL, which is the lower wiring, is anodically oxidized including the portion of the gate electrode G to generate an oxide film a on the surface, and the insulating film on the gate wiring GL and the gate electrode G is replaced with the oxide film a. And a gate insulating film 3.

In the anodic oxidation of the gate wiring GL, the substrate 1 on which the gate wiring GL is formed is immersed in an electrolytic solution so that the gate wiring GL on the substrate 1 is opposed to the cathode in the electrolytic solution. As the gate wiring GL
When a voltage is applied between the gate line GL and the counter electrode in the electrolytic solution in this manner, the gate line GL as an anode undergoes a chemical reaction. Then, it is anodized from its surface (upper surface and both side surfaces).

By the way, when the surface of the wiring is anodized,
Since the thickness and width of the non-oxidized layer of the wiring are reduced by an amount corresponding to the oxide film a on the upper surface and both side surfaces of the wiring, the oxidation depth from the wiring surface is required to keep the wiring resistance sufficiently low even after anodic oxidation. It is necessary to control the thickness to a desired ratio with respect to the thickness and width of the wiring before oxidation.

Conventionally, the oxidation depth is controlled by controlling the voltage applied between the wiring (anode) and the cathode, and the oxidation progression depth in the anodic oxidation mainly depends on the applied voltage. Therefore, by controlling the applied voltage according to the thickness of the wiring, the surface of the wiring can be oxidized to a desired oxidation depth.

[0013]

However, the conventional anodic oxidation method in which the depth of oxidation from the wiring surface is controlled by the applied voltage as described above has a problem that the control of the applied voltage is troublesome.

In addition, in the above-described conventional anodic oxidation method, if the thickness of the wiring varies, the thickness of the non-oxidized layer of the oxidized wiring varies. Particularly, when the thickness of the wiring is small, There is also a problem that the thickness of the non-oxidized layer becomes too thin and the resistance of the wiring increases.

That is, the wiring formed on the substrate is formed by forming a metal film on the substrate by a sputtering device or the like and patterning the metal film by photolithography. Since the film thickness is not necessarily uniform for all the substrates, the wiring thickness of each substrate varies even for the same type of substrate on which the wiring of the same standard is formed.

Conventionally, the same voltage is applied to the same type of substrate by applying the same voltage to the anodic oxidation of the wiring. Therefore, the surface of the wiring of any substrate is oxidized to the same oxidation depth. Therefore, if the thickness of the wiring is thin,
The thickness of the non-oxidized layer remaining under the oxide film formed on the wiring surface is reduced, the cross-sectional area (area of the cross section along the width direction of the wiring) is reduced, and the resistance of the wiring is increased.

An object of the present invention is to oxidize the surface of a wiring without leaving troublesome voltage control and leaving a non-oxidized layer having a sufficient cross-sectional area even when the thickness of the wiring varies.
An object of the present invention is to provide a method of anodizing a wiring surface which can suppress an increase in wiring resistance.

[0018]

According to the anodic oxidation method of the present invention, a power supply path for supplying a voltage to the wiring is formed on a substrate on which the wiring is formed, and the power supply path and the wiring are connected to each other. The wiring is made of the same metal and has a cross-sectional area along the width direction connected to a conductive path smaller than the cross-sectional area along the width direction of the wiring, and at least the wiring and the conductive path are immersed in an electrolytic solution. A voltage is supplied from the power supply path to the wiring via the conductive path to anodize the wiring.

[0019]

As described above, the wiring and the conductive path connecting the wiring and the power supply path are immersed in the electrolytic solution, and while the voltage is supplied from the power supply path to the wiring via the conductive path, the anodic oxidation of the wiring is performed. Then, the wiring made of the same metal and the conductive path are oxidized at the same oxidation depth from the surface thereof, and when the conductive path is oxidized over the entire cross section, the supply of voltage from the power supply path to the wiring is cut off. Then, the progress of the oxidation of the wiring is stopped.

In the present invention, the cross-sectional area (the area of the cross section along the width direction) of the conductive path is smaller than the cross-sectional area of the wiring. In each case, the wiring surface is oxidized except for a non-oxidized layer having a cross-sectional area corresponding to the difference from the cross-sectional area before oxidation.

That is, according to the present invention, the oxidation depth of the surface of the wiring is regulated by the cross-sectional area of the conductive path. Therefore, the voltage applied between the wiring and the cathode is limited by the conductive path. It is sufficient that the voltage is not less than a value enough to oxidize the entire cross-section, so that it is not necessary to perform troublesome voltage control, and the difference in cross-sectional area between the conductive path and the wiring is made sufficiently large. For example, even if the thickness of the wiring varies, the surface of the wiring is oxidized while leaving the non-oxidized layer having a sufficient cross-sectional area, and the increase in the resistance of the wiring can be suppressed to a small value.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. This embodiment is an example in which the surface of the gate wiring GL, which is the lower wiring of the TFT panel shown in FIGS. 8 to 10, is anodized.

FIG. 1 is a pattern diagram of a gate wiring, a power supply line, and a conductive path formed on a substrate. FIG. 2 is an enlarged sectional view taken along the line II-II in FIG. 1 before and after anodic oxidation. 1 of I
FIG. 4 is an enlarged sectional view before and after anodic oxidation along line II-III, FIG. 4 is an enlarged sectional view before and after anodic oxidation along line IV-IV in FIG. 1, and FIG. 5 is used for anodic oxidation of wiring. It is a perspective view of an oxidation device.

The anodic oxidation method according to this embodiment employs a method in which a plurality of gate lines GL are formed on a substrate 1 on which a plurality of gate lines GL are formed.
And a plurality of conductive paths 12 connecting the power supply path 11 and each of the gate lines GL. A voltage is supplied to each of the gate lines GL through the gate 12 to anodize the surface of all the gate lines GL.

The above-mentioned power supply path 11 is formed in a margin portion on the outer periphery of the substrate, that is, a portion which is cut and separated along a dividing line c shown by a dashed line in FIG. 1 after completion of the TFT panel or assembly of the liquid crystal display element. The conductive path 12 is formed between the power supply path 11 and the end of each gate line GL. In this embodiment, the power supply path 11 is formed in a frame shape over the entire circumference of the substrate 1 and the terminal portions GL formed at both ends of each gate wiring GL, that is, at one end of the gate wiring GL.
Conductive paths 12 are formed on the outer end side of a and on the other end side of the gate line GL, respectively, and a voltage is supplied to each gate line GL from both ends.

The power supply path 11 and the conductive path 12 are formed of the same metal as the gate wiring GL when forming the gate wiring GL. That is, the gate line GL, the power supply path 11 and the conductive path 12 are formed on the substrate 1 by Al (aluminum), Al
A metal film such as a base alloy, Cr (chromium), Ta (tantalum), Mo (molybdenum) is formed by a sputtering device or the like.
This metal film is formed by patterning by photolithography. In FIG. 1, G is a gate electrode formed integrally with the gate line GL.

At this time, the conductive path 12 is formed to have a width smaller than the width of the gate line GL, and the area of the cross section along the width direction of the conductive path 12 is made smaller than the area of the cross section along the width direction of the gate line GL. Make it smaller. That is, since the conductive path 12 and the gate line GL are formed by patterning the same metal film, they have the same thickness. Therefore, the width of the conductive path 12 is smaller than the width of the gate line GL. Then, the cross-sectional area of the conductive path 12 becomes smaller than the cross-sectional area of the gate line GL. The width of the conductive path 12 is set to approximately twice the layer thickness of the region to be oxidized on the surface of the gate wiring. Note that the power supply path 11
Is formed slightly wider than the width of the gate line GL.

The anodic oxidation of the gate wiring GL is performed by the oxidizing apparatus shown in FIG. This oxidizer,
An electrolytic solution tank 20 filled with an electrolytic solution 21, a reticulated cathode 23 made of platinum or the like immersed in the electrolytic solution 21, and a voltage is applied between the cathode 23 and the gate wiring GL, which is a film to be oxidized. And a power supply (DC power supply) 24. The cathode 23 is connected to the negative pole of the power supply 24, and the positive pole of the power supply 24 is connected to a clip-type connector 26 via an oxidation start switch 25.

Anodization of the gate line GL by this oxidizing device is performed as follows.

First, as shown in FIG. 2A, a resist mask 30 is formed on the terminal portion GLa of the gate line GL. Although the resist mask 30 is not shown in FIG. 1, the resist mask 30 is formed so as to cover almost the entire area of the terminal portion GLa.

Next, as shown in FIG. 5, a clip-shaped connecting member 26 is fixed to the outer peripheral portion of the substrate 1, and a part of the power supply path 11 on the outer peripheral portion of the substrate 1 is connected to the power supply through the connecting member 26. 24+
At the same time as connecting to the poles, the substrate 1 is inserted into the electrolytic solution tank 20, and the gate wiring GL and all of the power supply path 11 and the conductive path 12 are immersed in the electrolytic solution 21. Make them face each other.

Next, the oxidation start switch 25 is turned on,
An oxidation voltage higher than a value sufficient to oxidize the conductive path 12 over the entire cross section is applied between the gate line GL and the cathode 23. In this case, the + voltage applied to the gate line GL is supplied from the power supply path 11 on the outer peripheral portion of the substrate to the conductive path 1.
2 to the gate line GL via the
1 and between the conductive path 12 and the cathode 23.

As described above, when a voltage is applied between the gate line GL and the cathode 23, a portion of the gate line GL that is not covered with the resist mask 30 (a portion excluding the terminal portion GLa) becomes in the electrolytic solution 21. A chemical reaction is caused to be anodized from the surface thereof, and the power supply path 11 and the conductive path 12 which are voltage supply paths to the gate wiring GL are also formed in the electrolytic solution 21.
A chemical conversion reaction takes place inside, and the surface is anodically oxidized.

In this case, the gate wiring GL, the power supply path 11 and the conductive path 12 are all anodized almost uniformly from the upper surface and both side surfaces.
Since the width is smaller than the width of the gate line GL, the conductive path 12 is oxidized over the entire cross section when the upper surface and both side surfaces of the gate line GL are oxidized to a certain depth.

That is, the thickness of the conductive path 12 is the same as the thickness of the gate wiring GL, but the width of the conductive path 12 is almost twice the layer thickness of the oxidized region on the surface of the gate wiring as described above. When the oxidation depth of each surface of the gate wiring GL reaches the layer thickness of the region to be oxidized as shown in FIGS. 2B and 3B, the conductive path 12 As shown in FIGS. 2B and 4B, the entire width of the conductive path 12 becomes an oxide film a. Since the width of the power supply line 11 is slightly larger than the width of the gate line GL, the power supply line 11 is only oxidized on the upper surface and both side surfaces similarly to the gate line GL.

As described above, when the conductive path 12 is oxidized over the entire cross section, the entire cross section of the conductive path 12 becomes insulative, so that the supply of voltage from the power supply path 11 to the gate line GL is cut off. Then, the progress of the oxidation of the gate line GL stops.

For this reason, the gate wiring GL has a cross-sectional area and a cross-sectional area of the conductive path 12 (both before the oxidation).
The wiring surface is oxidized while leaving a non-oxidized layer having a cross-sectional area corresponding to the difference. Therefore, the conductive path 12 and the gate line GL
If the difference in cross-sectional area between the gate wiring G
The surface of the gate line GL can be oxidized while leaving a non-oxidized layer having a sufficient sectional area in L.

When the metal is oxidized, its volume increases. Therefore, the thickness of the oxidized gate line GL, the power supply path 11 and the conductive path 12 shown in FIGS.
4 to a certain thickness as compared to the thickness before oxidation shown in FIG. The thickness of the oxide film a generated on the surface of the gate line GL and the power supply path 11 until the entire cross section of the conductive path 12 is oxidized is approximately one width of the width of the conductive path 12 whose entire cross section is oxidized. / 2.

That is, in this embodiment, the gate wiring GL
Is regulated by the cross-sectional area of the conductive path 12 connecting the power supply path 11 and the gate wiring GL. Therefore, the oxidation voltage applied between the gate wiring GL and the cathode 23 is reduced. It is sufficient that the voltage is at least a value sufficient to oxidize the conductive path 12 over the entire cross section, so that it is not necessary to perform complicated voltage control.

In the conventional anodic oxidation in which the oxidation depth is controlled by a voltage, as described in the section of [Problems to be Solved by the Invention], if there is a variation in the thickness of the wiring, the oxidation treatment is performed. The thickness of the non-oxidized layer of the formed wiring varies, and particularly when the thickness of the wiring is thin, the thickness of the non-oxidized layer becomes too thin, and the resistance of the wiring increases. In the example, since the oxidation depth of the surface of the gate line GL is regulated by the cross-sectional area of the conductive path 12,
As long as the difference between the cross-sectional areas of the conductive path 12 and the gate wiring GL is made sufficiently large, even if the thickness of the gate wiring GL varies, a non-oxidized layer having a sufficient cross-sectional area can be formed on the gate wiring GL. The surface of the wiring can be oxidized while being left, so that an increase in resistance of the gate wiring GL due to anodic oxidation of the surface can be suppressed to a small value.

In the above-described embodiment, the width of the conductive path 12 is reduced in order to make the cross-sectional area of the conductive path 12 smaller than the cross-sectional area of the gate line GL.
The thickness of the conductive path 12 may be reduced by reducing the thickness.

FIGS. 6 and 7 show another embodiment of the present invention. FIG. 6 is a pattern diagram of a gate wiring, a power supply path and a conductive path formed on a substrate, and FIG.
It is an expanded sectional view before and after anodization along II-VII line.

In this embodiment, the width of the conductive path 12 is made the same as the width of the gate line GL as shown in FIG. 6, and the thickness of the conductive path 12 is half-etched on the upper surface as shown in FIG. By reducing the thickness as described above, the sectional area of the conductive path 12 is made smaller than the sectional area of the gate wiring GL, and the thickness of the conductive path 12 is made substantially equal to the layer thickness of the oxidized region on the surface of the gate wiring. It is.

In this embodiment, the anodic oxidation of the gate line GL is performed in the same manner as in the above-described embodiment.
The description will be omitted by attaching the same reference numerals to the drawings. However, in the case of this embodiment, the thickness of the oxide film a formed on the surface of the gate line GL and the power supply path 11 until the entire cross section of the conductive path 12 is oxidized is shown in FIG. like,
The entire cross section has the same thickness as the oxidized conductive path 12.

In each of the above embodiments, the cross-sectional area of the conductive path 12 is reduced over its entire length. However, the cross-sectional area of the conductive path 12 may be reduced in at least a part thereof. The substrate 1 may be immersed in the electrolytic solution 21 at least at a portion where the cross-sectional area of the gate line GL and the conductive path 12 is reduced.

The present invention is not limited to the anodic oxidation of the lower wiring (gate wiring GL in the above embodiment) of the TFT panel. For example, a multilayer wiring board in which wiring is formed in a plurality of layers with an insulating film interposed on a substrate is provided. Can be applied to the anodic oxidation of the lower wiring surface.

[0047]

According to the anodic oxidation method of the present invention, a power supply path for supplying a voltage to the wiring is formed on a substrate on which the wiring is formed, and the power supply path and the wiring are made the same as the wiring. The conductive path is made of metal and has a cross-sectional area along the width direction that is smaller than the cross-sectional area along the width direction of the wiring, and at least the wiring and the conductive path are immersed in an electrolytic solution. Since a voltage is supplied to the wiring through the conductive path to anodize the wiring, sufficient voltage control can be performed without any troublesome voltage control, and sufficient disconnection can be performed even when the wiring thickness varies. By oxidizing the wiring surface while leaving the non-oxidized layer in the area, the increase in the resistance of the wiring can be suppressed to a small value.

[Brief description of the drawings]

FIG. 1 is a pattern diagram of a gate wiring, a power supply path, and a conductive path formed on a substrate, showing one embodiment of the present invention.

FIG. 2 is an enlarged sectional view taken along a line II-II in FIG. 1 before and after anodic oxidation.

FIG. 3 is an enlarged sectional view taken along the line III-III in FIG. 1 before and after anodic oxidation.

FIG. 4 is an enlarged sectional view taken along the line IV-IV in FIG. 1 before anodic oxidation and after oxidization.

FIG. 5 is a perspective view of an oxidation apparatus used for anodizing a wiring.

FIG. 6 is a pattern diagram of a gate wiring, a power supply path, and a conductive path formed on a substrate, showing another embodiment of the present invention.

FIG. 7 is an enlarged sectional view taken along the line VII-VII of FIG. 6 before and after anodic oxidation.

FIG. 8 is a plan view of a TFT panel obtained by anodizing a surface of a gate wiring as a lower wiring.

FIG. 9 is an enlarged sectional view taken along line IX-IX in FIG. 8;

FIG. 10 is an enlarged sectional view taken along line XX of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, GL ... Gate wiring, GLa ... Terminal part, G ... Gate electrode, 11 ... Feeding path, 12 ... Conducting path, a ... Oxide film,
21: electrolytic solution, 30: resist mask.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/768 H01L 21/90 L 27/12 21/88 B 29/786 G02F 1/136 500 (58) Fields surveyed (Int. .Cl. ⁷ , DB name) H01L 21/316 C25D 11/04 H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] 1. A method in which a wiring formed on a substrate is opposed to a cathode in an electrolytic solution, and a voltage is applied between the wiring and the cathode to anodize the surface of the wiring. A power supply path for supplying a voltage to the wiring is formed on the formed substrate, and the power supply path and the wiring are formed of the same metal as the wiring and have a cross-sectional area along the width direction of the wiring. Connected by a conductive path smaller than the area of the cross section along the width direction, immerse at least the wiring and the conductive path in an electrolytic solution, supply a voltage from the power supply path to the wiring via the conductive path, Anodizing the wiring surface, wherein the wiring is anodized.