JPS61133662A - Active matrix type thin film transistor substrate - Google Patents

Abstract

PURPOSE:To improve the manufacturing yield rate of a liquid crystal display device, by using a double-layer structure of SiN:N and Al2O3 for inter-wire insulating layers between a gate and a drain and between a source and the drain, and providing a thickness of 200-500Angstrom for the Al2O3 film. CONSTITUTION:A double-layer structure of an SiN:H layer and an oxide insulating layer of a gate wire metal is used for inter-wire insulating films between a gate and a drain and between the gate and a source, in an active matrix type thin film transistor. In manufacturing the substrate on the side of a thin film transistor, an Al gate wire 2 is patterned on an insulating substrate comprising glass and the like, and an Al2O3 insulating film 9 is formed on the surface by anodic oxidation. Then, a picture element electrode 3 is formed by a transparent conducting film. A gate insulating layer 7 made of SiN:H, an amorphous silicon semiconductor layer 4 and an n<+> amorphous silicon layer 8 are deposited by a plasma CVD method. Patterning is performed in a specified shape. Finally a source wire 5 and a drain wire 6 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an active matrix type (hereinafter referred to as A or M type) thin film transistor substrate (hereinafter referred to as TPT substrate).

[Prior art] Conventionally, A and M type TFT substrates are produced by patterning a gate line with Au, Ta, Mo, Cr, N1Cr, etc. on an insulating substrate such as glass, and then patterning a gate line with indium oxide-tin oxide. A pixel is formed with a transparent conductive film such as a transparent conductive film (hereinafter referred to as ITO), an SiN:H film is used as an insulating layer, an amorphous silicon layer is used as a semiconductor layer, and n+7 moles are used to make ohmic contact with the source and drain electrodes. 7779
937 layers are deposited, patterned into a predetermined shape by a normal photolithography process, and finally source lines and drain lines are formed using Al, Ta, Mo, Cr, NiCr, etc. (lower gate stagger). type TPT).

In this case, the SiN:H layer also serves as a gate insulating layer and an interline insulating layer between the source and gate. The SiN:H film formed by the plasma CVD method can be formed at low temperatures (~250°C) and has features such as a higher relative permittivity than other inorganic insulating films such as 5i02, so it can be used as a gate insulating film for TPT. Extremely good transistor characteristics can be obtained. However, if there are pinholes or the like in the SiN:H film, it may cause a source-to-gate or drain-to-gate short, which appears as a line defect on the display panel.
This caused defects in the T-substrate.

In recent years, as TPTs have become larger in area and higher in definition, the number of TPTs and the number of source lines and gate lines have increased.
:The number of overlapping parts increases with an insulating layer such as an H film interposed therebetween. Therefore, if there is an insulation defect in an insulating layer such as a SiN:H film, the manufacturing yield of TPT substrates will be significantly reduced.

[Problems to be Solved by the Invention] The purpose of the present invention is to significantly reduce defects in TPT substrates caused by pinholes in insulating layers such as SiN:H films, and to improve manufacturing yields of liquid crystal display devices. do.

[Means and effects for solving the problems] In order to solve these problems, the inventors of the present invention have conducted various studies, and have developed an insulating layer with a SiN:H film, an oxide layer on the gate line metal surface, and an insulating layer. The present invention was made based on the discovery that the object could be achieved by forming the layers into a two-layer structure. That is, the present invention is an active matrix type thin film transistor substrate in which the line insulating layer between the gaiters 194 and between the gaiter source has a two-layer structure of a SiN:H layer and an oxide insulating layer of gate line metal.

[Example] Next, the present invention will be described in detail based on the accompanying drawings.

FIG. 1 is a plan view showing an embodiment of the A and M type TFT substrates of the present invention. 1 is a TFT side insulating substrate such as glass, 2
is a metal that can be oxidized (e.g. AM, Ta, Mo, C
3 is a pixel electrode such as ITO, 4 is a semiconductor layer such as amorphous silicon, 5 is a source line, and 6 is a drain line. Figures 2(a) and 2(b) are A of Figure 1, respectively.
-A" cross-section and B-B" cross-section.

7 is a gate insulating layer such as a SiN:H layer formed using a plasma CVD method; 8 is an n1 amorphous silicon layer; 9
is an insulating layer obtained by, for example, anodic oxidation of the surface of the gate line 2.

The case where AA is used as the gate line will be described below. Figures 3(a) to (e) show plasma C as an insulating layer.
This figure shows an example of the manufacturing process of a TFT side plate using a VD SiN:H film and an A-pattern anodic oxide film. A4fL gate line 2 is patterned on an insulating substrate 1 such as glass, and A pattern is formed on the surface.

03 Insulating layer 9 is formed by anodic oxidation. Next, the pixel electrode 3 is formed of a transparent conductive film such as ITO, and then plasma
A gate insulating layer 7 of SiN:H, a semiconductor layer 4 of amorphous silicon, and an n+ amorphous silicon layer 8 are deposited using the VD method, and patterned into a predetermined shape using a normal photolithography process.Finally, a source line 5, a drain Line 6 is formed.

It is preferable to oxidize the AJI gate line by an anodic oxidation method, as shown in Figure 4, after patterning the gate electrode, immerse it in an electrolytic solution except for the gate line lead-out part, and then oxidize the AJI gate line in a predetermined manner using the AJI as an anode. The anodizing voltage is maintained for a certain period of time to perform anodic oxidation. As the electrolyte, a 1% aqueous solution of ammonium borate (NH4/B505) or tartaric acid (
Propylene glycol (CH3CH(OH) CH20H
) was used. Al 203 formed by the above method is a dense, non-porous film without pinholes, and since the film thickness of All, 03 is proportional to the formation voltage, the film thickness can be easily controlled. It has its features.

Table 1 shows SiN:H and anodized Al as an insulating layer.
The results of actually fabricating TPT substrates and comparing the probability of short circuit occurrence when using the 203 double-layer structure and when only SiN:H is used in the conventional example are shown below. As is clear from Table 1, A
If the thickness of l 203 is 200 Å or more, the probability of short circuit occurring between the source and the gate or between the drain and the gate is greatly reduced. Furthermore, it has been found that when the AlzO3 film thickness is approximately 500 Å or less, there is almost no difference in transistor characteristics from that of the conventional example.

As another example, all the gate lines are patterned so as to be short-circuited, and portions where an anodic oxide film is not needed, such as the connection with the drive circuit, are covered with photoresist (for example: AZ-1).
There is also a method of performing anodic oxidation by covering with 350 J). The short-circuited gate line may be cut by a laser or the like after the TFT substrate is completed.

[Effects of the Invention] As explained above, the present invention has a two-layer structure of SiN:H and the A pattern 203 for the line insulating layer between the gate and the drain and between the source and gate, and the film thickness of the A pattern 203 is reduced. 200-5
00A, it is possible to dramatically improve the manufacturing yield of matrix type liquid crystal display devices without impairing the TPT characteristics.

Furthermore, it goes without saying that the structure of the insulating layer is not limited to SiN:H and A-203, but any combination of an inorganic insulating film and a metal oxide film is within the scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of an active matrix thin film transistor substrate of the present invention, FIG. 2(a),
Figure 2(b) is the cross section AA' and B in Figure 1, respectively.
3 is a sectional view showing an example of the manufacturing process of the thin film transistor substrate of the present invention, and FIG.
An explanatory diagram illustrating an anodizing device and Table 1 are tables showing comparative examples of short-circuit occurrence probabilities. 1...TFT side insulating substrate 2...Gate line 3...Pixel electrode 4...
Semiconductor layer 5...Source line 6...
Drain line 7... Gate insulating layer 8... n+7 moles 7779917 layer 9...
... Insulating layer patent applicant Canon Co., Ltd. Agent Yutaka 1) Yoshio Figure 3 (α) Procedural amendment April 22, 1985

Claims (1)

[Claims] An active matrix thin film transistor substrate characterized in that the line insulating layer between the gate and the drain and between the gate and the source has a two-layer structure of an SiN:H film and an oxide layer of a gate line metal or an oxide insulating layer.