JPS63216091A - Matrix type display device - Google Patents
Matrix type display deviceInfo
- Publication number
- JPS63216091A JPS63216091A JP62049679A JP4967987A JPS63216091A JP S63216091 A JPS63216091 A JP S63216091A JP 62049679 A JP62049679 A JP 62049679A JP 4967987 A JP4967987 A JP 4967987A JP S63216091 A JPS63216091 A JP S63216091A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- source
- drain
- display device
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 239000012769 display material Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 description 12
- 239000010409 thin film Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は薄膜トランジスタを利用するマトリクス型表
示装置に関するもので、特に配線交差部の短絡及び配線
の断線を低減し、表示装置の大面積化及び高解像化を図
るものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a matrix type display device using thin film transistors, and in particular reduces short circuits and disconnections at wiring intersections, increases the area of the display device, and The aim is to achieve high resolution.
薄膜トラシジスタアレイを践マトリクス型表示装置は、
通常２枚の対向基板の間に液晶等の表示材料が挾持され
た構造となっておシ、この表示材料に電圧を印加する。A matrix type display device that uses a thin film transistor array is
Usually, a display material such as a liquid crystal is sandwiched between two opposing substrates, and a voltage is applied to this display material.
そして少くとも一方の基板にマトリクス状に配列した画
素電極を設けており、これらの画素を選択的に動作する
ために各画素毎にＦＥＴ （電界効果トランジスタ）等
の非線形を有する能動素子を設けている。At least one substrate is provided with pixel electrodes arranged in a matrix, and in order to selectively operate these pixels, each pixel is provided with a nonlinear active element such as an FET (field effect transistor). There is.
従来この種の装置としては例えば特開昭６０−１２９７
８１号公報に記されたようなものがあった。第４因は従
来のマ） ＩＪクス型表示装置の薄膜トランジスタアレ
イを主に一画素部分を示す部分平面図、第５因は第４図
におけるｖ−Ｖ線断面図、第６図は弗４図におけるＶｌ
−Ｖｌ線断面図である。Conventional devices of this type include, for example, Japanese Patent Application Laid-Open No. 60-1297.
There was something like the one described in Publication No. 81. The fourth factor is a partial plan view mainly showing one pixel portion of the thin film transistor array of a conventional IJ type display device, the fifth factor is a cross-sectional view taken along the line v-V in FIG. 4, and FIG. Vl in
-Vl line sectional view.
因において、＋１）は透明絶縁性基板、（２１はゲート
電極（２ａ）及び電極配線（２ｔ）） 、＋３１はソー
ス電極（３ａ）及び電極配線（３ｂ） 、（４）はドレ
イン電極、（５）は画素電極、（６１はゲート絶縁膜、
（７）はノ〉ドープ半導体層、（８）はりンドープ半導
体層、（９）はバンシベーション膜、凹は遮光膜、住υ
はドレイン電極１画素コシタクト部である。In the above, +1) is the transparent insulating substrate, (21 is the gate electrode (2a) and electrode wiring (2t)), +31 is the source electrode (3a) and electrode wiring (3b), (4) is the drain electrode, (5 ) is a pixel electrode, (61 is a gate insulating film,
(7) is a doped semiconductor layer, (8) is a doped semiconductor layer, (9) is a bancivation film, and the concave is a light-shielding film.
is a one-pixel cositact portion of the drain electrode.
例えばマ） ＩＪクス型液晶表示装置等に用いられる薄
膜トランジスタアレイのソース電極及び電極配線は通常
配線抵抗による信号の減衰を防止するために、Ｍ等の低
抵抗金属が用いられる。For example, a low resistance metal such as M is usually used for the source electrode and electrode wiring of a thin film transistor array used in an IJ type liquid crystal display device or the like in order to prevent signal attenuation due to wiring resistance.
しかし、大面積高解像度化に伴って、ソース電極及び電
極配線（以下配線）が微細化されるためにゴミ等による
バターニング不良に起因する断線が発生したり、ソース
及びゲート配線の交差部が増加することによって、この
部分での短絡が発生するという問題点があった。However, as source electrodes and electrode wiring (hereinafter referred to as wiring) become finer as the resolution increases over large areas, disconnections may occur due to poor patterning due to dust, and intersections between source and gate wiring may occur. There is a problem in that short circuits occur in this part due to the increase in the number of parts.
この発明はかかる問題点を解決するためになされたもの
で、配線の断線及び配線交差部における短絡を著しく低
減し、大面積、高解像度のマトリクス型表示装置を得る
ことを目的とする。The present invention has been made to solve these problems, and aims to significantly reduce wire breaks and short circuits at wire intersections, and to provide a large-area, high-resolution matrix type display device.
この発明のマ） ＩＪクス型表示装置は、複数の並行す
るゲート電極配線、これらのゲート電極配線と交差する
複数の並行するソース（又はドレイン）電極配線、上記
ゲート電極配線とソース（又はドレイン）電極配線の各
交差部に形成され、ゲート電極が上記ゲート電極配線圧
ソース（又はドレイン）電極が上記ソース（又はドレイ
ン）電極配線に接続されたトランジスタを有する絶縁性
基板と、対向電極基板との間に表示材料を介在させたマ
トリクス型表示装置において、上記トランジスタはゲー
ト電極、ゲート絶縁膜、第１半導体層、極性を決める不
純物をドープした第２半導体層、コンタクト金属層、ソ
ース電極及びドレイ〉電極を有するとともに、少くとも
上記第１半導体層及びコンタクト金属層を複数の並行す
る上記ソース（又はドレイン）電極配線と絶縁性基板間
にソース（又はドレイン）電極配線側がコンタクト金属
層として延在させたものである。The IJ type display device according to the present invention includes a plurality of parallel gate electrode wirings, a plurality of parallel source (or drain) electrode wirings that intersect with these gate electrode wirings, and a source (or drain) electrode wiring that intersects with these gate electrode wirings. An insulating substrate having a transistor formed at each intersection of the electrode wiring and having a gate electrode connected to the gate electrode wiring and a source (or drain) electrode connected to the source (or drain) electrode wiring, and a counter electrode substrate. In a matrix display device in which a display material is interposed between the transistors, the transistor includes a gate electrode, a gate insulating film, a first semiconductor layer, a second semiconductor layer doped with an impurity that determines polarity, a contact metal layer, a source electrode, and a drain. an electrode, and at least the first semiconductor layer and the contact metal layer are extended between the plurality of parallel source (or drain) electrode wirings and the insulating substrate, with the source (or drain) electrode wiring side serving as a contact metal layer. It is something that
この発明に詔けるコンタクト金属層は第２のソース（又
はドレイン）電極及び電極配線のような役を担い、二層
構造のような構成となるので、配線の断線を著しく低減
できる。また第１半導体層が配線交差部の絶縁耐圧を向
上させるので短絡を著しく低減できる。The contact metal layer according to the present invention plays the role of the second source (or drain) electrode and the electrode wiring, and has a two-layer structure, so that disconnection of the wiring can be significantly reduced. Furthermore, since the first semiconductor layer improves the dielectric strength of the wiring intersection, short circuits can be significantly reduced.
第１図はこの発明の一実施例のマトリクス型表示装置の
一画素部を薄膜トラ〉ジスタアレイを主に示す部分平面
図、第２図は第１図における■−■線断面図、第３図は
第１図に詔けるＩ−Ｉ線断面図である。図において、（
７）は第１半導体層で、この場合はノンドープ半導体層
、（８１は極性を決める不純物をドープした第２半導体
層で、この場合はりンドープ半導体層、圓はコンタクト
金属層である。FIG. 1 is a partial plan view mainly showing a thin film transistor array of one pixel portion of a matrix type display device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. is a cross-sectional view taken along the line I--I shown in FIG. In the figure, (
7) is a first semiconductor layer, in this case a non-doped semiconductor layer; (81 is a second semiconductor layer doped with an impurity that determines polarity; in this case, 81 is a phosphorus-doped semiconductor layer; and 81 is a contact metal layer).
まずガラス等の透明絶縁性基板（１）上をＩＴＯ（Ｉｎ
ｄｉｕｍ Ｔｉｎ ０ｘｉｄｅ ）等の透明導電膜をｇ
Ｂ蒸肴法等で堆積形成する。この後ホ） ＩＪングラフ
イ等の方法で画素電極（５）を形成する。次ＫＥＢ蒸着
法等でａｒ等の金属を堆積し、ゲート電極及び電極配線
（２）を形成する。次にゲート絶縁膜（６）として５ｉ
ｓＮ４または！３１０ｚ等、ノンドープ半導体層（７）
としてアモルファスシリコン等及びり〉ドープ半導体層
（８）として水素化アモルファスシリコン（ａ−８１：
Ｈ）等を連通してＯＶＤ法等により堆積した後、さらに
８ｂ蒸着法等でＴ１等のコシタクト金属層αａを堆積形
成する。次いで順次、コシタクト金Ｒ層ＣＩつ、リンド
ープ半導体層（８）、及びノンドープ半導体層（７）を
第１図のように形成する。この時に、コンタクト金属層
（Ｌ２、りンドープ半導体層（８１及び〕〉ドープ半導
体層（７）で仮想ソース配線を形成する。次にゲート絶
縁膜（６）に画素電極（５）とドレイン電極（４）を接
続するためのコンタクトホールの形成を行った後、Ｍ等
の金属を堆積し、ソース電極及び電極配線（３）を前述
の仮想ソース配線上に形成する。次にパッシベーション
膜＋９１として３ｉ３０４またはＳｉ ０２等を堆積す
る。そして一括して画素電極（５１上部のゲート絶縁膜
（６）及びパッシベーション膜１９１を取り除く。次に
Ｍ等を堆積し、遮光膜Ｃ１ｌを形成する。First, a transparent insulating substrate (1) such as glass is coated with ITO (In).
A transparent conductive film such as dium tin oxide) is
B. Deposits are formed using the steaming method, etc. After this, e) a pixel electrode (5) is formed by a method such as IJ graphing. Next, a metal such as argon is deposited by KEB evaporation method or the like to form a gate electrode and electrode wiring (2). Next, as the gate insulating film (6), 5i
sN4 or! Non-doped semiconductor layer (7) such as 310z
Hydrogenated amorphous silicon (a-81:
H), etc., and deposited by OVD method or the like, and then a cositact metal layer αa such as T1 is further deposited by 8b evaporation method or the like. Next, a cositact gold R layer CI, a phosphorus-doped semiconductor layer (8), and a non-doped semiconductor layer (7) are sequentially formed as shown in FIG. At this time, a virtual source wiring is formed using the contact metal layer (L2, the phosphorus-doped semiconductor layer (81) and the doped semiconductor layer (7). Next, the pixel electrode (5) and the drain electrode ( After forming a contact hole for connecting 4), a metal such as M is deposited, and a source electrode and electrode wiring (3) are formed on the virtual source wiring described above.Next, 3i304 is formed as a passivation film +91. Alternatively, deposit Si 02 or the like. Then, remove the gate insulating film (6) and the passivation film 191 on the pixel electrode (51) at once. Next, deposit M or the like to form a light shielding film C1l.
このようにして形成されたトランジスタを有する絶縁性
基板、即ち薄膜トランジスタ（ＴＦＴ）アレイ基板と、
透引導電電極及びカラーフィルタ等を有する対向電極基
板との間に液晶等の表示材料が挾持され、マ） ＩＪク
ス型表示装置が完成する。An insulating substrate having a transistor formed in this manner, that is, a thin film transistor (TFT) array substrate;
A display material such as a liquid crystal is sandwiched between a transparent conductive electrode and a counter electrode substrate having a color filter, etc., and an IJ type display device is completed.
このようにして得られたＴＦＴアレイ及び表示装置は、
コンタクト金属層（１２が第２のソース電極及び電極配
線（３）のような役を担い、ソース電極及び電極配線が
二層で構成された形となシ、しかも、バターニングが別
々になっているため、どちらかにバターニング不良等が
発生しても、もう一方の層で接続されているため、断線
欠陥とならない。The TFT array and display device thus obtained are
The contact metal layer (12) plays the role of the second source electrode and the electrode wiring (3), and the source electrode and the electrode wiring are made up of two layers, and the patterning is done separately. Therefore, even if a patterning defect occurs in either layer, it will not result in a disconnection defect because the connection is made in the other layer.
さらに同一場所でのパターン欠陥の起こる確率は極めて
低い。従って断線を著しく低減できる。また、ゲート電
極及び電極配線（２１とソース電極及び電極配線（３）
との交差部はゲート絶縁膜（６１、ノンドープ半導体層
（７）の二層で絶縁されることになり、この部分の絶縁
耐圧は向上し、静電破壊等による短絡は減少する。Furthermore, the probability of pattern defects occurring at the same location is extremely low. Therefore, disconnection can be significantly reduced. In addition, the gate electrode and electrode wiring (21) and the source electrode and electrode wiring (3)
The intersection with the gate insulating film (61) and the non-doped semiconductor layer (7) will be insulated by two layers, and the withstand voltage of this part will be improved and short circuits due to electrostatic breakdown etc. will be reduced.
従って、この実施例のマトリクス型表示装置は極めて表
示欠陥を低減でき大面積、高解像化が実現できる。Therefore, the matrix type display device of this embodiment can significantly reduce display defects and realize a large area and high resolution.
なお、上記実施例では、第１半導体層がノンドープ半導
体層の場合について説明したが、ソース電極配線とゲー
ト電極配線の絶縁が保てるくらいの微量のＰ型不純物、
例えばＢが含まれていても同様の効果を素する。In the above embodiment, the first semiconductor layer is a non-doped semiconductor layer, but a trace amount of P-type impurity to maintain insulation between the source electrode wiring and gate electrode wiring,
For example, even if B is included, the same effect will occur.
以上のように、この発明によれば複数の並行するゲート
電極配線、これらのゲート電極配線と交差する複数の並
行するソース（又はドレイン）電極配線、上記ゲート電
極配線とソース（又はドレイン）電極配線の各交差部に
形成され、ゲート電極が上記ゲート電極配線にソース（
又はドレイン）電極が上記ソース（又はドレイン）電極
配線に接続されたトランジスタを有する絶縁性基板と対
向電極基板との間に表示材料を介在させたマトリクス型
表示装置において、上記トランジスタはゲート電極、ゲ
ート絶縁膜、第１半導体層、極性を決める不純物をドー
プした第２半導体層、コンタクト金属層、ソース電極及
びドレイン電極を有するとともに、少くとも上記第１半
導体層及びコンタクト金属層を複数の並行する上記ソー
ス（又はドレイン）電極配線と絶絶性基板間にソース（
又はドレイン）電極配線側がコンタクト金属層として見
在させることによシ、ソース（又はドレイン）電極及び
電極配線の断線並びにソース（又はドレイン）電極及び
電極配線とゲート電極及び電極配線との交差部における
短絡を防止でき大面積。As described above, according to the present invention, a plurality of parallel gate electrode wirings, a plurality of parallel source (or drain) electrode wirings that intersect with these gate electrode wirings, and the above-mentioned gate electrode wirings and source (or drain) electrode wirings. The gate electrode is formed at each intersection of the gate electrode wiring and the source (
In a matrix type display device in which a display material is interposed between an insulating substrate and a counter electrode substrate having a transistor whose gate electrode (or drain) electrode is connected to the source (or drain) electrode wiring, the transistor has a gate electrode, a gate It has an insulating film, a first semiconductor layer, a second semiconductor layer doped with an impurity that determines polarity, a contact metal layer, a source electrode, and a drain electrode, and at least the first semiconductor layer and the contact metal layer are arranged in parallel with each other. Source (or drain) between the source (or drain) electrode wiring and the instable substrate
By making the (or drain) electrode wiring side visible as a contact metal layer, disconnections in the source (or drain) electrode and electrode wiring and at intersections between the source (or drain) electrode and electrode wiring and the gate electrode and electrode wiring can be avoided. Large area that prevents short circuits.
高解像度のマ） ＩＪクス型表示装置が得られる効果が
ある。This has the effect of providing a high-resolution matrix type display device.
第１図はこの発明の一実施例のマ） ＩＪクース型表示
装置の一部を示す部分平面図、第２図は第１図に＃ける
■−■線断面図、第３図は第１図におけるＩ−１線断面
図、第４図は従来のマトリクス型表示装置の一部を示す
部分平面図、第５図は第４図のｖ−ｖ線断面図、第６図
は第４図における■−■線断面図である。
図において、（１）は絶縁性基板、（２）はゲート電極
（２ａ）とゲート電極配線（２ｂ）、（３）はソース電
極（３ａ）とソーク電極配線、（４）はドレイン電極、
（７）は第１半導体層、＋８）は第２半導体層、ａ’ａ
はコンタクト金属層である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a partial plan view showing a part of an IJ-Coos type display device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line #1 in FIG. 4 is a partial plan view showing part of a conventional matrix type display device, FIG. 5 is a sectional view taken along line v-v in FIG. 4, and FIG. 6 is a sectional view taken along line I-1 in FIG. It is a sectional view taken along the line ■-■. In the figure, (1) is an insulating substrate, (2) is a gate electrode (2a) and gate electrode wiring (2b), (3) is a source electrode (3a) and soak electrode wiring, (4) is a drain electrode,
(7) is the first semiconductor layer, +8) is the second semiconductor layer, a'a
is the contact metal layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (3)
電極配線と交差する複数の並行するソース（又はドレイ
ン）電極配線、上記ゲート電極配線とソース（又はドレ
イン）電極配線の各交差部に形成され、ゲート電極が上
記ゲート電極配線にソース（又はドレイン）電極が上記
ソース（又はドレイン）電極配線に接続されたトランジ
スタを有する絶縁性基板と、対向電極基板との間に表示
材料を介在させたマトリクス型表示装置において、上記
トランジスタはゲート電極、ゲート絶縁膜、第１半導体
層、極性を決める不純物をドープした第２半導体層、コ
ンタクト金属層、ソース電極及びドレイン電極を有する
とともに、少くとも上記第１半導体層及びコンタクト金
属層を複数の並行する上記ソース（又はドレイン）電極
配線と絶縁性基板間にソース（又はドレイン）電極配線
側がコンタクト金属層として延在させたことを特徴とす
るマトリクス型表示装置。(1) A plurality of parallel gate electrode wirings, a plurality of parallel source (or drain) electrode wirings that intersect with these gate electrode wirings, and a plurality of parallel source (or drain) electrode wirings formed at each intersection of the gate electrode wiring and the source (or drain) electrode wiring. , a matrix in which a display material is interposed between an insulating substrate having a transistor having a gate electrode connected to the gate electrode wiring and a source (or drain) electrode connected to the source (or drain) electrode wiring, and a counter electrode substrate; In the type display device, the transistor has a gate electrode, a gate insulating film, a first semiconductor layer, a second semiconductor layer doped with an impurity that determines polarity, a contact metal layer, a source electrode, and a drain electrode, and at least the first semiconductor layer. A matrix display device characterized in that a plurality of parallel semiconductor layers and contact metal layers extend between the source (or drain) electrode wiring and the insulating substrate, with the source (or drain) electrode wiring side serving as the contact metal layer. .
特徴とする特許請求の範囲第１項記載のマトリクス型表
示装置。(2) The matrix type display device according to claim 1, wherein the first semiconductor layer is a non-doped semiconductor layer.
に、第１、第２半導体層及びコンタクト金属層を延在さ
せたことを特徴とする特許請求の範囲第１項又は第２項
記載のマトリクス型表示装置。(3) Claim 1 or 2, characterized in that the first and second semiconductor layers and the contact metal layer extend between the source (or drain) electrode wiring and the insulating substrate. matrix type display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049679A JPS63216091A (en) | 1987-03-04 | 1987-03-04 | Matrix type display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049679A JPS63216091A (en) | 1987-03-04 | 1987-03-04 | Matrix type display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63216091A true JPS63216091A (en) | 1988-09-08 |
Family
ID=12837864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62049679A Pending JPS63216091A (en) | 1987-03-04 | 1987-03-04 | Matrix type display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63216091A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137825A (en) * | 1988-11-18 | 1990-05-28 | Sharp Corp | Active matrix substrate |
| JP2015130453A (en) * | 2014-01-09 | 2015-07-16 | 株式会社Ｊｏｌｅｄ | Thin-film transistor, display device, and electronic apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151188A (en) * | 1984-08-21 | 1986-03-13 | セイコーインスツルメンツ株式会社 | Substrate for active matrix display unit |
| JPS6156382A (en) * | 1984-08-28 | 1986-03-22 | セイコーインスツルメンツ株式会社 | Manufacture of thin film transistor display panel |
-
1987
- 1987-03-04 JP JP62049679A patent/JPS63216091A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151188A (en) * | 1984-08-21 | 1986-03-13 | セイコーインスツルメンツ株式会社 | Substrate for active matrix display unit |
| JPS6156382A (en) * | 1984-08-28 | 1986-03-22 | セイコーインスツルメンツ株式会社 | Manufacture of thin film transistor display panel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137825A (en) * | 1988-11-18 | 1990-05-28 | Sharp Corp | Active matrix substrate |
| JP2015130453A (en) * | 2014-01-09 | 2015-07-16 | 株式会社Ｊｏｌｅｄ | Thin-film transistor, display device, and electronic apparatus |
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