JPH0990405A - Thin-film transistor - Google Patents

Thin-film transistor

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Publication number
JPH0990405A
JPH0990405A JP24347995A JP24347995A JPH0990405A JP H0990405 A JPH0990405 A JP H0990405A JP 24347995 A JP24347995 A JP 24347995A JP 24347995 A JP24347995 A JP 24347995A JP H0990405 A JPH0990405 A JP H0990405A
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Prior art keywords
gate electrode
tft
lower
lower gate
thin film
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JP24347995A
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Japanese (ja)
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Masahiro Fujiwara
正弘 藤原
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Sharp Corp
シャープ株式会社
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Priority to JP24347995A priority Critical patent/JPH0990405A/en
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Abstract

PROBLEM TO BE SOLVED: To prevent the increase in off current by light incidence and to lessen the adverse influence of the capacitors by light shielding films on images. SOLUTION: Upper gate electrodes 106, 107 and lower gate electrodes 102 are formed via insulating films 103, 105 above and below a semiconductor thin film having channel regions 104, source regions and drain regions 112. The lower gate electrodes 102 overlap at least partly on the adjacent upper gate electrodes 106, 107 and do not overlap on the source regions and drain regions 111, 112. An impurity of the same conduction type as the conduction type of the source regions and drain regions 111, 112 may be introduced into the parts 114 on the lower electrodes of the semiconductor thin film. The upper gate electrodes 106, 107 and the lower gate electrodes 102 may be connected to the same signal lines and the specified voltage may be impressed on the lower gate electrodes 102.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、たとえばアクティブマトリックス型液晶パネル(以下、AMLCDと称する)にマトリックス状に設けられた画素のオンオフを制御するスイッチング素子として好適に用いられる薄膜トランジスタに関する。 The present invention relates, for example an active matrix type liquid crystal panel for a thin film transistor suitably used as a switching element for controlling on and off of pixels provided in a matrix (hereinafter, referred to as AMLCD).

【0002】 [0002]

【従来の技術】近年、多結晶シリコン(以下、p−Si In recent years, polycrystalline silicon (hereinafter, p-Si
と称する)を半導体層に用いた薄膜トランジスタ(以下、TFTと称する)に関する研究が活発に行われている。 Referred to as) a thin film transistor (hereinafter used for the semiconductor layer, research has been actively carried out regarding called TFT). このp−Si・TFTを上述した画素用のスイッチング素子として用いたAMLCDにおいては、ドライバ回路を同一基板上に形成することが可能であり、コスト低減、基板サイズの縮小化等の効果が期待できる。 In the AMLCD using the p-Si · TFT as a switching element for pixel described above, it is possible to form the driver circuit on the same substrate, cost reduction, it can effectively be expected reduction of the substrate size . また、上記p−Si・TFTにおいては、ゲート電極をマスクとしてイオン注入を行うことにより、ゲート電極とソース領域およびドレイン領域とを自己整合的に作製することが可能となる。 In the above p-Si · TFT, by ion implantation using the gate electrode as a mask, it is possible to manufacture a gate electrode and a source region and a drain region in a self-aligned manner. このため、p−Si・TFTを画素のスイッチング素子として用いた場合に、画素電極とゲート電極との間の容量結合による画素信号の変動を抑えることができる。 Therefore, in the case of using p-Si · TFT as a switching element of a pixel, it is possible to suppress the fluctuation of the pixel signals by capacitive coupling between the pixel electrode and the gate electrode.

【0003】しかし、画素のスイッチング素子としてp [0003] However, p as a switching element of a pixel
−Si・TFTを用いた場合には、非晶質シリコン(以下、a−Si:Hと称する)を半導体層に用いたa−S In the case of using the -Si · TFT is amorphous silicon (hereinafter, a-Si: referred to as H) was used in the semiconductor layer a-S
i:H・TFTに比べてオフ電流が高く、特に、ソース−ドレイン電圧が高くなると、急激にオフ電流が増加するという問題がある。 i: high off current than H · TFT, in particular, the source - drain voltage rises rapidly there is a problem that the off current is increased. このような現象が生じる理由は、 The reason for such a phenomenon occurs,
ソースードレイン電圧が高くなると、ドレイン端の電界強度が強くなって、欠陥準位を介したトンネル電流や熱励起電流等が流れるためであると一般に説明されている。 When the source-drain voltage is increased, the electric field intensity at the drain end is strong, are generally described If it is to flow like a tunnel current or thermal excitation current through the defect levels.

【0004】この問題を解決するために、例えば図10 [0004] In order to solve this problem, for example, FIG. 10
に示すような複数のゲート電極205、206を有するデュアルゲート構造のTFTが提案されている(特公平5−44195号)。 TFT dual-gate structure has been proposed having a plurality of gate electrodes 205, 206 as shown in (Kokoku No. 5-44195). また、図11に示すようなオフセット領域またはLDD(Lightly Doped Further, an offset region or LDD as shown in FIG. 11 (Lightly Doped
Drain)領域213aを有するオフセット構造またはLDD構造のTFTが提案されている(特公平3−3 TFT of offset structure or an LDD structure having Drain) regions 213a has been proposed (KOKOKU 3-3
4699号)。 No. 4699). さらに、図12に示すようなデュアルゲートのオフセット構造またはLDD構造のTFTが提案されている(特開平2−135780号)。 Furthermore, TFT of offset structure or an LDD structure of a dual-gate as shown in FIG. 12 has been proposed (Japanese Patent Laid-Open No. 2-135780). 尚、これらの図において、201はガラス基板、202は絶縁膜、 In these figures, the glass substrate 201, 202 is an insulating film,
203はチャンネル領域、204はゲート絶縁膜、20 203 channel region 204 is a gate insulating film, 20
5および206はゲート電極、207は層間絶縁膜、2 5, 206 gate electrode, 207 denotes an interlayer insulating film, 2
08および209はソース電極およびドレイン電極、2 08 and 209 the source and drain electrodes, 2
10、211および213はソース領域およびドレイン領域、213aはオフセット領域またはLDD領域を示す。 10,211 and 213 source and drain regions, 213a denotes an offset region or LDD region.

【0005】このように複数のゲート電極205、20 [0005] a plurality of gate electrodes thus 205,20
6を設けた構造では、ソース−ドレイン電圧が個々のゲート電極に対応したTFTに分割されるので、オフ電流が低減される。 In the structure in which the 6, source - the drain voltage is divided into TFT corresponding to each of the gate electrode, the off current is reduced. また、オフセット領域またはLDD領域213aを設けた構造では、ソース−ドレイン電圧がオフセット領域またはLDD領域に分散されるので、電界強度が減少してオフ電流が低減される。 Further, in the structure provided with an offset region or LDD region 213a, the source - the drain voltage is dispersed in the offset region or LDD region, the electric field intensity is off-current is reduced to decrease. オフセット構造またはLDD構造では、ソース−ドレイン抵抗が増大してオン電流が減少するという欠点もあるが、p−Si・ An offset structure or an LDD structure, the source - the drain resistance is a disadvantage in that the on-current is reduced by increasing, p-Si ·
TFTでは移動度が高いので問題が生じない。 Problem does not occur because of the high mobility of the TFT.

【0006】 [0006]

【発明が解決しようとする課題】一般に、トップゲート構造のTFTには、基板裏面からの光入射により光伝導が生じて、オフ電流が増加するという問題がある。 Generally [0007], the TFT of the top gate structure, the light conduction caused by light incident from the back surface of the substrate, there is a problem that the off current is increased. 従来のa−Si:H・TFTでは、一般に逆スタガ構造が採用されるので、ゲート電極が自動的に遮光膜となって、 Conventional a-Si: The H · TFT, since generally inverted staggered structure is employed, the gate electrode becomes automatically shielding film,
問題は生じない。 There is no problem. しかし、トップゲート構造を採用した場合には、このような光入射によるオフ電流の増加という問題が生じる。 However, in the case of employing the top gate structure, the problem of an increase in the off current due to such light incident occurs.

【0007】この問題を解決するために、トップゲート構造のTFTでは、図13に示すように、チャンネル領域304の下側に、絶縁膜303を介してゲート電極3 [0007] To solve this problem, in the TFT of the top gate structure, as shown in FIG. 13, the lower side of the channel region 304, a gate electrode 3 through the insulating film 303
06よりも大きい形状の遮光膜302を形成することが一般的に行われている。 It is common practice to form a light-shielding film 302 of the shape larger than 06. この場合は、プロセス温度の関係から遮光膜として金属を用いることが多いので、図1 In this case, it is often to use metal as a light shielding film from the process temperature relationship, Figure 1
3および図14に示すように、ソース領域およびドレイン領域310、311と遮光膜302との間に寄生容量312、313が発生する。 As shown in 3 and 14, the parasitic capacitance 312 and 313 is generated between the source and drain regions 310 and 311 and the light shielding film 302. このため、遮光膜302をゲートバスラインやソースバスライン等と接続すると、 Therefore, when the light shielding film 302 is connected to the gate bus lines and source bus lines, etc.,
バスラインの電圧変化がこの寄生容量を介して画素電圧の変動をもたらすことになり、画像に悪影響を与えるという問題がある。 The voltage change of the bus line will be result in variation of the pixel voltage through the parasitic capacitance, there is a problem that adversely affects the image. 尚、この図13において、301はガラス基板、302は遮光膜、303は絶縁膜、304はチャンネル領域、305はゲート絶縁膜、306はゲート電極、307は層間絶縁膜、308および309はソース領域およびドレイン電極、310および311はソース領域およびドレイン領域、312および313は寄生容量を示す。 Incidentally, in this FIG. 13, 301 denotes a glass substrate, the light shielding film 302, 303 is an insulating film, the channel region 304, the gate insulating film 305, 306 is a gate electrode, 307 denotes an interlayer insulating film, a source region 308 and 309 and drain electrodes, 310 and 311 are source and drain regions, the 312 and 313 show the parasitic capacitance.

【0008】本発明は、このような従来技術の課題を解決すべくなされたものであり、光入射によるオフ電流の増加を防ぐことができ、遮光膜による寄生容量が画像に悪影響を及ぼすのを防ぐことができる薄膜トランジスタ(TFT)を提供することを目的とする。 [0008] The present invention has such directed to solve the problems of the prior art, it is possible to prevent an increase in off current due to light incident, a parasitic capacitance due to light-shielding film from adversely affecting the image and to provide a thin film transistor (TFT) can be prevented.

【0009】 [0009]

【課題を解決するための手段】本発明の薄膜トランジスタは、チャンネル領域の両側にソース領域とドレイン領域とを有する半導体薄膜の該チャンネル領域を挟んで一方側に、絶縁膜を介して2以上の上部ゲート電極が形成され、他方側に絶縁膜を介して1以上の下部ゲート電極が、各下部ゲート電極の両端部を相互に隣接する上部ゲート電極の各々に対して重畳させて形成され、そのことにより上記目的が達成される。 The thin film transistor of the present invention In order to achieve the above object, according to one side across the channel region of a semiconductor thin film having a source region and a drain region on opposite sides of the channel region, two or more upper via the insulating film a gate electrode is formed on the other side via the insulating film is 1 or more lower gate electrode is formed by superposing on each of the upper gate electrode adjacent the opposite ends of each of the lower gate electrode from each other, that the the above-mentioned object can be achieved by.

【0010】本発明の薄膜トランジスタにおいて、前記半導体薄膜の前記上部ゲート電極とは重畳しない部分に、前記ソース領域およびドレイン領域に導入されている不純物と同じ導電型の不純物が該ソース領域およびドレイン領域よりも低濃度に導入されている構成とすることができる。 [0010] In the thin film transistor of the present invention, the said portion not overlapping the upper gate electrode of the semiconductor thin film, an impurity of the same conductivity type as the impurity introduced into the source region and the drain region than the source region and the drain region it can also be configured to be introduced into the low concentration.

【0011】本発明の薄膜トランジスタにおいて、前記上部ゲート電極および下部ゲート電極が同一の信号線に接続されている構成、または前記下部ゲート電極に一定の電圧が印加されている構成とすることができる。 [0011] In the thin film transistor of the present invention, may be configured to the configuration upper gate electrode and the lower gate electrode are connected to the same signal line, or a constant voltage to the lower gate electrode is applied.

【0012】以下に、本発明の作用について説明する。 [0012] The following is a description of the operation of the present invention.

【0013】本発明にあっては、半導体薄膜を挟んで2 [0013] In the present invention, 2 across the semiconductor thin film
以上の上部ゲート電極と1以上の下部ゲート電極とが形成され、各下部ゲート電極の両端部が相互に隣接する上部ゲート電極の各々に対して重畳している。 More the upper gate electrode and one or more lower gate electrode is formed, both ends of each of the lower gate electrode are overlapped with respect to each of the upper gate electrode adjacent to each other. この構造により、ソース−ドレイン電圧が各々のゲート電極に対応したTFTに分散され、これによりオフ電流が低減される。 This structure, the source - drain voltage is distributed to the TFT corresponding to the gate electrode of each, which off-current is reduced.

【0014】また、MIS型TFTでは、キャリアがゲート電極に近い絶縁膜の界面に形成されるので、下部ゲート電極で構成されるTFTと、上部ゲート電極で構成されるTFTの間では、チャンネル領域の膜厚方向の中央部が空乏化する。 Further, the MIS-type TFT, the carrier is formed at the interface of the insulating film near the gate electrode, the TFT composed of a lower gate electrode, between the TFT composed of the upper gate electrode, the channel region central portion in the thickness direction is depleted of. その結果、さらにオフ電流が低減される。 As a result, further off-current is reduced.

【0015】さらに、光が基板裏面から入射しても、下部ゲート電極で構成されるTFTが下部ゲート電極の陰になるので、光電流の発生が抑えられる。 Furthermore, even if the light is incident from the substrate backside, the TFT composed of a lower gate electrode is the shadow of the lower gate electrode, the generation of the photocurrent is suppressed.

【0016】また、上部ゲート電極とソース領域およびドレイン領域とは自己整合的に形成でき、下部ゲート電極はソース領域およびドレイン領域と重ならないので、 Further, the upper gate electrode and the source and drain regions can self-aligned manner, since the lower gate electrode does not overlap with the source and drain regions,
画素電極とゲート電極との容量結合による画素電圧の変動が抑制される。 Variation of the pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode can be suppressed.

【0017】半導体薄膜の上部ゲート電極とは重畳しない部分に、ソース領域およびドレイン領域と同じ導電型の不純物を低濃度に導入すると、下部ゲート電極がオフレベルになった時に、半導体薄膜の下部ゲート電極上の部分が空乏化され、さらにオフ電流の低減を図ることができる。 [0017] portion not overlapping the upper gate electrode of the semiconductor thin film, the introduction of the same conductivity type impurity and a source region and a drain region in a low concentration, when the lower gate electrode is turned off level, the lower gate of the semiconductor thin film portion of the electrode is depleted, it is possible to further reduce the off current. このLDD領域は、上部ゲート電極をマスクとして不純物導入を行うことにより、注入領域を正確に制御できる。 The LDD region, by performing the impurities introduced upper gate electrode as a mask, can be accurately controlled injection region.

【0018】上部ゲート電極および下部ゲート電極は、 The upper gate electrode and the lower gate electrode,
同一の信号線に接続してもよく、下部ゲート電極に一定の電圧を印加してもよい。 May be connected to the same signal line may be a constant voltage is applied to the lower gate electrode. 下部ゲート電極に一定の電圧を印加する場合には、全体として最もオンオフ比が高くなるように電圧を印加する。 When applying a constant voltage to the lower gate electrode, a voltage is applied so that the most-off ratio is increased as a whole. この場合、下部ゲート電極と上部ゲート電極とを接続する必要が無い。 In this case, it is not necessary to connect the lower gate electrode and an upper gate electrode.

【0019】 [0019]

【実施形態】以下、本発明の実施形態について、図面を参照しながら説明する。 [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0020】本実施形態のTFTは、例えば図1(a) [0020] TFT of the present embodiment, for example, FIGS. 1 (a)
に示すように、ガラス基板101上に、チャンネル領域104、ソース領域およびドレイン領域111、112 As shown in, on a glass substrate 101, the channel region 104, a source region and a drain region 111, 112
を有する半導体薄膜が形成され、その上下に、絶縁膜1 The semiconductor thin film having is formed on the upper and lower insulating film 1
03、105を介して上部ゲート電極106、107および下部ゲート電極102が形成されている。 Upper gate electrodes 106 and 107 and the lower gate electrode 102 is formed through a 03,105. 下部ゲート電極102はソース領域およびドレイン領域111、 Lower gate electrode 102 is a source region and a drain region 111,
112と重なっておらず、また、その一部は、隣接する上部ゲート電極106、107と重なっている。 112 and not without overlap, and a portion thereof overlaps the adjacent upper gate electrodes 106 and 107. その上には、上部ゲート電極106、107を覆うように層間絶縁膜108が形成され、絶縁膜105および層間絶縁膜108に形成されたコンタクトホールを介して、ソース電極およびドレイン電極109、110がソース領域およびドレイン領域111、112に接続されている。 On its interlayer insulating film 108 is formed so as to cover the upper gate electrode 106 and 107, through a contact hole formed in the insulating film 105 and the interlayer insulating film 108, a source electrode and a drain electrode 109, 110 It is connected to the source and drain regions 111 and 112.

【0021】この構造によれば、従来の複数ゲート電極を有するTFTと同様に、ソース−ドレイン電圧が個々のゲート電極に対応したTFTに分割されるので、オフ電流が低減される。 According to this structure, similar to the TFT having a conventional multiple gate electrodes, the source - the drain voltage is divided into TFT corresponding to each of the gate electrode, the off current is reduced.

【0022】本実施形態の構造をMIS型TFTに適用した場合には、キャリアがそれぞれのゲート電極に近い絶縁膜の界面に形成され、例えばNch TFTのオフ状態では、図1(b)に示すように、正孔が絶縁膜10 [0022] The structure of this embodiment when applied to the MIS-type TFT, the carrier is formed at the interface of the insulating film closer to the gate electrode, for example, in the off state of the Nch TFT, shown in FIG. 1 (b) as such, holes insulating film 10
3、105とチャンネル領域104との界面に形成される。 It is formed at the interface between 3,105 and the channel region 104. このため、中央の下部ゲート電極102で構成されるTFTと、両端の上部ゲート電極106、107で構成されるTFTの間で、チャンネル領域104の膜厚方向の中央部113が空乏化する。 Therefore, a TFT formed at the center of the bottom gate electrode 102, between the TFT composed of upper gate electrodes 106 and 107 at both ends, the thickness direction of the central portion 113 of the channel region 104 is depleted. その結果、膜厚分のオフセット領域が形成されることになり、さらにオフ電流が低減される。 As a result, the offset region of the thickness fraction is formed, further off-current is reduced. また、本実施形態においては、図2 Further, in the present embodiment, FIG. 2
(c)に示すように、光が基板裏面から入射する場合、 (C), the case where light is incident from the back surface of the substrate,
下部ゲート電極102で構成されるTFTが下部ゲート電極102の陰になる。 TFT composed of the lower gate electrode 102 is behind the lower gate electrode 102. このため、チャンネル104での正孔−電子対の発生が抑えられ、オフ電流の増加を防ぐことができる。 Thus, holes in the channels 104 - generation of electron pairs can be suppressed to prevent an increase in off-current. 光が基板表面から入射する場合には、 If the light is incident from the substrate surface,
従来のトップゲート構造のTFTと同様に、上部ゲート電極106、107により遮光することができる。 Like the TFT of a conventional top-gate structure, it can be shielded by the upper gate electrode 106 and 107.

【0023】また、本実施形態においては、上部ゲート電極105、106とソース領域およびドレイン領域1 Further, in the present embodiment, the upper gate electrode 105 and the source region and the drain region 1
11、112とは自己整合的に形成することができ、かつ、下部ゲート電極102はソース領域およびドレイン領域111、112と重ならないので、画素電極とゲート電極との容量結合による画素電圧の変動が抑制され、 The 11,112 can be formed in a self-aligned manner, and, since the lower gate electrode 102 does not overlap with the source and drain regions 111 and 112, the variation of the pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode is suppressed,
画像への悪影響が少なくなる。 Adverse effect on the image is reduced.

【0024】さらに、図2(d)に示すように、半導体薄膜の下部電極102上の部分114に、ソース領域およびドレイン領域111、112と同じ導電型の不純物を低濃度に導入すると、下部ゲート電極102がオフレベルになった時に、チャンネル領域104にソース領域およびドレイン領域111、112と反対導電型のキャリアが発生するのを防ぐことができる。 Furthermore, as shown in FIG. 2 (d), the portion 114 on the lower electrode 102 of the semiconductor thin film, the introduction of the same conductivity type impurity source and drain regions 111 and 112 to a low concentration, the lower gate when the electrode 102 is turned off level, opposite conductivity type carriers the source and drain regions 111 and 112 in the channel region 104 can be prevented from occurring. その結果、半導体薄膜の下部ゲート電極102上の部分114を空乏化して実質的に高抵抗とすることができ、オフ電流の低減を図ることができる。 As a result, the portion 114 on the lower gate electrode 102 of the semiconductor thin film is depleted can be substantially high resistance, it is possible to reduce the off current. また、従来のLDD構造と同様に、ソース−ドレイン電圧がLDD領域に分散されことによっても、オフ電流が低減される。 Also, as in the conventional LDD structure, the source - drain voltage also by being dispersed in the LDD region, off-current is reduced. このLDD領域1 The LDD region 1
14は、上部ゲート電極106、107をマスクとして不純物導入を行うことにより、注入領域を正確に制御でき、容易に作製することができる。 14, by performing the impurities introduced upper gate electrode 107 as a mask, the implanted region can be accurately controlled, it can be easily manufactured. 上部ゲート電極10 Upper gate electrode 10
5、106および下部ゲート電極102は、同一の信号線に接続して使用することもでき、下部ゲート電極10 5,106 and lower gate electrode 102 may also be used to connect to the same signal line, the lower gate electrode 10
2に一定の電圧が印加されるようにしてもよい。 May be a constant voltage is applied to two. 下部ゲート電極102に一定の電圧を印加する場合には、全体として最もオンオフ比が高くなるような電圧を印加する。 When applying a constant voltage to the lower gate electrode 102 applies a voltage such that the most off ratio is increased as a whole. この場合、下部ゲート電極102と上部ゲート電極105、106とを接続する必要が無いので、プロセスの簡略化を図ることができる。 In this case, it is not necessary to connect the lower gate electrode 102 and the upper gate electrode 105 and 106, it is possible to simplify the process.

【0025】ここでは、1つの下部ゲート電極102と2つの上部ゲート電極105、106を有する構成について説明したが、下部ゲート電極が1以上で上部ゲート電極が2以上の構成としてもよい。 [0025] Here has been described the configuration having one lower gate electrode 102 and the two upper gate electrode 105 and 106, the lower gate electrode may be two or more configurations upper gate electrode with one or more. この場合にも、同様の効果が得られることはもちろんである。 In this case, the same effect can be obtained of course. また、Nch In addition, Nch
TFTについて説明したが、Pch TFTについても同様である。 It was described TFT, but the same is true for Pch TFT.

【0026】 [0026]

【実施例】以下、本発明の具体的な実施例について説明する。 BRIEF DESCRIPTION specific examples of the present invention.

【0027】(実施例1)図4(g)に本実施例1のT [0027] (Example 1) FIG. 4 (g) to the first embodiment T
FTの断面図を示す。 It shows a cross-sectional view of FT.

【0028】このTFTは、ガラス基板401上に、p [0028] The TFT is, on a glass substrate 401, p
−Siからなる半導体薄膜404が形成され、その上下に、絶縁膜403、405を介して上部ゲート電極40 The semiconductor thin film 404 is formed consisting of -Si, above and below, the upper gate electrode 40 through the insulating film 403 and 405
6、406および下部ゲート電極402が形成されている。 6,406 and lower gate electrode 402 is formed. 下部ゲート電極402はソース領域およびドレイン領域と重なっておらず、また、その一部は、隣接する上部ゲート電極406、406と重なっている。 Lower gate electrode 402 is not overlapped with the source and drain regions, also, some of which overlap with the adjacent upper gate electrode 406, 406. その上には、上部ゲート電極406、406を覆うように層間絶縁膜408が形成され、絶縁膜405および層間絶縁膜408に形成されたコンタクトホールを介して、ソース電極およびドレイン電極409、409がソース領域およびドレイン領域に接続されている。 On top of them, an interlayer insulating film 408 is formed so as to cover the upper gate electrode 406, 406, through a contact hole formed in the insulating film 405 and the interlayer insulating film 408, a source electrode and a drain electrode 409,409 is It is connected to the source and drain regions.

【0029】このTFTの作製方法を図3および図4に従って説明する。 [0029] illustrating a manufacturing method of the TFT according to FIGS.

【0030】まず、図3(a)に示すように、ガラス基板401上にTa膜を成膜し、これをパターニングして下部ゲート電極402を形成する。 First, as shown in FIG. 3 (a), a Ta film was deposited on a glass substrate 401, to form a lower gate electrode 402 and patterned to.

【0031】次に、図3(b)に示すように、厚み30 Next, as shown in FIG. 3 (b), the thickness 30
0nmのSiO 2膜をAPCVD(常圧化学気相成長) APCVD an SiO 2 film of 0nm (atmospheric pressure chemical vapor deposition)
法により成膜し、下部ゲート電極402に対応したゲート絶縁膜403を形成する。 Deposited by law, to form a gate insulating film 403 corresponding to the lower gate electrode 402.

【0032】続いて、図3(c)に示すように、厚み5 [0032] Subsequently, as shown in FIG. 3 (c), the thickness 5
0nmのp−Si膜をLPCVD(減圧化学気相成長) LPCVD the p-Si film of 0nm (low pressure chemical vapor deposition)
法により成膜し、これをパターニングして半導体薄膜4 Formed by law, the semiconductor thin film 4 by patterning the
04を形成する。 04 to form a.

【0033】その後、図3(d)に示すように、厚み1 [0033] Thereafter, as shown in FIG. 3 (d), the thickness 1
00nmのSiO 2膜をAPCVD法により成膜し、上部ゲート電極に対応したゲート絶縁膜405を形成する。 The SiO 2 film of 00nm is deposited by APCVD method to form the gate insulating film 405 corresponding to the upper gate electrode.

【0034】次に、図4(e)に示すように、その上にTa膜を成膜し、これをパターニングして上部ゲート電極406、406を形成する。 [0034] Next, as shown in FIG. 4 (e), forming a Ta film thereon and patterned to form the upper gate electrode 406, 406.

【0035】続いて、図4(f)に示すように、中央の下部ゲート電極402に対応したチャンネル領域をレジスト407により保護して、イオン注入法によりリンイオンを1×10 15 cm -2 、90kVで注入する。 [0035] Subsequently, as shown in FIG. 4 (f), a channel region corresponding to the center of the lower gate electrode 402 and protected by resist 407, 1 × 10 15 cm -2 phosphorus ions by ion implantation, 90 kV in the injection. レジストを除去した後、活性化アニールを600℃で20時間行う。 After removing the resist, performing 20 hours activation annealing at 600 ° C..

【0036】さらに、図4(g)に示すように、厚み4 Furthermore, as shown in FIG. 4 (g), thickness 4
00nmのSiO 2膜をAPCVD法により成膜して層間絶縁膜408を形成後、コンタクトホールを形成し、 The SiO 2 film of 00nm was deposited by APCVD method after forming the interlayer insulating film 408, contact holes are formed,
Al電極を形成してソース電極およびドレイン電極40 A source electrode and a drain electrode to form the Al electrode 40
9、409とする。 And 9,409.

【0037】この実施例では、上部ゲート電極長L1、 [0037] In this embodiment, the upper gate electrode length L1,
L2を各々4μm、上部ゲート電極間を3μm、下部ゲート電極長L3を7μm、重なり領域を各々2μmとし、チャンネル幅は3μmとした。 Each 4μm and L2, 3 [mu] m between the upper gate electrode, 7 [mu] m the lower gate electrode length L3, and each overlapping region 2 [mu] m, the channel width was 3 [mu] m.

【0038】図5(a)および(b)に、本実施例1のTFTについて、下部ゲート電極402を上部ゲート電極406に接続した場合のドレイン電流−ゲート電圧(I D −V G )曲線を示す。 [0038] FIGS. 5 (a) and (b), the TFT of the embodiment 1, the drain current in the case of connecting the bottom gate electrode 402 to the upper gate electrode 406 - the gate voltage (I D -V G) curve show. 左側の図5(a)のグラフは暗時を示し、右側の図5(b)のグラフは基板裏面からの2000lxの光照射時を示す。 Graph of the left 5 (a) shows the dark, the graph on the right side of FIG. 5 (b) shows the time of light irradiation 2000lx from the substrate back surface. また、通常のデュアルゲート構造のTFTを比較例として同図に点線で示した。 Further, it indicated by a dotted line in the drawing as a comparative example a conventional dual gate structure TFT. 比較例のTFTは、下部ゲート電極402の作製工程がないこと、およびイオン注入工程で中央の下部ゲート電極402に対応したチャンネル領域をレジスト40 TFT of the comparative example, there is no manufacturing process of the lower gate electrode 402, and the resist 40 a channel region corresponding to the center of the lower gate electrode 402 by ion implantation step
7で保護しなかったこと以外は実施例1のTFTと同様にして作製した。 Except that did not protected 7 was produced in the same manner as the TFT of Example 1.

【0039】この図5(a)および(b)によれば、暗時のオフ電流については、本実施例1のTFTと比較例のTFTとで、あまり差が見られない。 [0039] According to FIGS. 5 (a) and (b), for the off-current of the dark, in a TFT of the comparative example to the TFT of the embodiment 1, not seen so much difference. しかし、基板裏面から光を2000lx照射した時には、本実施例1のTFTではオフ電流の増加が殆ど見られないが、比較例のTFTでは1桁程度のオフ電流の増加が見られる。 However, the light from the substrate backside when 2000lx irradiation is increased TFT in the off-state current of the first embodiment is hardly observed, increase in off-current of 1 order of magnitude in the TFT of the comparative example is observed. このように、本実施例1の構造は、光入射時のオフ電流の低減に非常に有効である。 Thus, the structure of the present embodiment 1 is extremely effective in reducing the off current when the light incidence.

【0040】また、図5(c)に、本実施例1のTFT Further, in FIG. 5 (c), of the embodiment 1 TFT
について、下部ゲート電極402を上部ゲート電極40 For, upper gate electrode 40 of the lower gate electrode 402
6に接続しないで独立して変化させた場合の(I D In the case of independently varying without connecting to 6 (I D -
G )曲線を示す。 It shows the V G) curve. この図5(c)によれば、下部ゲート電極402の電圧V G 2を正方向に高くしていくと、 According to FIG. 5 (c), when gradually increasing the voltage V G 2 of the lower gate electrode 402 in the positive direction,
中央の下部ゲート電極402に対応したTFTがオン状態になるので、オン電流は増加する。 Since the center of the TFT corresponding to the lower gate electrode 402 is turned on, the on-current is increased. しかし、この場合、下部ゲート電極402に対応したTFTが単なる抵抗体に近付くので、若干オフ電流が増加する。 However, in this case, TFT corresponding to the lower gate electrode 402 is so close to the mere resistor, slightly off-current increases. 一方、下部ゲート電極402の電圧V G 2を負方向に高くしていくと、中央の下部ゲート電極402に対応したTFTがオフ状態になるので、オン電流は減少するが、オフ電流も減少する。 On the other hand, when gradually increasing the voltage V G 2 of the lower gate electrode 402 in the negative direction, since TFT corresponding to the center of the lower gate electrode 402 is turned off, but ON current is reduced, the off current is also decreased .

【0041】図5(d)に、本実施例1のTFTについて、オンオフ比のV G 2依存性を示す。 [0041] in FIG. 5 (d), of the TFT according to the first embodiment, showing the V G 2-dependent on-off ratio. 尚、オンオフ比は、V G =10V時とV G =−10V時とのドレイン電流の比で定義した。 Incidentally, the on-off ratio was defined as the ratio of the drain current of the at V G = 10V at a V G = -10V. この図5(d)によれば、本実施例1 According to FIG. 5 (d), the present embodiment 1
のTFTでは、V G 2が約−2V程度で最もオンオフ比が高くなっている。 In the TFT, V G 2 has the largest on-off ratio is higher in the order of about -2 V. 従って、下部ゲート電極402にV Therefore, V on the lower gate electrode 402
G 2=−2Vの電圧を印加することにより、最も良好な特性が得られると考えられる。 By applying a voltage of G 2 = -2 V, considered to be the most favorable characteristics can be obtained. 尚、この値は、p−Si Note that this value, p-Si
やゲート絶縁膜の作製方法やサイズ等により変化することは言うまでもない。 It goes without saying that changes according to the manufacturing method and sizes of and the gate insulating film.

【0042】また、本実施例1のTFTを液晶表示装置のスイッチング素子として形成した場合、画素電極とゲート電極との容量結合による画素電圧の変動が抑制され、画像への悪影響は見られなかった。 Further, if the TFT of this Example 1 was formed as a switching element of a liquid crystal display device, variations in pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode is suppressed, adverse effects on the image was observed .

【0043】(実施例2)図8に本実施例2のTFTの断面図を示す。 [0043] illustrates a cross-sectional view of the TFT (Example 2) In this example in FIG. 82.

【0044】このTFTは、ガラス基板601上に、p [0044] The TFT is, on a glass substrate 601, p
−Siからなる半導体薄膜604が形成され、その上下に、絶縁膜603、605を介して上部ゲート電極60 The semiconductor thin film 604 is formed consisting of -Si, above and below, the upper gate electrode 60 through the insulating film 603, 605
6、606および下部ゲート電極602が形成されている。 6,606 and lower gate electrode 602 is formed. 半導体薄膜604の下部ゲート電極602上の部分610には、ソース領域およびドレイン領域と同じ導電型の不純物が低濃度に導入されている。 The portion 610 of the lower gate electrode 602 of the semiconductor thin film 604, an impurity of the same conductivity type as the source and drain regions are introduced at a low concentration. 下部ゲート電極602はソース領域およびドレイン領域と重なっておらず、また、その一部は、隣接する上部ゲート電極60 Lower gate electrode 602 is not overlapped with the source and drain regions, also, some of the upper gate adjacent electrodes 60
6、606と重なっている。 It overlaps with the 6,606. その上には、上部ゲート電極606、606を覆うように層間絶縁膜608が形成され、絶縁膜605および層間絶縁膜608に形成されたコンタクトホールを介して、ソース電極およびドレイン電極409、409がソース領域およびドレイン領域に接続されている。 On top of them, an interlayer insulating film 608 is formed so as to cover the upper gate electrode 606,606, through a contact hole formed in the insulating film 605 and the interlayer insulating film 608, a source electrode and a drain electrode 409,409 is It is connected to the source and drain regions.

【0045】このTFTの作製方法を図6、図7および図8に従って説明する。 [0045] illustrating a manufacturing method of the TFT 6 in accordance with FIGS.

【0046】まず、図6(a)に示すように、ガラス基板601上にTa膜を成膜し、これをパターニングして下部ゲート電極602を形成する。 [0046] First, as shown in FIG. 6 (a), a Ta film was deposited on a glass substrate 601, to form a lower gate electrode 602 and patterned to.

【0047】次に、図6(b)に示すように、厚み30 Next, as shown in FIG. 6 (b), the thickness 30
0nmのSiO 2膜をAPCVD法により成膜し、下部ゲート電極602に対応したゲート絶縁膜603を形成する。 The SiO 2 film of 0nm deposited by APCVD method to form the gate insulating film 603 corresponding to the lower gate electrode 602. 続いて、図6(c)に示すように、厚み50n Subsequently, as shown in FIG. 6 (c), the thickness 50n
mのp−Si膜をLPCVD法により成膜し、これをパターニングして半導体薄膜604を形成する。 The p-Si film of m was formed by the LPCVD method to form the semiconductor thin film 604 is patterned so.

【0048】その後、図6(d)に示すように、厚み1 [0048] Thereafter, as shown in FIG. 6 (d), the thickness 1
00nmのSiO 2膜をAPCVD法により成膜し、上部ゲート電極に対応したゲート絶縁膜605を形成する。 The SiO 2 film of 00nm is deposited by APCVD method to form the gate insulating film 605 corresponding to the upper gate electrode.

【0049】次に、図7(e)に示すように、その上にTa膜を成膜し、これをパターニングして上部ゲート電極606、606を形成する。 Next, as shown in FIG. 7 (e), forming a Ta film thereon and patterned to form the upper gate electrode 606,606.

【0050】続いて、図7(f)に示すように、イオン注入法によりリンイオンを1×10 12 cm -2 、90kV [0050] Subsequently, as shown in FIG. 7 (f), an ion implantation method, phosphorus ions 1 × 10 12 cm -2 by, 90 kV
で注入する。 In the injection.

【0051】その後、図7(g)に示すように、中央の下部ゲート電極602に対応したチャンネル領域をレジスト607により保護して、イオン注入法によりリンイオンを1×10 15 cm -2 、90kVで注入する。 [0051] Thereafter, as shown in FIG. 7 (g), a channel region corresponding to the center of the lower gate electrode 602 and protected by resist 607, 1 × 10 15 cm -2 phosphorus ions by ion implantation, in 90kV inject. レジストを除去した後、活性化アニールを600℃で20H行う。 After removing the resist, the activation annealing performed 20H at 600 ° C..

【0052】さらに、図8に示すように、厚み400n [0052] Further, as shown in FIG. 8, the thickness 400n
mのSiO 2膜をAPCVD法により成膜して層間絶縁膜608を形成後、コンタクトホールを形成し、Al電極を形成してソース電極およびドレイン電極609、6 The SiO 2 film of m was deposited by APCVD method after forming the interlayer insulating film 608, contact holes are formed, a source electrode and a drain electrode to form the Al electrode 609,6
09とする。 09 to be.

【0053】この実施例では、上部ゲート電極長L1、 [0053] In this embodiment, the upper gate electrode length L1,
L2を各々4μm、上部ゲート電極間を3μm、下部ゲート電極長L3を7μm、重なり領域を各々2μmとし、チャンネル幅は3μmとした。 Each 4μm and L2, 3 [mu] m between the upper gate electrode, 7 [mu] m the lower gate electrode length L3, and each overlapping region 2 [mu] m, the channel width was 3 [mu] m.

【0054】図9(a)および(b)に、本実施例2のTFTについて、下部ゲート電極602を上部ゲート電極606に接続した場合のドレイン電流−ゲート電圧(I D −V G )曲線を示す。 [0054] FIG. 9 (a) and 9 (b), the TFT of the second embodiment, the drain current in the case of connecting the bottom gate electrode 602 to the upper gate electrode 606 - the gate voltage (I D -V G) curve show. 左側の図9(a)のグラフは暗時を示し、右側の図9(b)のグラフは基板裏面からの2000lxの光照射時を示す。 Graph of the left 9 (a) shows the dark, the graph on the right side of FIG. 9 (b) shows the time of light irradiation 2000lx from the substrate back surface. また、実施例1のT Further, in Example 1 T
FTを点線で同図に示した。 The FT shown in FIG by a dotted line.

【0055】この図9(a)および(b)によれば、本実施例2のTFTは、実施例1のTFTに比べてオン電流が増加している。 [0055] According to FIG. 9 (a) and 9 (b), TFT of the second embodiment, the on-current as compared to the TFT of Example 1 is increased. これは、低濃度の不純物導入により、下部ゲート電極602に対応したTFTの閾値電圧が負方向にシフトしたためである。 This is because the introduction of impurities low concentration, because the threshold voltage of the TFT corresponding to the lower gate electrode 602 is shifted in the negative direction. また、V Gを十分負側にすることにより、下部ゲート電極602に対応したTFTのチャンネル領域が空乏層化するので、実施例1 Further, by making the V G sufficiently negative, since the channel region of the TFT corresponding to the lower gate electrode 602 is depleted, Example 1
のTFTに比べてオフ電流も低減している。 It has also reduced off-current than the TFT. さらに、光照射によるオフ電流の増加も見られない。 Furthermore, not also seen an increase in the off current due to light irradiation. このように、 in this way,
本実施例2の構造は、オフ電流の低減に非常に有効である。 Structure of this second embodiment is very effective in reducing the off current.

【0056】また、図9(c)に、本実施例2のTFT [0056] Further, in FIG. 9 (c), the present embodiment 2 TFT
について、下部ゲート電極602を上部ゲート電極60 For, upper gate electrode 60 of the lower gate electrode 602
6に接続しないで独立して変化させた場合の(I D In the case of independently varying without connecting to 6 (I D -
G )曲線を示す。 It shows the V G) curve. 本実施例2のTFTについても、実施例1のTFTと同様に、下部ゲート電極602の電圧V G 2を負方向に高くしていくにつれてオン電流は減少するが、オフ電流も減少するという傾向が見られた。 For the TFT even the second embodiment, similarly to the TFT of Example 1, a tendency that although on-current as going to a high voltage V G 2 of the lower gate electrode 602 in the negative direction decreases off current also decreases It was observed.

【0057】図9(d)に、本実施例2のTFTについて、オンオフ比のV G 2依存性を示す。 [0057] in FIG. 9 (d), of the TFT according to the second embodiment, showing the V G 2-dependent on-off ratio. 尚、オンオフ比は、実施例1と同様に定義した。 Incidentally, the on-off ratio was defined in the same manner as in Example 1. この図9(d)によれば、本実施例2のTFTでは、VG 2が約−7V程度で最もオンオフ比が高くなっている。 According to FIG. 9 (d), the the TFT of the second embodiment, the most off ratio VG 2 is at approximately -7V is high. 従って、下部ゲート電極602にV G 2=−7Vの電圧を印加することにより、最も良好な特性が得られると考えられる。 Therefore, by applying a voltage of V G 2 = -7V beneath the gate electrode 602, it is considered the most favorable characteristics can be obtained. 尚、この値についても、p−Siやゲート絶縁膜の作製方法やサイズ等により変化することは言うまでもない。 Note that this value also, it is needless to say that changes according to the manufacturing method and sizes of p-Si and the gate insulating film.

【0058】また、本実施例2のTFTも実施例1のT [0058] Further, TFT of this Example 2 also show Example 1 T
FTと同様に、液晶表示装置のスイッチング素子として形成した場合、画素電極とゲート電極との容量結合による画素電圧の変動が抑制され、画像への悪影響は見られなかった。 Like the FT, when formed as a switching element of a liquid crystal display device, variations in pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode is suppressed, adverse effects on the image was observed.

【0059】上記実施例1および2では、ゲート絶縁膜にAPCVD法によるSiO 2膜を、半導体層にLPC [0059] In Embodiment 1 and 2, the SiO 2 film by APCVD method gate insulating film, LPC on the semiconductor layer
VD法によるp−Si膜、ゲート電極にTaを用いたが、その他の作製法や材料を用いてもよい。 p-Si film by VD method, using Ta gate electrode, and may be other fabrication methods and materials. 例えば、ゲート絶縁膜の形成は、スパッタリング法やLPCVD For example, the formation of the gate insulating film, a sputtering method, LPCVD
法、PCVD法等により行うことができ、SiN膜やT Law, can be carried out by a PCVD method or the like, SiN film or a T
25膜、Al 23膜等を用いてもよい。 a 2 O 5 film, may be used an Al 2 O 3 film and the like. 上下の絶縁膜の膜厚やそれらの膜厚比も、p−Si膜や絶縁膜の膜質に応じて最適化することができる。 Thickness and their thickness ratio of the upper and lower insulating film can be optimized in accordance with the quality of the p-Si film or an insulating film. p−Si膜の形成は、LPCVD法やPCVD法によりa−Si膜を成膜した後、固相成長やレーザーアニール、ランプアニール等によりp−Si膜としてもよい。 Formation of p-Si film, after forming an a-Si film by the LPCVD method or a PCVD method, solid phase growth and laser annealing may be p-Si film by lamp annealing or the like. ゲート電極の材料としては、作製に耐える導電性材料であればいずれも用いることができる。 The gate electrode material, can be used, so long as the conductive material to withstand manufacturing. また、本発明より得られるTFT Further, TFT obtained from the present invention
は、AMLCDの画素用トランジスタや、他にイメージセンサのスイッチングトランジスタなど、様々な用途に適用することができる。 It is and pixel transistors for AMLCD, other like switching transistor of the image sensor, can be applied to various applications.

【0060】 [0060]

【発明の効果】以上の説明から明らかなように、本発明によればTFTのオフ電流を低減でき、光入射によるオフ電流の増加も防ぐことができる。 As apparent from the foregoing description, according to the present invention can reduce an off current of the TFT, it is possible to prevent an increase in the off current due to light incidence. また、このTFTを画素用スイッチング素子として用いると、画素電極とゲート電極との容量結合による画素電圧の変動が抑制され、画像への悪影響も生じない。 Moreover, the use of the TFT as a pixel switching element, the variation of the pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode is suppressed, no adverse effect on the image.

【0061】半導体薄膜の下部電極上の部分にLDD領域を形成すると、さらにオフ電流の低減を図ることができる。 [0061] When forming the LDD region in a portion of the lower electrode of the semiconductor thin film, it is possible to further reduce the off current. このLDD領域は、上部ゲート電極をマスクとして位置制御性良く形成することができる。 The LDD region may be located with good controllability forming an upper gate electrode as a mask.

【0062】上部ゲート電極および下部ゲート電極は、 [0062] The upper gate electrode and the lower gate electrode,
同一の信号線に接続してもよく、下部ゲート電極に一定の電圧を印加してもよい。 May be connected to the same signal line may be a constant voltage is applied to the lower gate electrode. 下部ゲート電極に一定の電圧を印加する場合には、全体として最もオンオフ比が高くなるように電圧を印加することにより、特性を良好することができる。 When applying a constant voltage to the lower gate electrode, by applying a voltage so that the most-off ratio is increased as a whole, it is possible to improve the properties. このように下部ゲート電極に一定の電圧を印加する場合には、下部ゲート電極と上部ゲート電極とを接続する必要が無く、さらにプロセスが簡略化できる。 If this applying a constant voltage to the lower gate electrode, as, it is not necessary to connect the lower gate electrode and the upper gate electrode, the process can be simplified.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】(a)および(b)は、本発明のTFTの一実施形態を示す断面図である。 [1] (a) and (b) is a sectional view showing an embodiment of a TFT of the present invention.

【図2】(c)および(d)は、本発明のTFTの一実施形態を示す断面図である。 Figure 2 (c) and (d) is a cross-sectional view showing an embodiment of a TFT of the present invention.

【図3】(a)〜(d)は、実施例1のTFTの製造工程を示す断面図である。 [3] (a) ~ (d) are cross-sectional views showing a manufacturing process of the TFT in Example 1.

【図4】(e)〜(g)は、実施例1のTFTの製造工程を示す断面図である。 [4] (e) ~ (g) are cross-sectional views showing a manufacturing process of the TFT in Example 1.

【図5】(a)〜(d)は、実施例1のTFTの特性を示すグラフである。 [5] (a) ~ (d) is a graph showing characteristics of the TFT in Example 1.

【図6】(a)〜(d)は、実施例2のTFTの製造工程を示す断面図である。 6 (a) ~ (d) are cross-sectional views showing a manufacturing process of the TFT in Example 2.

【図7】(e)〜(g)は、実施例2のTFTの製造工程を示す断面図である。 7 (e) ~ (g) are cross-sectional views showing a manufacturing process of the TFT in Example 2.

【図8】実施例2のTFTの製造工程を示す断面図である。 8 is a sectional view showing a manufacturing process of the TFT in Example 2.

【図9】(a)〜(d)は、実施例2のTFTの特性を示すグラフである。 9 (a) ~ (d) is a graph showing characteristics of the TFT in Example 2.

【図10】従来のオフ電流を低減したTFTを示す断面図である。 10 is a cross-sectional view of a conventional off-current reduced TFT with.

【図11】従来のオフ電流を低減した他のTFTを示す断面図である。 11 is a sectional view showing another TFT with reduced conventional off-current.

【図12】従来のオフ電流を低減した更に他のTFTを示す断面図である。 12 is a cross-sectional view showing still another TFT with reduced conventional off-current.

【図13】従来の遮光膜を形成したTFTを示す断面図である。 13 is a sectional view showing a forming a conventional light-shielding film TFT.

【図14】図13のTFTの等価回路である。 14 is an equivalent circuit of a TFT of FIG. 13.

【符号の説明】 DESCRIPTION OF SYMBOLS

101、401、601 ガラス基板 102、402、602 下部ゲート電極 103、403、603 下部ゲート電極に対応した絶縁膜 104 チャンネル領域 105、405、605 上部ゲート電極に対応した絶縁膜 106、107、406、606 上部ゲート電極 108、408、608 層間絶縁膜 109、110、409、609 ソース電極およびドレイン電極 111、112 ソース領域およびドレイン領域 113、114 空乏層領域 404、604 半導体層 407、607 レジスト 101,401,601 glass substrate 102,402,602 lower gate electrode 103,403,603 insulation corresponding to the lower gate electrode layer 104 channel regions 105,405,605 insulating film 106,107,406 corresponding to the upper gate electrode, 606 upper gate electrode 108,408,608 interlayer insulating film 109,110,409,609 source electrode and a drain electrode 111, 112 source and drain regions 113 and 114 depletion region 404, 604 semiconductor layers 407,607 resist

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 チャンネル領域の両側にソース領域とドレイン領域とを有する半導体薄膜の該チャンネル領域を挟んで一方側に、絶縁膜を介して2以上の上部ゲート電極が形成され、他方側に絶縁膜を介して1以上の下部ゲート電極が、各下部ゲート電極の両端部を相互に隣接する上部ゲート電極の各々に対して重畳させて形成されている薄膜トランジスタ。 To 1. A contrast across the channel region of a semiconductor thin film on both sides of the channel region and a source region and a drain region side, two or more upper gate electrode through the insulating film is formed, an insulating on the other side a thin film transistor 1 or more lower gate electrode via the film is formed by superposing on each of the upper gate electrode adjacent the opposite ends of each of the lower gate electrode to one another.
  2. 【請求項2】 前記半導体薄膜の前記上部ゲート電極とは重畳しない部分に、前記ソース領域およびドレイン領域に導入されている不純物と同じ導電型の不純物が該ソース領域およびドレイン領域よりも低濃度に導入されている請求項1に記載の薄膜トランジスタ。 To claim 2, wherein the portions not overlapping the upper gate electrode of the semiconductor thin film, the lower concentration than the impurity is the source and drain regions of the same conductivity type as the impurity introduced into the source region and the drain region the thin film transistor according to claim 1 that has been introduced.
  3. 【請求項3】 前記上部ゲート電極および下部ゲート電極が同一の信号線に接続されている請求項1または2に記載の薄膜トランジスタ。 3. The thin film transistor according to the upper gate electrode and the claim 1 or 2 lower gate electrode is connected to the same signal line.
  4. 【請求項4】 前記下部ゲート電極に一定の電圧が印加されている請求項1または2に記載の薄膜トランジスタ。 4. A thin film transistor according to claim 1 or 2 constant voltage is applied to the lower gate electrode.
JP24347995A 1995-09-21 1995-09-21 Thin-film transistor Withdrawn JPH0990405A (en)

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