JP2523679B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JP2523679B2 JP2523679B2 JP23010987A JP23010987A JP2523679B2 JP 2523679 B2 JP2523679 B2 JP 2523679B2 JP 23010987 A JP23010987 A JP 23010987A JP 23010987 A JP23010987 A JP 23010987A JP 2523679 B2 JP2523679 B2 JP 2523679B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- amorphous silicon
- region
- nitrogen
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 44
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 34
- 229910052757 nitrogen Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 2
- 239000010408 film Substances 0.000 description 33
- 229910004205 SiNX Inorganic materials 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 101100341032 Caenorhabditis elegans inx-5 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001782 photodegradation Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 この発明は半導体装置、特にその活性領域がシラン中
でのグロー放電によって形成された非晶質シリコンから
なり、その内に半導体接合を持った装置に関する。さら
に本発明は、ゲート絶縁膜として非晶質窒化シリコン
（ａ−SiNx）や非晶質酸化シリコン（ａ−SiOx）を用
い、活性層として非晶質シリコン（ａ−Si:H）を用いた
薄膜トランジスタ（TFT）を含む装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device having an active region made of amorphous silicon formed by glow discharge in silane and having a semiconductor junction therein. . Further, in the present invention, amorphous silicon nitride (a-SiNx) or amorphous silicon oxide (a-SiOx) is used as the gate insulating film, and amorphous silicon (a-Si: H) is used as the active layer. A device including a thin film transistor (TFT).
従来の技術 ａ−Si:Hを用いたTFTは200℃前後の比較的低温で大面
積にわたって容易に形成されるため、太陽電池、一次元
センサや、液晶ディスプレィに応用されるべく研究され
ている、ａ−Si:H膜によるTFTはそのｎチャンネルの良
好なトランジスタ特性のため、ON状態では、正バイアス
をゲート電極に加えるが、OFF状態ではアース電位と同
等の電位（零バイアス）で十分な動作をしていた。また
TFTのソース・ドレイン電極とｉ型のａ−Si:H膜との間
にはｎ型ａ−Si:H膜が通常形成されており、導電型を異
にする半導体接合を有していた。2. Description of the Related Art TFTs using a-Si: H are easily formed over a large area at a relatively low temperature of around 200 ° C. Therefore, they are being researched to be applied to solar cells, one-dimensional sensors, and liquid crystal displays. , A-Si: H film TFT has good transistor characteristics of its n-channel, so a positive bias is applied to the gate electrode in the ON state, but a potential equivalent to the ground potential (zero bias) is sufficient in the OFF state. It was working. Also
An n-type a-Si: H film is usually formed between the source / drain electrodes of the TFT and the i-type a-Si: H film, and has a semiconductor junction having a different conductivity type.
発明が解決しようとする問題点 しかし、前述したとおり、このTFTが応用される電子
素子は一次元センサや液晶ディスプレィ等強力な光を用
いる場合が多く、TFTにも一部その光が照射されるよう
な状態を取らざるを得なかった。ａ−Si:H膜は強力な光
が照射されると半導体としての特性が劣化することが知
られており、ステブラ、ロンスキ効果と一般に呼ばれて
いる。電界ストレスを加えると、この劣化現象が助長さ
れOFF電流が増加し、TFT特性を著しく悪化させた。電界
ストレスを加えて、即ち、ソース、ドレインにバイアス
を加え、電流を流すと、電界によって加速された電子
が、ソース、ドレイン金属膜電極とオーム接触を確保す
るｎ型ドープａ−Si:H膜中の弱いネットワークに歪を与
えたり、結合状態を切断し、TFTの活性領域であるａ−S
i:H膜との界面を損ない、この界面にキャリアが捕獲さ
れる準位が多数形成され、これがOFF電流増加の原因の
１つとなっていた。また、ａ−SiNxとａ−Si:H膜との超
格子の報告が最近なされ、その界面には大きなストレス
が観測されている。ストレスが存在すると、その界面に
は電荷が蓄積されることが知られている。However, as described above, the electronic element to which this TFT is applied often uses strong light such as a one-dimensional sensor or a liquid crystal display, and the TFT is also partially irradiated with the light, as described above. I had to take such a condition. It is known that the characteristics of the a-Si: H film as a semiconductor are deteriorated when it is irradiated with strong light, and it is generally called the Stepra and Ronski effect. When the electric field stress was applied, this deterioration phenomenon was promoted, the OFF current increased, and the TFT characteristics were significantly deteriorated. An n-type doped a-Si: H film that secures ohmic contact with the source and drain metal film electrodes by electrons accelerated by an electric field when electric field stress is applied, that is, a bias is applied to the source and drain, and a current is caused to flow. Strains the weak network inside or breaks the bonding state, which is the active region of TFT aS
The interface with the i: H film was damaged, and a large number of levels at which carriers were captured were formed at this interface, which was one of the causes of the increase in the OFF current. In addition, a superlattice of a-SiNx and a-Si: H film has been recently reported, and a large stress has been observed at the interface. It is known that in the presence of stress, charges are accumulated at the interface.
問題点を解決するための手段 本発明の半導体装置は、積層された非晶質窒化シリコ
ンから拡散された窒素を1015/cm3以上1019/cm3以下含む
n-型の導電型を持ち、約10-7秒あるいはそれ以上のキャ
リア寿命、約1017/cm3あるいはそれ以下のエネルギ・ギ
ャップ中の平均局在状態密度、および約10-3cm2/V・sec
あるいはそれ以上の電子に対する移動度を持つ非晶質シ
リコンの本体と、この本体よりも導電率をさらにｎ型に
変更する窒素以外のドープ材を含んでいるn-領域および
ｎ領域の複数のドープ領域とを有し、前記本体と前記n-
領域、および前記n-領域とｎ領域がそれぞれ半導体接合
を有するもので、望ましくはドープ領域が、導電率をさ
らにｎ型に変更する窒素以外のドープ材を1018/cm3より
も小さな濃度で含んでいる第１のドープ領域と上記ｎ型
に変更するドープ材を1018/cm3よりも大きな濃度で含ん
でいる第２のドープ領域を含む導電型を同じくする領域
とに分かれている。Means for Solving the Problems A semiconductor device of the present invention contains nitrogen diffused from stacked amorphous silicon nitride in an amount of 10 15 / cm 3 or more and 10 19 / cm 3 or less.
has n - type conductivity, has a carrier lifetime of about 10 -7 seconds or more, an average localized density of states in the energy gap of about 10 17 / cm 3 or less, and about 10 -3 cm 2 / V ・ sec
Or a body of amorphous silicon having a mobility for more electronic, the n contains dopants other than nitrogen to be changed more n-type conductivity than the body - a plurality of doped and n regions and a region, the said body n -
Region and said n - region and n-region each have a semiconductor junction, preferably the doped region contains a dopant other than nitrogen which further changes the conductivity to n-type at a concentration of less than 10 18 / cm 3. It is divided into a first doped region containing the same and a region having the same conductivity type including a second doped region containing the above-mentioned n-type converting dopant at a concentration higher than 10 18 / cm 3 .
本発明の製造方法は、活性領域とオーム接触を確保す
るn-型ドープ領域とｎ型ドープ領域の複数の領域を専用
堆積室で形成するに際し、n-領域の堆積には導電型を変
えるドープ材の導入を止めて形成し、然る後ドープ材を
導入してｎ領域形成し、ソース．ドレイン電極形成の工
程後、非晶質窒化シリコン膜積層状態のまま100℃から3
00℃で10分間から60分間の熱処理を加え、非晶質シリコ
ン中に窒素を1015/cm3以上1019/cm3以下拡散させる。According to the manufacturing method of the present invention, when forming a plurality of regions of the n − -type doped region and the n-type doped region for ensuring ohmic contact with the active region in a dedicated deposition chamber, the doping of changing the conductivity type is performed for the deposition of the n − region. The formation of the source is stopped by stopping the introduction of the material, and then the doping material is introduced to form the n region. After the process of forming the drain electrode, the amorphous silicon nitride film stacked state is maintained at 100 ° C to 3
A heat treatment is performed at 00 ° C. for 10 minutes to 60 minutes to diffuse nitrogen in the amorphous silicon to 10 15 / cm 3 or more and 10 19 / cm 3 or less.
作用 熱処理することにより活性領域は非晶質窒化シリコン
膜から拡散した窒素が混入しn-型となり、さらにその窒
素はドーピング材ともなるがアロイとしてａ−Si:H膜中
に取り込まれ、ステブラ、ロンスキ効果を抑制するとと
もにａ−Si:H/a−SiNx界面のストレスを緩和する。そし
て、ｎ型ドープ領域を複数に分けることによって不純物
の濃度勾配を緩和し、ドープ領域と活性領域との界面損
傷を緩和する事ができる。By heat treatment, the active region is mixed with nitrogen diffused from the amorphous silicon nitride film to become n − type, and the nitrogen also serves as a doping material, but is taken into the a-Si: H film as an alloy, It suppresses the Ronski effect and relieves stress at the a-Si: H / a-SiNx interface. By dividing the n-type doped region into a plurality of regions, the impurity concentration gradient can be mitigated, and the interface damage between the doped region and the active region can be mitigated.
実施例 以下、本発明による１実施例についてTFTの作成例を
第１図で説明する。ガラス基板１上にCr,Mo,W,Niなどの
蒸着膜によるゲート電極２を形成し、（第１図（ａ）高
周波プラズマ法によって、ゲート絶縁膜SiNx3、活性領
域ａ−Si:H4、保護膜SiNx5をそれぞれ基板温度を変えて
堆積する。SiNx3を形成するための原料ガスはSiH4,N2,N
H3を含む混合ガスであり、ａ−Si:H4を形成するための
原料ガスはSiH4,H2を含む混合ガスである。次に保護膜S
iNx5にコンタクトホール６を開ける（第１図ｂ）。次に
二層のｎ型のドープ領域、すなわちn-領域とｎ領域とを
形成する（第１図ｃ）。n-型およびｎ型に導電型を変化
させるドープ材としては一般的に知られている例えばPH
3が適用でき、n-型に導電型を変化させるには例えばリ
ンが1018/cm3以下ａ−Si:H膜中に取り込まれるように、
ａ−Si:H膜の主な原料であるSiH4に混入させる。混合比
はプラズマ堆積条件に依存するが一般的にはPH3/SiH4＝
10ppm程度で良い。本実施例では、ｎ型の非晶質シリコ
ン膜を堆積する専用堆積室でn-型の堆積を行ったため、
ドープ材であるPH3を混入せずに30秒間放電を行い、n-
型の第１ドープ領域７を形成したが、このようにドープ
材を混入しなくとも、堆積室内部の例えば堆積室壁面等
に付着したドープ材（例えばリン）が第１ドープ領域７
中に再現性よく1018/cm3以下の濃度で取り込まれてい
た。1018/cm3を越えるドープ量では強力な光に対する劣
化減少を十分に抑制することが困難であった。続いてPH
3/SiH4＝１％の混合比を持つガスを導入して５分間放電
しｎ型の第２ドープ領域８を形成する。この領域８はリ
ンを1018/cm3よりも大きな濃度で含ませるのが望まし
い。第１、第２のドープ領域７、８を部分的にエッチン
グした後ソース・ドレイン電極となるMo,Ni,Ta,W,Al等
の蒸着膜を形成して部分的にエッチングし、配線用導電
膜９とする（第１図ｄ）。ｎ型のドープ領域７、８を２
層形成すると、不純物の濃度勾配を緩和することが可能
となる。Embodiment An example of making a TFT for one embodiment according to the present invention will be described below with reference to FIG. The gate electrode 2 is formed on the glass substrate 1 by a vapor deposition film of Cr, Mo, W, Ni, etc. (FIG. 1 (a), the high frequency plasma method is used to form the gate insulating film SiNx3, the active region a-Si: H4, and the protection film. The film SiNx5 is deposited while changing the substrate temperature, and the source gases for forming SiNx3 are SiH 4 , N 2 , and N.
The mixed gas containing H 3 and the source gas for forming a-Si: H 4 is the mixed gas containing SiH 4 and H 2 . Next, the protective film S
Open the contact hole 6 in iNx5 (Fig. 1b). Next, two layers of n-type doped regions, that is, an n − region and an n region, are formed (FIG. 1c). Generally known as a dopant for changing the conductivity type to n − type and n type, for example, PH
3 is applicable, and in order to change the conductivity type to n − type, for example, phosphorus is incorporated into the a-Si: H film at 10 18 / cm 3 or less,
It is mixed with SiH 4 which is the main raw material of the a-Si: H film. Mixing ratio depends on plasma deposition conditions, but generally PH 3 / SiH 4 =
10ppm is enough. In this embodiment, since the n − -type deposition is performed in the dedicated deposition chamber for depositing the n-type amorphous silicon film,
Without mixing PH 3 is doped material for 30 seconds discharge, n -
Although the first dope region 7 of the mold is formed, the dope material (for example, phosphorus) attached to the inside of the deposition chamber, for example, the wall surface of the deposition chamber or the like can be used as the first doped region 7 without mixing the dope material in this way.
It was incorporated with good reproducibility at a concentration of 10 18 / cm 3 or less. When the doping amount exceeds 10 18 / cm 3 , it is difficult to sufficiently suppress the deterioration reduction due to strong light. Then PH
A gas having a mixture ratio of 3 / SiH 4 = 1% is introduced and discharged for 5 minutes to form an n-type second doped region 8. This region 8 preferably contains phosphorus at a concentration higher than 10 18 / cm 3 . After the first and second doped regions 7 and 8 are partially etched, a vapor deposition film of Mo, Ni, Ta, W, Al, etc., which will be the source / drain electrodes, is formed and partially etched, and wiring conductivity is obtained. It is referred to as membrane 9 (FIG. 1d). n-type doped regions 7 and 8 are 2
When a layer is formed, the concentration gradient of impurities can be relaxed.
この後、100℃から300℃の温度で10分間から60分間の
熱処理を行う。この熱処理によってゲート絶縁膜３およ
び保護膜５のSiNxから窒素原子を含む粒子がTFT活性領
域ａ−Si:H4および第１、第２ドープ領域７、８中に10
15/cm3から1019/cm3拡散し、ａ−Si:H膜４をn-型ａ−S
i:H膜10にすると同時に第１第２のドープ領域７、８の
不純物の活性化率を高め、さらにソース・ドレイン金属
電極（配線用導電膜）９とドープ領域８との接触をより
強固なものにする（第１図ｅ）。TFTの活性領域である
ｎ型非晶質シリコン10の禁止帯幅の中の平均局在状態密
度は1017/cm3もしくはそれ以下の程度である。また、電
子の移動度は10-3cm2/V・秒以上であり、キャリア寿命
は約10-7秒以上であった。窒素原子がａ−Si:H膜中に取
り込まれると、ｐ型になるとの報告もあるが、これは、
原料ガス中にN2またはNH2を混ぜて膜形成を行った場合
であり、本発明によるａ−SiNx固相からの窒素ドープで
はn-型になった。1020/cm3の窒素が混入した場合は活性
化エネルギが0.35eVとなり1019/cm3以下1015/cm3以上で
は、0.5から0.6eVとなった。n-型の定義として本発明で
は0.5＜Ec−Ea＜0.6eVを用いた。ｎ型かｐ型かの判定
は、TFTの動作で確認した。即ち、窒素がドープされな
い状態で形成したTFTをｎチャンネルとなるようにゲー
トバイアスを正にとってVthを求めると約3Vとなった。1
019/cm3以下1015/cm3以上の窒素を含むTFTでは1.5＜Vth
＜2.6Vと小さくなり、1020/cm3以上ではリーク電流が大
きくなって、十分なTFT特性を示さなかった。窒素ドー
プによってｐ型になったならばVthはドープ量とともに
大きくならなければならない。After that, heat treatment is performed at a temperature of 100 to 300 ° C. for 10 to 60 minutes. By this heat treatment, particles containing nitrogen atoms from SiNx of the gate insulating film 3 and the protective film 5 are formed in the TFT active region a-Si: H4 and the first and second doped regions 7 and 8.
Diffuse from 15 / cm 3 to 10 19 / cm 3 and form a-Si: H film 4 with n - type aS
At the same time as forming the i: H film 10, the activation rate of impurities in the first and second doped regions 7 and 8 is increased, and the contact between the source / drain metal electrode (conductive film for wiring) 9 and the doped region 8 is further strengthened. (Fig. 1e). The average localized density of states in the bandgap of the n-type amorphous silicon 10 which is the active region of the TFT is 10 17 / cm 3 or less. The electron mobility was 10 −3 cm 2 / V · sec or more, and the carrier lifetime was about 10 −7 sec or more. It has been reported that when nitrogen atoms are taken into the a-Si: H film, it becomes p-type.
This is the case of forming a film by mixing N 2 or NH 2 into the raw material gas, and the nitrogen doping from the a-SiNx solid phase according to the present invention resulted in n − type. When 10 20 / cm 3 of nitrogen was mixed, the activation energy was 0.35 eV, and from 10 19 / cm 3 or less to 10 15 / cm 3 or more, it was 0.5 to 0.6 eV. In the present invention, 0.5 <Ec−Ea <0.6 eV was used as the definition of n − type. The judgment of n-type or p-type was confirmed by the operation of TFT. That is, Vth was about 3 V when the gate bias was positive and the Vth was calculated so that the TFT formed in a state where nitrogen was not doped had an n channel. 1
0 < 19 / cm 3 or less 1.5 <Vth for TFTs containing 10 15 / cm 3 or more nitrogen
It became as small as <2.6 V, and at 10 20 / cm 3 or more, the leak current became large, and sufficient TFT characteristics were not exhibited. If it becomes p-type by nitrogen doping, Vth must increase with the doping amount.
以下、動作劣化の実施例に関して説明する。第２図は
従来のｎ型/i型ステップ接合を持つｎチャンネルTFTの
ソース、ドレイン電流を縦軸に、ソース、ドレイン電圧
を横軸にとり、ゲートバイアスを＋10V一定とした場合
の特性である。実線は初期特性である、TFTをON状態の
ままでソーラーシミュレーターによってスペクトルがAM
1（Air Mass One）、エネルギ密度100mW/cm2の光を30
分間照射し、再び同様の特性を測定すると破線で示した
特性となる。この様に従来OFF電流が増加し、ON電流が
減少するという特性を示した。本発明による、n-型活性
領域とn-型/n型ドープ領域による接合を有するTFTを同
様な光照射を行いながらON状態を続けても、従来の初期
特性である実線とほぼ同一の特性を得た。An example of operation deterioration will be described below. FIG. 2 shows the characteristics of a conventional n-channel TFT having an n-type / i-type step junction when the source and drain currents are plotted on the vertical axis, the source and drain voltages are plotted on the horizontal axis, and the gate bias is kept constant at + 10V. The solid line is the initial characteristic, the spectrum is AM by the solar simulator with the TFT in the ON state.
1 (Air Mass One), 30 light with an energy density of 100 mW / cm 2
When irradiation is performed for a minute and the same characteristic is measured again, the characteristic indicated by the broken line is obtained. In this way, the characteristics that the conventional OFF current increases and the ON current decreases are shown. According to the present invention, even if the TFT having the junction of the n − -type active region and the n − -type / n-type doped region is kept in the ON state while performing similar light irradiation, the characteristics which are almost the same as the solid line which is the conventional initial characteristic Got
発明の効果 本発明によるｎ型/n-型/n-型接合を用いる事によっ
て、非晶質シリコンの光劣化を未然に防ぐことができ、
キャリアの易動度の大きなTFTを強力な光照射状態にお
いても動作させ続けることが出来る。Effects of the Invention By using the n-type / n - type / n - type junction according to the present invention, photodegradation of amorphous silicon can be prevented in advance.
The TFT with high carrier mobility can continue to operate even under strong light irradiation.
第１図は本発明の１実施例による非晶質シリコン薄膜ト
ランジスタの製造方法を示す工程断面図、第２図は非晶
質シリコン薄膜トランジスタの動作を示す電流電圧特性
図、実線はTFTの初期特性及び本発明のｎ型/n-型整合を
用いたTFTの強力な光照射後の特性を示し、破線は強力
な光照射によって劣化した従来のｎ型/i型接合を用いた
TFTの特性を示す。 １……ガラス基板、２……ゲート電極、３……SiNxゲー
ト絶縁膜、４……ｉ型ａ−Si:H膜、５……SiNx保護膜、
６……コンタクトホール、７……n-型第１ドープ領域、
８……ｎ型第２ドープ領域、９……配線用導電膜、10…
…窒素を含むn-型ａ−Si:H膜。FIG. 1 is a process cross-sectional view showing a method of manufacturing an amorphous silicon thin film transistor according to one embodiment of the present invention, FIG. 2 is a current-voltage characteristic diagram showing the operation of the amorphous silicon thin film transistor, and the solid line shows the initial characteristics of the TFT. The characteristics of the TFT using n-type / n - type matching of the present invention after strong light irradiation are shown, and the broken line shows the conventional n-type / i-type junction deteriorated by strong light irradiation.
The characteristics of the TFT are shown. 1 ... Glass substrate, 2 ... Gate electrode, 3 ... SiNx gate insulating film, 4 ... i-type a-Si: H film, 5 ... SiNx protective film,
6 ... contact hole, 7 ... n - type first doped region,
8 ... N-type second doped region, 9 ... Wiring conductive film, 10 ...
... An n - type a-Si: H film containing nitrogen.
Claims (3)
れた窒素を1015/cm3以上1019/cm3以下含むn-型の導電型
を持ち、10-7秒以上のキャリア寿命、1017/cm3以下のエ
ネルギ・ギャップ中の平均局在状態密度、および10-3cm
2/V・sec以上の電子に対する移動度を持つ非晶質シリコ
ンの本体と、この本体よりも導電率をさらにｎ型に変更
する窒素以外のドープ材を含んでいるn-領域およびｎ領
域の複数のドープ領域とを有し、前記本体と前記n-領
域、および前記n-領域とｎ領域がそれぞれ半導体接合を
有することを特徴とする薄膜トランジスタ。1. A carrier life of 10 −7 seconds or more, having an n − type conductivity type containing nitrogen diffused from laminated amorphous silicon nitride in the range of 10 15 / cm 3 or more and 10 19 / cm 3 or less, Average localized density of states in the energy gap below 10 17 / cm 3 and 10 -3 cm
The main body is amorphous silicon having a mobility of electrons of 2 / V · sec or more, and the n − region and the n region containing a doping material other than nitrogen that changes the conductivity to n type more than the main body. A thin film transistor having a plurality of doped regions, wherein the body and the n − region, and the n − region and the n region respectively have semiconductor junctions.
する窒素以外のドープ材を1018/cm3よりも小さな濃度で
含んでいる第１のドープ領域と上記ｎ型に変更するドー
プ材を1018/cm3よりも大きな濃度で含んでいる第２のド
ープ領域を含む導電型を同じくする領域とに分かれてい
ることを特徴とする特許請求の範囲第１項記載の薄膜ト
ランジスタ。2. A first doped region, wherein the doped region contains a doping material other than nitrogen, which further changes the conductivity to n-type, in a concentration smaller than 10 18 / cm 3, and the dope which changes to the n-type. The thin film transistor according to claim 1, wherein the thin film transistor is divided into a second doped region containing a material at a concentration higher than 10 18 / cm 3 and a region having the same conductivity type.
程、第１の非晶質窒化シリコン／非晶質シリコン／第２
の非晶質窒化シリコンを基板温度をそれぞれ変えながら
堆積する工程、前記第２の非晶質窒化シリコンを選択的
にエッチングする工程、ｎ型に導電型を変える窒素以外
のドープ材を含んだ原料ガスを導入する専用堆積室内
で、前記ドープ材を原料ガスに導入せずにn-型非晶質シ
リコンを形成する工程の後、前記ドープ材を原料ガスに
導入しｎ型非晶質シリコンを形成する工程、前記n-型非
晶質シリコンおよびｎ型非晶質シリコンの少なくともゲ
ート電極上の一部を選択的にエッチングする工程、ソー
スおよびドレイン電極を形成する工程、および少なくと
もこれら工程の後100℃から300℃の温度で10分間から60
分間の熱処理で前記第１または第２の非晶質窒化シリコ
ンの窒素を非晶質シリコンに拡散する工程を含むことを
特徴とする薄膜トランジスタの製造方法。3. A step of forming a gate electrode on a glass substrate, first amorphous silicon nitride / amorphous silicon / second
Of depositing the amorphous silicon nitride while changing the substrate temperature, selectively etching the second amorphous silicon nitride, and a raw material containing a dopant other than nitrogen that changes the conductivity type to n-type After the step of forming the n − -type amorphous silicon without introducing the doping material into the source gas in a dedicated deposition chamber for introducing the gas, the doping material is introduced into the source gas to remove the n-type amorphous silicon. Forming step, selectively etching at least a part of the n − -type amorphous silicon and the n-type amorphous silicon on the gate electrode, forming source and drain electrodes, and at least after these steps 10 minutes to 60 at a temperature of 100 ℃ to 300 ℃
A method of manufacturing a thin film transistor, comprising a step of diffusing nitrogen of the first or second amorphous silicon nitride into the amorphous silicon by heat treatment for minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23010987A JP2523679B2 (en) | 1987-09-14 | 1987-09-14 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23010987A JP2523679B2 (en) | 1987-09-14 | 1987-09-14 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6473671A JPS6473671A (en) | 1989-03-17 |
| JP2523679B2 true JP2523679B2 (en) | 1996-08-14 |
Family
ID=16902701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23010987A Expired - Lifetime JP2523679B2 (en) | 1987-09-14 | 1987-09-14 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2523679B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2635885B2 (en) * | 1992-06-09 | 1997-07-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Thin film transistor and active matrix liquid crystal display |
| US8053294B2 (en) * | 2008-04-21 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of thin film transistor by controlling generation of crystal nuclei of microcrystalline semiconductor film |
| JP5436017B2 (en) * | 2008-04-25 | 2014-03-05 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP5518366B2 (en) | 2008-05-16 | 2014-06-11 | 株式会社半導体エネルギー研究所 | Thin film transistor |
-
1987
- 1987-09-14 JP JP23010987A patent/JP2523679B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6473671A (en) | 1989-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6753211B2 (en) | Semiconductor devices and manufacturing methods thereof | |
| US5534445A (en) | Method of fabricating a polysilicon thin film transistor | |
| US5231297A (en) | Thin film transistor | |
| KR840001605B1 (en) | Thin film transistor | |
| KR100317641B1 (en) | Thin film transistor and the method of fabricating the same | |
| KR0180323B1 (en) | Method for fabricating reverse-staggered thin-film transistor | |
| EP0496639B1 (en) | Polysilicon thin film semiconductor device | |
| JPH03116875A (en) | Thin film field effect transistor and method of manufacturing the same | |
| JPH08242005A (en) | Amorphous silicon thin film transistor and its manufacture | |
| JP2523679B2 (en) | Thin film transistor and manufacturing method thereof | |
| JPH0746728B2 (en) | Method for manufacturing semiconductor device | |
| JPH04367277A (en) | Thin film transistor and manufacture thereof | |
| KR100317640B1 (en) | Thin film transistor and the method of fabricating the same | |
| JPH0564862B2 (en) | ||
| JPH06291316A (en) | Thin film insulated gate semiconductor device and manufacture thereof | |
| JP3300645B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0562899A (en) | Formation of semiconductor thin film | |
| KR100370451B1 (en) | Method for manufacturing amorphous silicon thin film transistor and liquid crystal display using simple process | |
| JPH088440A (en) | Thin film transistor and its manufacture | |
| KR0165579B1 (en) | Amorphous silicon thin film transistor and manufacturing thereof | |
| KR100451152B1 (en) | Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof | |
| JP3055170B2 (en) | Method for manufacturing thin film semiconductor device | |
| JP2976569B2 (en) | Method for manufacturing semiconductor device | |
| JP2681148B2 (en) | Method for manufacturing thin film junction field effect element | |
| JPH0488682A (en) | Manufacture of semiconductor device |