JPH088440A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the leakage current of a back channel when an inverse staggered type thin film transistor is turned off. CONSTITUTION:A gate electrode 2, a gate insulating film 3, an amorphous silicon layer 4, an N-type amorohous silicon layer, a drain electrode 6 and a source electrode 7 are formed on an insulating substrate 1. A P-type amorphous silicon layer 8 thinner than or equal to 100Angstrom which comes into contact directly with the amorphous silicon layer and a protective film 9 of silicon nitride is formed between the drain electrode and the source electrode 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to an inverted staggered thin film transistor which prevents a leakage current when the transistor is off and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional amorphous silicon thin film transistor is shown in FIG. The conventional thin film transistor has an insulating substrate 1
A gate electrode 2, a gate insulating film 3 of a silicon nitride film, an intrinsic amorphous silicon layer 4 and an n-type amorphous silicon layer 5, a drain electrode 6 and a source electrode 7, and a silicon nitride film. The protective layer 9 is formed. Here, the surface or interface of the amorphous silicon between the drain electrode 6 and the source electrode 7 will be referred to as the back channel 10 hereinafter.

In this conventional thin film transistor, the back channel is exposed when the protective film 9 is not provided, and electrons are easily induced in the back channel due to contamination such as positive ions from the outside, and a leak current is generated when the transistor is off. Increase. Further, in the case where the protective film 9 is provided, when the electric field generated by positive charges due to contamination on the protective film is applied to the back channel threshold value or more, the leak current when the transistor is off increases. Alternatively, the protective film itself is positively charged, and similarly the leak current at the time of off increases.

Since these phenomena are caused by the long-term operation of the thin film transistor, they are very important problems from the viewpoint of reliability, and various improvement examples have been seen in the past.

For example, Japanese Unexamined Patent Publication No. 2-163972 has an oxide film obtained by using hydrogen peroxide solution or an alumina film formed by a plasma CVD method in the back channel portion. This oxide film or alumina It is disclosed that the back channel semiconductor layer becomes p-type due to the influence of the film, and the above-mentioned leak current at the time of OFF can be reduced. In this conventional example, the p-type quality is different depending on the quality of the oxide film or the alumina film, and there is a drawback that it is difficult to control. Further, when hydrogen peroxide solution is used, there is a problem that it corrodes the metal wiring of the drain electrode and the source electrode, and when alumina is formed, aluminum diffuses into amorphous silicon to improve the characteristics of the thin film transistor. There is a problem that makes it worse.

As a conventional example similar to this, there is one disclosed in Japanese Patent Application Laid-Open No. 4-321275. In this conventional example, an aluminum oxide layer is formed on the back channel portion. In this example, similar to the previous example, the problem that aluminum diffuses into amorphous silicon and deteriorates the characteristics, and since the patterning is performed so that aluminum oxide remains only on the upper part of the thin film transistor, the manufacturing process is significantly increased. There is a problem of doing.

On the other hand, Japanese Patent Publication No. 5-0083197 discloses an example in which a layer 11 in which a p-type impurity is added to an n-type amorphous silicon layer is formed on a back channel as shown in FIG. In this conventional example, the same layer as the n-type amorphous silicon layer 5 is doped with p-type impurities to form a p-type layer. The underlying n-type impurity layer is a layer provided to bring the drain electrode 6 and the source electrode 7 into contact with the semiconductor layer, and has a very high impurity concentration of 10 ²⁰ atoms / cm ^3.
That is all. In order to make the layer p-type, it is necessary to dope p-type impurities at a high concentration, and it is impossible to do this stably. Further, there are problems that the impurity concentration becomes non-uniform after doping, a leak current flows, and the FET characteristic value changes.

[0008]

In these conventional techniques, the technique for preventing the leak current in the back channel portion, as described above, is different from the purpose. It is not practical because it has the drawback of diffusing inside and process control is difficult. Therefore, it has been a problem to reduce the leak current in the back channel portion without such side effects. In particular, when p-type impurities are doped into n-type silicon, it is necessary to dope p-type impurities at a high concentration, and the impurity concentration in silicon becomes non-uniform, so that a leak current rather tends to occur. There was a problem that it would end up. Since it is difficult to evenly distribute the impurities by doping even if the concentration is low, stable characteristic values cannot be obtained.

[0009]

In the thin film transistor of the present invention, a p-type amorphous silicon layer having a film thickness of 100 angstroms or less and containing no n-type impurities is provided above the amorphous silicon portion of the back channel portion. The layer is characterized in that it is in direct contact with the intrinsic amorphous silicon layer and the protective film of silicon nitride. The p-type amorphous silicon layer is characterized in that it is obtained by exposing and growing the intrinsic amorphous silicon layer of the back channel portion in the vapor phase of disilane gas containing boron. Note that polycrystalline silicon can be used instead of amorphous silicon.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a thin film transistor showing an embodiment of the present invention. The thin film transistor of the present invention has a gate electrode 2, a gate insulating film 3, an intrinsic amorphous silicon layer 4, an n-type amorphous silicon layer 5, a drain electrode 6 and a source electrode 7 on an insulating substrate 1. In this structure, the p-type amorphous silicon layer 8 containing no n-type impurities is present on the intrinsic amorphous silicon between the source electrode 7 and the source electrode 7. This p-type amorphous silicon layer has a thickness of 100 angstroms or less, and has a structure in which it is in direct contact with the amorphous silicon layer 4 and the silicon nitride protective film 9.

Next, this manufacturing method will be described with reference to FIGS. 2A to 2D which are sectional views of the thin film transistor. A gate electrode 2 made of a metal such as chromium is formed by lithography on an insulating substrate 1 made of glass or the like, and a gate insulating film 3 made of silicon nitride is formed by a plasma CVD method.
The intrinsic amorphous silicon layer 4 and the n-type amorphous silicon layer 5 are continuously formed (FIG. 2A).

Next, the intrinsic amorphous silicon layer 4 and the n-type amorphous silicon layer 5 are formed into an island shape by using a lithography technique (FIG. 2B). A metal such as chrome is formed on it by a sputtering method, and a drain electrode 6 and a source electrode 7 are formed by a lithography technique (FIG. 2C). Then, the n-type amorphous silicon layer 5 between the drain electrode 6 and the source electrode 7 is removed by a wet etching method or a dry etching method, and etching is performed so as to dig into the intrinsic amorphous silicon layer 4 (FIG. 2D). ). The surface of the intrinsic amorphous silicon layer etched at this time is called a back channel 10. After that, a p-type amorphous silicon layer 8 is grown between the drain electrode 6 and the source electrode 7, and finally a protective film of silicon nitride. When 9 is deposited, the thin film transistor of the present invention shown in FIG. 1 can be completed.

This p-type amorphous silicon layer 8 is grown by using disilane Si ₂ H ₆ , hydrogen H _2, and diborane B ₂ H _6.
In a ratio of 3: 2: 6 to a pressure of 200 Pa,
The substrate temperature is set to 350 ° C., and the atmosphere shown in FIG.
When the thin film transistor shown in (1) is exposed, the p-type amorphous silicon layer 8 is selectively formed only on the amorphous silicon. Although the growth rate is very slow, it cannot be accurately measured, but a film thickness of several tens of angstroms is sufficient, and under the above conditions, the film can be grown in about 15 minutes. After this, at 250 ℃ 30
Completed by annealing in a nitrogen atmosphere for a minute.

When vapor phase growth as described above is performed, silane can be used instead of disilane in the mixed gas, but since silane is difficult to decompose, it does not decompose only by raising the temperature, and disilane is used. Is preferred. The ratio of disilane Si ₂ H ₆ and diborane B ₂ H ₆ in the mixed gas is 1: 2. The ratio of hydrogen gas can be changed, and when disilane is 1, it is adjusted within the range of 0 to 10. In addition, an inert gas such as argon may be added to the mixed gas to adjust the pressure.

The heating temperature of the substrate may be appropriately changed as long as it is 300 ° C. to 400 ° C., but if it is too low or too high, vapor phase growth becomes difficult. The film thickness of the p-type amorphous silicon layer to be vapor-grown is 10 angstroms or more and 100 angstroms or less.
It can be grown in about 0 to 30 minutes. If it is too thick, a leak current may flow, which is a problem. Although there is no problem in reducing the thickness, it is important that the p-type layer is formed uniformly. The annealing time of 30 minutes to 2 hours is sufficient.

Since the p-type amorphous silicon layer 8 thus obtained has a very slow growth rate, the p-type amorphous silicon layer 8 is greatly affected by the underlying substrate due to the same effect as that of the epitaxial technique of single crystal silicon, and the p-type amorphous silicon layer 8 has an intrinsic property. It selectively grows only on the amorphous silicon layer 4. Therefore, it hardly grows in a region other than the intrinsic amorphous silicon layer 4 of this substrate, which is convenient. The presence of the p-type amorphous silicon layer 8 may be determined by measuring the depth profile by SIMS elemental analysis, and boron is 10 ¹⁸ to 10 ¹⁹ a in a layer having a film thickness of 50 Å or less.
It was found to exist at a concentration of toms / cm ³ .

FIG. 3 shows the characteristics of the thin film transistor of this embodiment. Figure 3 shows 10 between drain and source
It is an example of measuring the current between the drain and the source with respect to the gate voltage when a voltage of V is applied. Gate voltage is -1
It can be seen that the current between the drain and the source is reduced between 0 V and 0 V as compared with the conventional example. That is, the leak current when the thin film transistor is off is reduced. With respect to this characteristic, no increase in the off-current was observed even when the gate electrode was +30 V, the drain electrode and the source electrode were 0 V, and the voltage was applied for 90 minutes in air at 80 ° C. The reason for this is that the p-type silicon layer is in direct contact with the silicon nitride protective film 9, and a stable interface is formed.

As another means, the p-type amorphous silicon layer may be formed by using the plasma CVD method. Plasma CV
In the case of the method D, for example, silane SiH ₄ , hydrogen H _2, and diborane B ₂ H ₆ are mixed at a ratio of 1: 1: 2 and the pressure is adjusted to 0.
75 Torr, substrate temperature 300 ° C., power 25 mW /
When the electric discharge is 10 cm ² for 10 seconds, a p-type amorphous silicon layer 8 having a thickness of several tens of angstroms is formed. Plasma CV
When the D method is used, the selectivity is low, but there is an advantage that the p-type amorphous silicon layer can be formed in several tens of seconds. As described above, it is preferable to use disilane and diborane as the mixed gas in the vapor phase growth method, but in the case of plasma CVD, it is preferable to use silane and diborane. Of course, plasma CV
Disilane can also be used in D, but since disilane is more easily decomposed than silane and is often decomposed too much by plasma, it is not suitable for plasma CVD. In plasma CVD, plasma can assist to decompose silane, and the combination of disilane and diborane in the vapor phase growth method is plasma CVD.
In the method, it corresponds to a combination of silane and diborane.

The mixing ratio of silane SiH ₄ and diborane B ₂ H ₆ is 1: 2, and hydrogen H ₂ is mixed therein in the range of 0-5. Pressure is 80Pa-120Pa, substrate temperature is 250
The power from ℃ to 320 ℃ can be changed from 10 to 30 mW / cm ² . The discharge time is from several seconds to less than 1 minute. Further, the p-type amorphous silicon layer may be formed by using an ion implantation method instead of the plasma CVD method.

Although the above embodiments show the case where amorphous and silicon are used, a thin film transistor in which polycrystalline silicon is used instead of amorphous silicon may be used. Even in the case of polycrystalline silicon, the method for producing p-type polycrystalline silicon is exactly the same as the above-described case of amorphous silicon.

[0021]

As described above, according to the present invention, the p-type amorphous silicon layer or the p-type polycrystalline silicon layer is provided in the amorphous silicon portion or the polycrystalline silicon portion between the drain electrode and the source electrode. Therefore, there is an effect that it is possible to prevent the leakage current of the transistor which is increased due to the electrons being induced in the back channel due to the contamination by positive ions or the like from the outside and the charging of the protective film. Further, when exposed to a gas phase of disilane containing diborane or a mixed gas of silane, p-type amorphous or polycrystalline silicon can be selectively grown on amorphous or polycrystalline silicon, so that wiring is eroded,
The effect is great because there are no side effects such as aluminum diffusing into the amorphous or polycrystalline silicon layer and difficulty in process control. When the plasma CVD method is used,
Although it has low selectivity, it has the advantage of high deposition rate.

Further, since the p-type silicon layer is in direct contact with the amorphous or polycrystalline silicon layer and the protective film of silicon nitride, a stable interface can be obtained, so that the reliability is high.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a thin film transistor showing an embodiment of the present invention.

2A to 2D are cross-sectional views showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 3 is a diagram comparing the characteristics of the thin film transistor of the present invention with that of a conventional technique.

FIG. 4 is a sectional view of a conventional thin film transistor.

FIG. 5 is a cross-sectional view of another conventional thin film transistor.

[Explanation of symbols]

1 Insulating Substrate 2 Gate Electrode 3 Gate Insulating Film 4 Intrinsic Amorphous Silicon Layer 5 n-type Amorphous Silicon Layer 6 Drain Electrode 7 Source Electrode 8 p-type Amorphous Silicon Layer 9 Silicon Nitride Protective Film 10 Back Channel 11 n -Type amorphous silicon layer with p-type impurities added

Claims (11)

[Claims] 1. A gate electrode, a gate insulating film, a first semiconductor layer, a source / drain electrode and the first electrode on an insulating substrate.
In the method of manufacturing a thin film transistor having one conductivity type second semiconductor layer which is a contact layer with the semiconductor layer and another source / drain electrode, another conductivity type second semiconductor layer is provided on the first semiconductor layer. And a step of forming
Forming a source / drain electrode on the semiconductor layer, removing a portion of the second semiconductor layer where the source / drain electrode is not formed, and removing a portion of the second semiconductor layer removed. And a step of forming a third semiconductor layer of another conductivity type on the first semiconductor layer. 2. The method of manufacturing a thin film transistor according to claim 1, wherein an insulating film is formed on the third semiconductor layer. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the first semiconductor layer is made of intrinsic amorphous silicon. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the third semiconductor layer is formed by implanting ions of another conductivity type into the first semiconductor layer. 5. The third semiconductor layer is plasma CVD
The thin film transistor manufacturing method according to claim 1, wherein the thin film transistor is formed by a method. 6. In the plasma CVD, B ₂ H _{6 is used.}
The thin film transistor according to claim 5, wherein the thin film transistor is discharged in a mixed gas containing SiH ₄ and SiH ₄ . 7. The thin film transistor according to claim 1, wherein the third semiconductor layer is formed by a vapor phase epitaxy method. 8. The third semiconductor layer comprises B ₂ H ₆ and Si.
8. The method of manufacturing a thin film transistor according to claim 7, wherein the growth is selectively performed on the first semiconductor layer in a mixed gas containing ₂ H ₆ . 9. The method of manufacturing a thin film transistor according to claim 1, wherein the first semiconductor layer is made of intrinsic polycrystalline silicon. 10. The mixed gas B ₂ H ₆ and Si ₂ H ₆
9. The method of manufacturing a thin film transistor according to claim 8, wherein the ratio is 2: 1. 11. A gate electrode, a gate insulating film, a first semiconductor layer, a source / drain electrode, and the first electrode on an insulating substrate.
Thin film transistor having a second semiconductor layer of one conductivity type which is a contact layer with the semiconductor layer and a source / drain electrode of the other conductivity type on the first semiconductor layer between the source / drain electrodes. Having two semiconductor layers,
A thin film transistor comprising a silicon nitride film on the second semiconductor layer.