JPS62209862A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPS62209862A JPS62209862A JP61052310A JP5231086A JPS62209862A JP S62209862 A JPS62209862 A JP S62209862A JP 61052310 A JP61052310 A JP 61052310A JP 5231086 A JP5231086 A JP 5231086A JP S62209862 A JPS62209862 A JP S62209862A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- intrinsic semiconductor
- film
- thin film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 239000010409 thin film Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 37
- 239000012535 impurity Substances 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- 230000003287 optical effect Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 44
- 238000000034 method Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001149 41xx steel Inorganic materials 0.000 description 1
- 229910000861 Mg alloy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012788 optical film Substances 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、基板上に薄膜半導体素子を集積化した集積回
路、イメージセンサ、表示デバイス、バイオセンサ、温
度センサ、圧力センサなどの薄膜半導体デバイスに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to thin film semiconductor devices such as integrated circuits, image sensors, display devices, biosensors, temperature sensors, pressure sensors, etc. in which thin film semiconductor elements are integrated on a substrate. It is.
従来の技術
基板上に複数種類の薄膜半導体素子を設けて有機的に機
能するデバイスは公知である。たとえば、石英ガラス基
板上に、６００’Ｃ以上の熱ＣＶＤで製膜した多結晶シ
リコンを用いたＴＰＴによる駆動回路とスイッチ素子と
を形成し、さらに、３００℃以下のプラズマＣＶＤで製
膜した非晶質シリコンを用いたＰＩＮフォトダイオード
アレイを形成し接続した一次元イメージセンサが知られ
ている。BACKGROUND OF THE INVENTION Devices that function organically by providing a plurality of types of thin film semiconductor elements on a conventional technology substrate are known. For example, a TPT drive circuit and a switch element are formed on a quartz glass substrate using polycrystalline silicon formed by thermal CVD at temperatures of 600°C or higher, and a non-transfer element formed by plasma CVD at temperatures of 300°C or lower. A one-dimensional image sensor is known in which a PIN photodiode array using crystalline silicon is formed and connected.
また、ホウケイ酸ガラス基板上にプラズマＣＶＤで１μ
■以上の膜厚の非晶質シリコンの真性半導体層を持つＰ
ＩＮフォトダイオードアレイを形成した後、０．３μ薦
以下の膜厚の非晶質シリコンの真性半導体層を持つＴＦ
Ｔアレイをスイッチ素子として形成した一次元イメージ
センサなども知られている。さらにＴＰＴのソース電極
およびドレイン電極とオーミック接触を取るため製膜し
た薄い不純物半導体層を電極形成時のフォトエツチング
工程で除去することは、ＴＰＴの作製上必要であるため
、従来より行なわれている。In addition, 1μ
■P with an intrinsic semiconductor layer of amorphous silicon with a film thickness of
After forming the IN photodiode array, a TF with an amorphous silicon intrinsic semiconductor layer with a film thickness of less than 0.3μ is recommended.
A one-dimensional image sensor in which a T-array is formed as a switch element is also known. Furthermore, removing the thin impurity semiconductor layer formed to make ohmic contact with the source and drain electrodes of the TPT in the photo-etching process when forming the electrodes is necessary for the fabrication of the TPT, so it has been conventionally done. .
発明が解決しようとする問題点
従来の技術は、ＴＰＴとフォトダイオードのような複数
の種類の素子を同一基板上に形成するのに、それぞれの
素子に対して製膜やフォトエツチングの工程を直列的に
くり返して行なうものであった。したがって工程数が非
常に多くなり、不良率が高く、また製造コストも高くな
る第１の欠点があった。また第２の欠点として、後の製
膜工程で先に形成された素子の半導体薄膜が損傷を受け
。Problems to be Solved by the Invention Conventional technology involves forming multiple types of elements such as TPT and photodiodes on the same substrate by serially performing film forming and photoetching processes for each element. It was something I would do over and over again. Therefore, the first disadvantage is that the number of steps is extremely large, the defective rate is high, and the manufacturing cost is also high. A second drawback is that the semiconductor thin film of the previously formed element is damaged in the later film forming process.
特性が劣化するという欠点があった。たとえば。There was a drawback that the characteristics deteriorated. for example.
ＴＰＴの半導体膜をプラズマＣＶＤで製膜する時、先に
形成したフォトダイオードの電極金属がプラズマのイオ
ン衝撃によりフォトダイオードの半導体接合部に拡散し
て特性を劣化させていた。When a TPT semiconductor film is formed by plasma CVD, the previously formed electrode metal of the photodiode is diffused into the semiconductor junction of the photodiode due to the ion bombardment of the plasma, deteriorating its characteristics.
そこで本発明は、このような従来技術における問題点を
解決することを目的とする。Therefore, the present invention aims to solve the problems in the prior art.
問題点を解決するための手段
上記問題点を解決するため本発明は、基板上に、同時に
製膜した真性半導体層を有するとともに互いに接続され
て機能する複数種類の素子を形成し、前記素子のうち少
なくとも１種類の素子の真性半導体層を部分的に除去し
てその膜厚を小さくしたものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms on a substrate a plurality of types of elements having intrinsic semiconductor layers formed at the same time and functioning by being connected to each other. The intrinsic semiconductor layer of at least one type of element is partially removed to reduce its film thickness.
作用
このような薄膜半導体デバイスは、複数の種類の素子を
同一基板上に形成するのにすべての素子をいずれも真性
半導体層を主とする素子で構成するとともに、この真性
半導体層を１回の製膜で同時に堆積し、その後、電極な
どの形成の過程で、各素子が最適な膜厚になるよう真性
半導体層をエツチングによって部分的に除去することに
よって得られる。このような製法が可能な素子は、非晶
質半導体薄膜や多結晶シリコン半導体薄膜を用いたＰＩ
Ｎ接合ダイオード、シ五ットキー接合型ダイオード、電
界効果型トランジスタや非晶質半導体の光導電素子など
を組み合わせたデバイスであり、真性半導体層としては
１１００ｐｐ以下の微量のＰやＢなどを含む弱いＮ型や
弱いＰ型のように、１層と実質的に同じように機能する
材料も含まれる。Function In such a thin film semiconductor device, multiple types of elements are formed on the same substrate, but all the elements are composed of elements mainly consisting of an intrinsic semiconductor layer, and this intrinsic semiconductor layer is formed in one process. The intrinsic semiconductor layer is deposited simultaneously during film formation, and then, during the process of forming electrodes, etc., the intrinsic semiconductor layer is partially removed by etching so that each element has an optimal film thickness. Elements that can be manufactured using this method include PI using an amorphous semiconductor thin film or a polycrystalline silicon semiconductor thin film.
It is a device that combines N-junction diodes, Schottky junction diodes, field-effect transistors, amorphous semiconductor photoconductive elements, etc., and the intrinsic semiconductor layer is made of weak N containing trace amounts of P and B of 1100 pp or less. Also included are materials that function substantially the same as a single layer, such as type and weak P type.
非晶質半導体の中で最も良い素子特性が得られるのは、
光ＣＶＤやプラズマＣＶＤで作製した水素化非晶質シリ
コン、水素化非晶質ゲルマニウムなどであり、ＰＩＮフ
ォトダイオード、電界効果型トランジスタ、光導電素子
の３種類について、いずれも良好な素子を同時に形成す
ることができる。Among amorphous semiconductors, the best device characteristics can be obtained by
Hydrogenated amorphous silicon, hydrogenated amorphous germanium, etc. produced by photo-CVD or plasma CVD are used to simultaneously form three types of good devices: PIN photodiodes, field-effect transistors, and photoconductive devices. can do.
このように本発明によると、真性半導体層を同時に製膜
することにより膜質の劣化や接合部の劣化の無い半導体
素子が同一基板上に形成され、膜厚を最適化するため真
性半導体層を部分的に除去していわゆる超薄膜化した電
界効果型トランジスタや光導電素子は、それぞれ電圧パ
ルス応答と光パルス応答が速くなり、イメージセンサな
どに最適な薄膜半導体デバイスとして機能する。As described above, according to the present invention, by simultaneously forming the intrinsic semiconductor layer, a semiconductor element without deterioration of film quality or bonding parts can be formed on the same substrate, and in order to optimize the film thickness, the intrinsic semiconductor layer can be partially removed. Field-effect transistors and photoconductive elements that have been made into so-called ultra-thin films have faster voltage and light pulse responses, respectively, and function as thin-film semiconductor devices ideal for image sensors and the like.
実施例 本発明の代表的な実施例の構造断面図を第１図に示す。Example A structural sectional view of a typical embodiment of the present invention is shown in FIG.
ホウケイ酸ガラスなどの透光性基板１の上に蒸着後フォ
トエツチングしたＣｒ、ＮｌＣｒ＊Ｍｏなどのゲート電
極２を設け、その上にｓｉ、Ｎ４＋５ｕｎ２などのゲー
ト絶縁膜３を設け、このゲート絶縁膜３の近くに別にＩ
ｎ２Ｏ，、ＳｎＯ，ｔ ＩＴ○（インジウム・スズ・
オキサイド）などの透明電極４を形成する。この上に光
ＣＶＤやプラズマＣＶＤによって厚さ０．６μｍ〜２μ
曙の水素化非晶質シリコンの真性半導体層５を製膜し、
次に、この真性半導体層５とオーミック接触するＡｌｌ
、 Ｍｇ。A gate electrode 2 made of Cr, NlCr*Mo, etc. is provided on a transparent substrate 1 made of borosilicate glass or the like, which is photo-etched after vapor deposition, and a gate insulating film 3 made of Si, N4+5un2, etc. is provided thereon. There is another I near 3.
n2O,, SnO,t IT○ (indium tin,
A transparent electrode 4 such as oxide) is formed. On top of this, a thickness of 0.6 μm to 2 μm is applied by optical CVD or plasma CVD.
Forming an intrinsic semiconductor layer 5 of Akebono's hydrogenated amorphous silicon,
Next, the alloy that makes ohmic contact with this intrinsic semiconductor layer 5 is
, Mg.
Ａ１１−Ｍｇ合金などを真空蒸着した後フォトエツチン
グして同時に形成した電界効果型トランジスタ（ＦＥＴ
）のドレイン電極６およびソース電極７と、ソース電極
７に連続したショットキー型フォトダイオードのオーミ
ック電極８とを設ける。フォトエツチングの工程を減ら
すため、ソース電極７、ドレイン電極６、およびオーミ
ック電極８をマスクとして真性半導体層をＣＦ４とｏ２
の混合ガス中でプラズマエツチングし、厚さ０．２μｍ
以下の超薄膜化真性半導体層９をゲート絶縁膜３の上に
形成する。さらにプラズマＣＶＤやスパッタリングでＳ
ｉｎ、、Ｓｉ、Ｎ４，５ｉｎ２とＳｉ、Ｎ４の多層膜、
シリコンオキシナイトライドなどの絶縁保護膜１０を全
面に着け、Ａｉｌ配線用のコンタクトホール１１を設け
る。Field-effect transistors (FETs) are formed by vacuum-depositing A11-Mg alloy, etc., and then photo-etching.
), and an ohmic electrode 8 of a Schottky photodiode continuous to the source electrode 7 are provided. In order to reduce the number of photo-etching steps, the intrinsic semiconductor layer is coated with CF4 and O2 using the source electrode 7, drain electrode 6, and ohmic electrode 8 as masks.
Plasma etched in a mixed gas of 0.2 μm thick.
The following ultra-thin intrinsic semiconductor layer 9 is formed on the gate insulating film 3. In addition, plasma CVD and sputtering
in, Si, N4, 5in2 and Si, N4 multilayer film,
An insulating protective film 10 made of silicon oxynitride or the like is applied to the entire surface, and a contact hole 11 for Ail wiring is provided.
ＦＥＴの活性層となる超薄膜化真性半導体層９は、製膜
の初期の高品質の半導体膜からなるため、キャリアの移
動度が大きく、ドレイン電流の大きいＦＥＴが得られる
。また初期の製膜速度を小さくして高品質化することも
できる。しかし、層９の厚さが０．０２μｍ以下に薄く
なると、エツチングにより発生した界面準位によるキャ
リアの再結合により移動度が減少するため、この超薄膜
化真性半導体層９の膜厚は０．０２μｍ〜０．２μｍが
望ましい。Since the ultra-thin intrinsic semiconductor layer 9, which becomes the active layer of the FET, is made of a high-quality semiconductor film in the early stage of film formation, an FET with high carrier mobility and a large drain current can be obtained. It is also possible to increase the quality by reducing the initial film forming speed. However, when the thickness of the layer 9 is reduced to 0.02 μm or less, the mobility decreases due to the recombination of carriers by the interface states generated by etching. 02 μm to 0.2 μm is desirable.
界面準位を減少させる方法として、プラズマエツチング
した超薄膜化真性半導体層９の表面を空気中にさらすこ
となく、同じプラズマＣＶＤ装置で連続して５ｉｎ２．
ＳＬ、Ｎ４などの絶縁保護膜１０を形成することも有効
である。原料ガスはＳ ｉｏ。As a method for reducing the interface state, the surface of the plasma-etched ultra-thin intrinsic semiconductor layer 9 is continuously etched at 5 in 2.
It is also effective to form an insulating protective film 10 of SL, N4, or the like. The raw material gas is Sio.
の場合はＮ、ＯとＳ ｉ Ｈ、の混合ガスを用い。In this case, use a mixed gas of N, O, and SiH.
Ｓｉ、Ｎ４の場合はＮＨ，やＮ２とＳ ｉ Ｈ４の混合
ガスを用いる。すると、ＲＦグロー放電によりいずれも
水素化された良質の絶縁保護膜１０が得られる。In the case of Si and N4, NH or a mixed gas of N2 and SiH4 is used. Then, a good quality insulating protective film 10 is obtained which is hydrogenated by RF glow discharge.
またプラズマエツチングした表面をＮ２中の放電により
水素プラズマ処理すれば１表面のＳｉ原子の未結合手が
励起したＨ、［子と結合して安定化し。Furthermore, if the plasma-etched surface is treated with hydrogen plasma by discharge in N2, the dangling bonds of the Si atoms on one surface combine with the excited H and [ atoms and become stable.
界面準位を減少させることができる。また、このような
水素プラズマ処理は、真性半導体層５のプラズマエツチ
ングと連続して行なうことができる。Interface states can be reduced. Further, such hydrogen plasma treatment can be performed continuously with plasma etching of the intrinsic semiconductor layer 5.
非晶質シリコンからなる超薄膜化真性半導体層９にＡｒ
レーザやエキシマレーザを照射してレーザアニールする
と、結晶化により約１ａ１／ｖ−３ｅｃの移動度が１０
〜２００ａＪ／ Ｖ−ｓｅｅに向上するほか、エツチン
グによって発生した歪と界面準位を除去できる効果が得
られる。以上のような、水素プラズマ処理、レーザアニ
ール、連続した絶縁膜の形成プロセスなどは、いずれも
本発明による真性半導体層５の部分的除去と組み合わせ
たときに効果が大きい。Ar is applied to the ultra-thin intrinsic semiconductor layer 9 made of amorphous silicon.
When laser annealing is performed by irradiating with laser or excimer laser, the mobility of about 1a1/v-3ec decreases to 10 due to crystallization.
In addition to being improved to ~200 aJ/V-see, it is also possible to remove the strain and interface states caused by etching. The above hydrogen plasma treatment, laser annealing, continuous insulating film formation process, etc. are all highly effective when combined with partial removal of the intrinsic semiconductor layer 5 according to the present invention.
オーミック電極８は透明電極４とともに真性半導体Ｍ５
をはさむサンドインチ型のフォトダイオードを構成して
いる。すなわち、透明電極４と真性半導体層５の間のシ
ゴットキバリアによる内部電界が発生する。透明電極４
を通して真性半導体層５に入射した光によって励起した
電子は、オーミック電極８からソース電極７にたまり、
ＦＥＴのスイッチ素子のオン・オフにより信号電流とし
て読み出しができる。このため、第１図の実施例の素子
を複数個直線状に配列すれば、画像情報を時系列で読み
出す一次元イメージセンサとして機能する。本実施例に
示す薄膜のＦＥＴは飽和ドレイン電圧が大きいため、５
〜１０ｖの逆バイアス電圧をフォトダイオードに印加す
る必要がある。また、安定な耐圧を得るため、真性半導
体Ｊｌ１５は０．６μＩｌ〜２μＩの厚さが必要である
。そこで超薄膜化真性半導体層９の望ましい膜厚０．０
２μ−〜０．１μｍと著しく膜厚が異なるため、独立し
て膜厚を最適化できる本発明が有効となる。多結晶Ｓｉ
薄膜を用いる場合も、はぼ同様の効果が得られる。The ohmic electrode 8 is an intrinsic semiconductor M5 together with the transparent electrode 4.
It constitutes a sandwich-type photodiode sandwiching the . That is, an internal electric field is generated due to the barrier between the transparent electrode 4 and the intrinsic semiconductor layer 5. Transparent electrode 4
Electrons excited by the light incident on the intrinsic semiconductor layer 5 through the ohmic electrode 8 accumulate in the source electrode 7,
It can be read out as a signal current by turning on and off the switch element of the FET. Therefore, if a plurality of elements of the embodiment shown in FIG. 1 are arranged in a straight line, it will function as a one-dimensional image sensor that reads out image information in time series. Since the thin film FET shown in this example has a large saturation drain voltage,
A reverse bias voltage of ~10v needs to be applied to the photodiode. Further, in order to obtain a stable breakdown voltage, the intrinsic semiconductor Jl15 needs to have a thickness of 0.6 μI to 2 μI. Therefore, the desirable thickness of the ultra-thin intrinsic semiconductor layer 9 is 0.0.
Since the film thickness is significantly different from 2 μm to 0.1 μm, the present invention, which can independently optimize the film thickness, is effective. Polycrystalline Si
Even when using a thin film, similar effects can be obtained.
第２図は、ＩＰ接合またはＩＮ接合を持つフォトダイオ
ードとＦＥＴを同時に形成した実施例を示すものである
。ここでは、ゲート電極２と同じＣｒ Ｍ ｏなどの金
属蒸着膜でフォトダイオードの下部電極１２を形成して
工程を減らすとともに、フォトダイオードの窓側の透明
電極１３とＦＥＴのソースまたはドレインとなる透明電
極１４．１５を同時に形成し、透明電極１３．１４．１
５と真性半導体層５との間に、安定な拡散電位を得るた
め薄いＰ型またはＮ型の不純物半導体層１６．１７を設
けたものである。この不純物半導体ｙＩｍ１６．１７の
ゲート部分は。FIG. 2 shows an embodiment in which a photodiode having an IP junction or an IN junction and a FET are formed at the same time. Here, the lower electrode 12 of the photodiode is formed with a metal vapor deposition film such as CrMo, which is the same as the gate electrode 2, to reduce the number of steps, and the transparent electrode 13 on the window side of the photodiode and the transparent electrode that becomes the source or drain of the FET are formed. 14.15 is formed at the same time, transparent electrode 13.14.1
5 and the intrinsic semiconductor layer 5, a thin P-type or N-type impurity semiconductor layer 16, 17 is provided in order to obtain a stable diffusion potential. The gate portion of this impurity semiconductor yIm16.17 is as follows.
真性半導体層５の一部を除去するときに同時に除かれる
。It is removed at the same time as part of the intrinsic semiconductor layer 5 is removed.
本実施例のものは、素子側から光を入射するため原稿に
接近して用いる完全密着型イメージセンサに応用でき、
ＦＥＴ部の真性半導体層５の超薄膜化によって、しや光
膜が無い場合でもＦＥＴが入射光の影響を受けないよう
にすることができる。This example can be applied to a fully contact type image sensor that is used close to the original because the light enters from the element side.
By making the intrinsic semiconductor layer 5 in the FET part ultra-thin, it is possible to prevent the FET from being affected by incident light even when there is no optical film.
また、不純物半導体層１６．１７と透明電極１３．１４
゜１５のような拡散しやすい原子を持つ層とを、真性半
導体層５の製膜の後の工程で形成するため、拡散が起き
ず、真性半導体層５の膜質が改善され、フォトダイオー
ドの暗電流の低減にも効果がある。In addition, the impurity semiconductor layer 16.17 and the transparent electrode 13.14
Since the layer containing easily diffusible atoms such as 15 is formed in the process after forming the intrinsic semiconductor layer 5, diffusion does not occur, the film quality of the intrinsic semiconductor layer 5 is improved, and the darkness of the photodiode is improved. It is also effective in reducing current.
下部電極１２にＣｒを用い、かつ真性半導体層５に水素
化非晶質シリコンを用いる場合は、その間の電位障壁は
比較的小さく、良好である。When Cr is used for the lower electrode 12 and hydrogenated amorphous silicon is used for the intrinsic semiconductor layer 5, the potential barrier therebetween is relatively small and good.
第３図は、フォトダイオードの下部電極とＦＥＴのゲー
ト電極を共通膜にして接続した実施例を示すものである
。本例によると、フォトダイオードの光電流をゲートに
蓄積し、これを増巾して信号処理することができる。こ
こで１８はゲート電極、１９はソース電極、２０はドレ
イン電極、２１は透明電極、２２．２３．２４は不純物
半導体層、２５は下部電極、２６は絶縁膜、２７は絶縁
保護膜である。FIG. 3 shows an embodiment in which the lower electrode of the photodiode and the gate electrode of the FET are connected by using a common film. According to this example, the photocurrent of the photodiode can be accumulated in the gate and amplified to perform signal processing. Here, 18 is a gate electrode, 19 is a source electrode, 20 is a drain electrode, 21 is a transparent electrode, 22, 23, and 24 are impurity semiconductor layers, 25 is a lower electrode, 26 is an insulating film, and 27 is an insulating protective film.
第４図に示す実施例は、第１図のＦＥＴのソース電極７
に、電極３０を対向させてギャップセルを形成し、超薄
膜化真性半導体層２９を用いた高速光応答の光導電素子
と、超薄膜化真性半導体層２８を用いたＦＥＴを、一つ
の基板上に同時に形成し接続したデバイスに関するもの
である。ここで、超薄膜化真性半導体層２９の膜厚が０
．１μｍ以下になると０．３μ■の場合の約１０倍に光
応答を速くできる。In the embodiment shown in FIG. 4, the source electrode 7 of the FET shown in FIG.
A gap cell is formed by making the electrodes 30 face each other, and a photoconductive element with high-speed photoresponse using the ultra-thin intrinsic semiconductor layer 29 and an FET using the ultra-thin intrinsic semiconductor layer 28 are mounted on one substrate. It relates to devices simultaneously formed and connected to. Here, the thickness of the ultra-thinned intrinsic semiconductor layer 29 is 0.
．． When the thickness is less than 1 μm, the optical response can be made about 10 times faster than when the thickness is 0.3 μm.
本例によると、最も単純な工程で製造でき、受光素子の
シミートもほとんど発生しない。また先は基板側と素子
側のどちら側からでも入射でき、読み取る原稿に受光素
子を近接させた２次元密着型イメージセンサなどにも応
用することが容易である。また超薄膜化真性半導体層２
９の絶縁保護膜１０として多孔質でじゃ光性の薄膜を用
いれば、表面吸着した水分により暗電流の変化する湿度
センサを実現することができるほかに、絶縁保護膜１０
として熱伝導率が良くしや光性の薄膜を用れば、温度上
昇による暗電流の増加を応用した温度センサアレイを実
現できるなどの利点がある。According to this example, it can be manufactured using the simplest process, and there is almost no shimmy of the light-receiving element. In addition, the light can enter from either the substrate side or the element side, and can be easily applied to two-dimensional contact type image sensors in which the light receiving element is placed close to the original to be read. In addition, ultra-thin intrinsic semiconductor layer 2
If a porous, light-absorbing thin film is used as the insulating protective film 10 of 9, it is possible to realize a humidity sensor in which the dark current changes due to moisture adsorbed on the surface.
If a thin film with good thermal conductivity and optical properties is used as a material, there are advantages such as the ability to realize a temperature sensor array that takes advantage of the increase in dark current caused by temperature rise.
発明の効果
以上のように本発明によれば、従来技術の欠点をすべて
解決し、一つの基板上に複数の機能を持つ半導体素子を
少ない工程で形成できる。また、それぞれの半導体素子
の高耐圧化や高速応答などの性能を独立して高めること
ができる。さらに、素子形成過程での特性劣化を除くこ
とができる。Effects of the Invention As described above, according to the present invention, all the drawbacks of the prior art can be solved and a semiconductor element having a plurality of functions can be formed on one substrate with a small number of steps. Furthermore, the performance of each semiconductor element, such as high breakdown voltage and high-speed response, can be independently improved. Furthermore, characteristic deterioration during the element formation process can be eliminated.
第１図〜第４図は、本発明の第１〜第４の実施例を示す
構造断面図である。
ｌ・・・透光性基板、５・・・真性半導体層、９．２８
゜２９・・・超薄膜化真性半導体層、１０・・・絶縁保
護膜、１３゜１４、１５．２１・・・透明電極、 １６
．１７．２４・・・不純物半導体層
代理人 森 本 義 弘
第１図
第２図
＝
／Ｊ、／４．／ｒ−＊ｅｆＪ＠ｆｉ
／ｊ、／７−−得＃３物科絹
第う図
２７−透Ｂ８％持
２４−ｍ−不才も才句半尊体層
第４図1 to 4 are structural sectional views showing first to fourth embodiments of the present invention. l... Transparent substrate, 5... Intrinsic semiconductor layer, 9.28
゜29...Ultra-thin intrinsic semiconductor layer, 10...Insulating protective film, 13゜14, 15.21...Transparent electrode, 16
．． 17.24... Impurity semiconductor layer agent Yoshihiro Morimoto Figure 1 Figure 2 = /J, /4. /r-*efJ@fi /j, /7--Profit #3 Materials silk diagram 27-Toru B8% holding 24-m-Untalented and talented half-venerable body layer Figure 4
Claims (1)
ともに互いに接続されて機能する複数種類の素子を形成
し、前記素子のうち少なくとも１種類の素子の真性半導
体層を部分的に除去してその膜厚を小さくしたことを特
徴とする薄膜半導体デバイス。 ２、電界効果型トランジスタの真性半導体層を部分的に
除去して膜厚を小さくしたことを特徴とする特許請求の
範囲第１項記載の薄膜半導体デバイス。 ３、プレーナ型光導電素子の真性半導体層を部分的に除
去して膜厚を小さくしたことを特徴とする特許請求の範
囲第１項記載の薄膜半導体デバイス。 ４、部分的に除去された真性半導体層の表面が水素プラ
ズマ中で処理されてなることを特徴とする特許請求の範
囲第１項記載の薄膜半導体デバイス。 ５、プラズマエッチングによって部分的に除去した真性
半導体層の表面を大気中にさらすこと無く、その上にプ
ラズマＣＶＤで製膜した絶縁保護膜を形成したことを特
徴とする特許請求の範囲第１項記載の薄膜半導体デバイ
ス。 ６、部分的に除去して膜厚を小さくした真性半導体層が
、レーザ光を照射して結晶化処理されてなることを特徴
とする特許請求の範囲第１項記載の薄膜半導体デバイス
。 ７、真性半導体層の上部電極を透明導電膜にて構成し、
この透明導電膜と真性半導体層の間に薄い不純物半導体
層を設けたことを特徴とする特許請求の範囲第１項記載
の薄膜半導体デバイス。[Claims] 1. A plurality of types of elements having intrinsic semiconductor layers formed simultaneously and functioning by being connected to each other are formed on a substrate, and the intrinsic semiconductor layer of at least one type of the elements is formed on a substrate. A thin film semiconductor device characterized in that the film thickness is reduced by partially removing the film. 2. The thin film semiconductor device according to claim 1, wherein the intrinsic semiconductor layer of the field effect transistor is partially removed to reduce the film thickness. 3. The thin film semiconductor device according to claim 1, wherein the intrinsic semiconductor layer of the planar photoconductive element is partially removed to reduce the film thickness. 4. The thin film semiconductor device according to claim 1, wherein the surface of the partially removed intrinsic semiconductor layer is treated in hydrogen plasma. 5. Claim 1, characterized in that an insulating protective film formed by plasma CVD is formed on the surface of the intrinsic semiconductor layer partially removed by plasma etching without exposing it to the atmosphere. The thin film semiconductor device described. 6. The thin film semiconductor device according to claim 1, wherein the intrinsic semiconductor layer whose thickness has been reduced by partially removing the film is crystallized by irradiation with laser light. 7. The upper electrode of the intrinsic semiconductor layer is made of a transparent conductive film,
The thin film semiconductor device according to claim 1, characterized in that a thin impurity semiconductor layer is provided between the transparent conductive film and the intrinsic semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052310A JP2865284B2 (en) | 1986-03-10 | 1986-03-10 | Thin-film semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052310A JP2865284B2 (en) | 1986-03-10 | 1986-03-10 | Thin-film semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62209862A true JPS62209862A (en) | 1987-09-16 |
| JP2865284B2 JP2865284B2 (en) | 1999-03-08 |
Family
ID=12911208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61052310A Expired - Lifetime JP2865284B2 (en) | 1986-03-10 | 1986-03-10 | Thin-film semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2865284B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331168A (en) * | 1986-07-25 | 1988-02-09 | Hitachi Ltd | Manufacture of thin-film transistor |
| JPH02250037A (en) * | 1989-03-23 | 1990-10-05 | Matsushita Electric Ind Co Ltd | Production of active matrix substrate and production of display device |
| US4997262A (en) * | 1987-08-26 | 1991-03-05 | Sharp Kabushiki Kaisha | Liquid crystal display element |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5075746A (en) * | 1988-07-19 | 1991-12-24 | Agency Of Industrial Science And Technology | Thin film field effect transistor and a method of manufacturing the same |
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| JP2006245045A (en) * | 2005-02-28 | 2006-09-14 | Fuji Photo Film Co Ltd | Solid imaging element of photoelectric conversion film stacked type and its manufacturing method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54130883A (en) * | 1978-04-01 | 1979-10-11 | Agency Of Ind Science & Technol | Production of semiconductor device |
| JPS5791517A (en) * | 1980-11-28 | 1982-06-07 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58178564A (en) * | 1982-04-13 | 1983-10-19 | Seiko Epson Corp | Thin film transistor |
| JPS59204275A (en) * | 1983-05-06 | 1984-11-19 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPS60136259A (en) * | 1983-12-24 | 1985-07-19 | Sony Corp | Manufacture of fet |
| JPS6142961A (en) * | 1984-08-07 | 1986-03-01 | Matsushita Electric Ind Co Ltd | Thin film field effect transistor and manufacture thereof |
| JPS62171155A (en) * | 1986-01-24 | 1987-07-28 | Canon Inc | Manufacture of photosensor |
-
1986
- 1986-03-10 JP JP61052310A patent/JP2865284B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54130883A (en) * | 1978-04-01 | 1979-10-11 | Agency Of Ind Science & Technol | Production of semiconductor device |
| JPS5791517A (en) * | 1980-11-28 | 1982-06-07 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58178564A (en) * | 1982-04-13 | 1983-10-19 | Seiko Epson Corp | Thin film transistor |
| JPS59204275A (en) * | 1983-05-06 | 1984-11-19 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPS60136259A (en) * | 1983-12-24 | 1985-07-19 | Sony Corp | Manufacture of fet |
| JPS6142961A (en) * | 1984-08-07 | 1986-03-01 | Matsushita Electric Ind Co Ltd | Thin film field effect transistor and manufacture thereof |
| JPS62171155A (en) * | 1986-01-24 | 1987-07-28 | Canon Inc | Manufacture of photosensor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331168A (en) * | 1986-07-25 | 1988-02-09 | Hitachi Ltd | Manufacture of thin-film transistor |
| US4997262A (en) * | 1987-08-26 | 1991-03-05 | Sharp Kabushiki Kaisha | Liquid crystal display element |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5075746A (en) * | 1988-07-19 | 1991-12-24 | Agency Of Industrial Science And Technology | Thin film field effect transistor and a method of manufacturing the same |
| JPH02250037A (en) * | 1989-03-23 | 1990-10-05 | Matsushita Electric Ind Co Ltd | Production of active matrix substrate and production of display device |
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| GB2253742A (en) * | 1990-10-05 | 1992-09-16 | Gen Electric | Device self-alignment by propagation of a reference structure's topography |
| US5340758A (en) * | 1990-10-05 | 1994-08-23 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| JP2006245045A (en) * | 2005-02-28 | 2006-09-14 | Fuji Photo Film Co Ltd | Solid imaging element of photoelectric conversion film stacked type and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2865284B2 (en) | 1999-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6146927A (en) | Semiconductor device, manufacturing method therefor and liquid crystal driving apparatus comprising the semiconductor device | |
| JP2923700B2 (en) | Semiconductor device and manufacturing method thereof | |
| USRE39393E1 (en) | Device for reading an image having a common semiconductor layer | |
| US5889291A (en) | Semiconductor integrated circuit | |
| KR0128724B1 (en) | Thin film insulated gate semiconductor device and manufacturing thereof | |
| US5705413A (en) | Method of manufacturing an electronic device using thermally stable mask | |
| JP2814319B2 (en) | Liquid crystal display device and method of manufacturing the same | |
| JPH0563196A (en) | Thin film semiconductor device, manufacture thereof and liquid crystal display device | |
| JPS62209862A (en) | Thin film semiconductor device | |
| JP3514891B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH07162003A (en) | Manufacture of thin-film transistor | |
| JP2572379B2 (en) | Method for manufacturing thin film transistor | |
| JP2776820B2 (en) | Method for manufacturing semiconductor device | |
| JP2916524B2 (en) | Thin film semiconductor device | |
| JPH0564862B2 (en) | ||
| KR100815894B1 (en) | Method of fabricating CMOS Poly Silicon TFT having LDD structure | |
| JP2698182B2 (en) | Thin film transistor | |
| JPH01248668A (en) | Thin-film transistor | |
| JPH0575125A (en) | Thin-film transistor | |
| KR100194677B1 (en) | Inverter and its fabrication method | |
| JPH03114234A (en) | Thin film transistor and its manufacture | |
| JP3336274B2 (en) | Method for manufacturing semiconductor device | |
| JPH09326495A (en) | Thin film transistor and its manufacturing method | |
| JPH09102627A (en) | Photoelectric conversion device | |
| JP2867457B2 (en) | Method of manufacturing thin film transistor matrix |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |