JP2814319B2 - Liquid crystal display device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (hereinafter, referred to as a liquid crystal display).
It is called a liquid crystal display or a thin film semiconductor device as appropriate. )
And a method of manufacturing the same, particularly forming a thin film transistor
Active matrix substrate and method of manufacturing the same
Related.

[0002]

2. Description of the Related Art As an active matrix substrate for a liquid crystal display, a thin film transistor for driving a pixel,
It is known that a thin film transistor for a peripheral driving circuit of a scanning circuit or a signal circuit for driving them is formed on the same substrate.

[0003] The thin film transistor for driving both the pixel and the peripheral circuit is formed of the same kind of single crystal or polycrystalline silicon. There is a thin film transistor formed of polycrystalline silicon.

An example of the former is disclosed in Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-open No. Sho 64-20 discloses an example of the latter.
No. 88, IEE Transaction on Electron Device, Vol. 36, No. 2868
Page to 2872 (IEEETransactions on Electron Dev
ices, Vol. 36, pp. 2868-2872 (1989)).

Japanese Patent Application Laid-Open No. Hei 2-27320 discloses that a channel region of a pixel driving thin film transistor is formed of amorphous silicon, a source and a drain region are formed of polycrystalline silicon, and a channel region and a source and drain of a peripheral circuit thin film transistor are formed. An example in which the region is formed of polycrystalline silicon is disclosed.

[0006]

The following characteristics are required for a thin film transistor on an active matrix substrate having a built-in peripheral driving circuit. It is desired that the thin film transistor for driving a pixel has a small off-current and is easily formed in a large-area substrate in a manufacturing method, so that uniformity of the process can be easily obtained. On the other hand, a thin film transistor for a peripheral driver circuit is desired to have high field-effect mobility in order to increase on-current. Further, in order to form both thin film transistors on the same substrate, matching of both manufacturing processes is an important issue.

[0007] In the above-mentioned conventional structures, the manufacturing process is complicated, and therefore, there are problems such as a decrease in yield, a high cost, and non-uniformity in a large-area substrate and between manufacturing lots.

For example, since a polycrystalline silicon thin film transistor has a high processing temperature in a manufacturing process, a usable heat-resistant glass substrate becomes expensive.

The method of bonding single crystal silicon to a glass substrate can provide a peripheral drive circuit excellent in characteristics, but is complicated and expensive in the manufacturing process.

[0010] A thin film transistor having a positive staggered structure in which an amorphous silicon layer is laser-annealed into a polycrystalline layer is relatively simple in manufacturing method and excellent in characteristics, but is shielded from light as an active matrix for a liquid crystal display. Is required, and the number of total process steps increases in this respect.

In addition, the structure in which the pixel driving thin film transistor is laminated with amorphous silicon is characterized in that, when the amorphous layer is bonded to the amorphous layer, the formation conditions at the time of plasma CVD, for example, slight changes in high-frequency output, substrate temperature, etc. Due to the difference, a new trap level is formed, and the characteristic tends to vary.

An object of the present invention is to provide a liquid crystal display device <br/> and a manufacturing method thereof having an active matrix substrate uniformity and reproducibility of the product was excellent.

[0013]

The object of the present invention is to provide a first reverse type in which a gate electrode, a gate insulating layer, a single-layer amorphous semiconductor layer channel region, a source electrode and a drain electrode are sequentially formed on the same insulating substrate. A field effect type thin film transistor having a staggered structure and a field effect type thin film transistor having a second inverted staggered structure in which a gate electrode, a gate insulating layer, a channel region of a semiconductor layer of crystalline and amorphous layers, a source electrode and a drain electrode are sequentially formed. This is achieved by having a thin film transistor.

[0014] The object is to form a gate electrode and a gate insulating layer sequentially on the same insulating substrate, form a polycrystalline semiconductor layer in a selected region on the gate insulating layer, and form a polycrystalline semiconductor layer on the polycrystalline semiconductor layer. This is achieved by forming an amorphous semiconductor layer, a source electrode and a drain electrode on the substrate.

An object of the present invention is to form a gate electrode, a gate insulating layer, and a first amorphous semiconductor layer sequentially on the same insulating substrate, and to form a laser on a selected region on the first amorphous semiconductor layer. Annealing is performed to remove unnecessary regions of the first amorphous semiconductor layer by etching to form a polycrystalline semiconductor layer, and a second amorphous semiconductor layer, a source electrode, and a drain electrode are formed on the polycrystalline semiconductor layer. It is achieved by forming.

An object of the present invention is to form a gate electrode, a gate insulating layer, and a first amorphous semiconductor layer sequentially on the same insulating substrate, and to form a laser on a selected region on the first amorphous semiconductor layer. Annealing, removing unnecessary regions of the first amorphous semiconductor layer by etching to form a polycrystalline semiconductor layer, and treating the polycrystalline semiconductor layer and the gate insulating layer in a hydrogen-based plasma atmosphere. This is achieved by forming a second amorphous semiconductor layer by a plasma CVD method, and then forming a source electrode and a drain electrode.

[0017]

According to the above arrangement, the first and the second are arranged on the same insulating substrate.
A second inverted staggered field effect thin film transistor is formed, and an on-current of the second inverted staggered field effect thin film transistor flows from the source electrode to the drain electrode through the polycrystalline semiconductor layer channel region. In a polycrystalline layer having better crystallinity than an amorphous layer, the trap density is extremely low, so that high field-effect mobility can be obtained. Also,
In the junction between the amorphous layer and the polycrystalline layer in the semiconductor layer, no new trap level or interface level is formed, and a good junction can be obtained with good reproducibility if attention is paid only to cleaning. On the other hand, the first field effect thin film transistor having an inverted staggered structure has a large area uniformity by a normal plasma CVD method, if care is taken to clean the interface between the single-layer amorphous semiconductor layer channel region and the gate insulating layer. Property is obtained.

The first and second inverted staggered field-effect thin film transistors are formed by simultaneously forming a gate electrode and a gate insulating layer on the same insulating substrate at the same time.
Only the process of forming a polycrystalline semiconductor layer in a selected region on the gate insulating layer of the second inverted staggered field effect thin film transistor and removing the amorphous film in a region other than the polycrystalline semiconductor layer is different. Since the processes can be performed almost simultaneously, the process can be matched, and the first and second field-effect thin film transistors having the inverted staggered structure can be formed on the same insulating substrate. Further, the manufacturing process is simple, the uniformity and reproducibility are excellent, and the yield is high.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a longitudinal sectional view of the thin film semiconductor device of this embodiment. The element on the left is a peripheral circuit thin film transistor, and the element on the right is a pixel driving thin film transistor. In this embodiment, an active matrix substrate for a liquid crystal display having a display unit having a size of 305 mm (equivalent to 12 inches) diagonal is manufactured, and a pixel unit is formed by using an ordinary inverted-staggered amorphous Si thin film transistor. In the case of manufacturing a thin film transistor substrate having an inverted staggered structure in which 480 × 640 (× 3) components are arranged on a substrate, and a channel region in a peripheral circuit portion has a two-layer structure of polycrystalline and amorphous Si. is there. What is needed for this channel region is a thin film polycrystal, but if it is made thin, it will be damaged in the subsequent process of forming another film and will not operate satisfactorily as a channel region. Then, an amorphous Si layer is formed thereon to form a two-layer structure. The inverted stagger structure is often used because a light-shielding mask is unnecessary.

First, an insulating substrate 1 made of glass and having a diagonal size of 355 mm (corresponding to 14 inches) and a thickness of 1.1 mm is prepared.

As shown in FIG. 2, a Cr layer is deposited on the insulating substrate 1 by a sputtering method to a thickness of 300 nm and then patterned by a usual photolithographic technique to form a gate electrode 2.

As shown in FIG. 3, an SiN layer 3 to be a gate insulating layer is successively formed to a thickness of 350 nm and a semiconductor thin film of amorphous Si.
Layer 4 is deposited by a 60 nm plasma CVD method. The layer deposition conditions are as follows: the SiN layer 3 is made of SiH ₄ and NH ₃ as source gases.
The substrate temperature is set to 300 ° C., and the amorphous Si layer 4 is deposited at a substrate temperature of 360 ° C. using SiH ₄ and H ₂ as source gases. What is important here is that hydrogen concentration in the amorphous Si layer 4 (Si-H bonds, Si-H ₂ bonds, (Si-
H ₂ ) hydrogen concentration such as n-bond) is 10% or less. To this end, it is desirable to raise the substrate temperature and lower the reaction pressure. The hydrogen content in the amorphous Si layer 4 deposited at a substrate temperature of 360 ° C. is about 9%. If the hydrogen content exceeds 10%, the Si content will increase during the next laser annealing.
Layer peeling is likely to occur. This is because hydrogen or SiHx in the layer
Is thought to be due to rapid evaporation and scattering. The energy of 280 mJ / c is applied only to the amorphous Si layer 4 on the gate insulating layer above the gate electrode 2 in the portion to be the peripheral circuit on the left side of FIG.
Irradiate with m ² XeCl excimer laser (wavelength 308 nm). In this step, the laser-irradiated amorphous S
The i layer 4 is modified into a polycrystalline Si layer 5.

In FIG. 4, the amorphous Si layer 4 which has partially become the polycrystalline Si layer 5 is replaced with an extremely low concentration of HF (1 volume) -HNO _3.
Etching is performed for 10 seconds with a mixed solution of (2 volumes) -H ₂ O (5 volumes) to etch only the amorphous Si layer 4 and selectively place the polycrystalline Si layer 5 in the peripheral circuit portion on the SiN layer 3. Is patterned.

As shown in FIG. 5, an amorphous Si layer 6 and an n-type Si layer 7 doped with phosphorus are deposited to a thickness of 220 nm and a thickness of 40 nm by a plasma CVD method. The deposition conditions are as follows. Amorphous Si layer using SiH ₄ and H ₂ as 6 material gas, the substrate temperature of 300 ° C., this hydrogen concentration of the deposited layer by being controlled 12-14%. The n-type amorphous Si layer 7 uses SiH ₄ as a source gas and PH ₃ (concentration 1%, base gas H ₂ ) as a dopant, the substrate temperature is 300 ° C., and the resistivity of the deposited layer is 10%.
³ Ω-cm. What is important here is to clean the substrate surface in which the polycrystalline Si layer 5 is selectively patterned on the SiN layer 3 in order to improve the reproducibility of the process. After setting the substrate in the plasma CVD apparatus, the amorphous S
Prior to depositing the i-layer 6 and the n-type Si layer 7, the substrate surface is thinly etched in a plasma of hydrogen or a mixed gas of hydrogen and a halide (HF, NF ₃ ). 0.8 ToN pressure
(100 Pa) Plasma processing was performed at a supply power of 0.8 W / cm ² . As a result, the polycrystalline Si layer 5 is etched by about 10 nm, and the tangling bonds are terminated with hydrogen. Contamination can be prevented by performing the above layer formation continuously in the same chamber. As a result, the peripheral circuit portion has the modified polycrystalline Si layer 5 and the amorphous Si layers 6 and 7 above the gate electrode 2.
In the pixel portion, a two-layer structure of amorphous Si layers 6 and 7 is formed above the gate electrode 2 in the pixel portion.

As shown in FIG. 6, the n-type amorphous Si layer 7 and the amorphous Si layer 6 are patterned into an island shape by a usual photolithography technique to form an active region of a thin film transistor.

As shown in FIG. 7, an indium tin oxide (ITO) layer, which is a transparent electrode, is deposited to a thickness of 120 nm by a sputtering method, and is then patterned by photolithography to form a pixel transparent electrode layer 8. .

As shown in FIG. 8, the Cr layer 9 and the Al layer 1
0 are sequentially deposited by a sputtering method with a layer thickness of 60 nm and a layer thickness of 350 nm, respectively. Thereafter, the source and drain electrodes are patterned by photolithography, and subsequently, the n-type amorphous Si exposed between the source and drain electrodes.
Layer 7 is dry etched. Accordingly, in the channel region of the silicon thin film transistor, the thin film transistor for the peripheral circuit has a laminated structure of the polycrystalline Si5 layer and the amorphous Si layer 6, and the thin film transistor for the pixel driving has the amorphous Si6 layer.
It has a single-layer structure. Next, as the passivation layer 11, SiN is applied to the substrate by a plasma CVD method so as to have a thickness of about 1 μm.
Deposit to μm. Through such a process, an active matrix substrate with a built-in peripheral circuit can be realized. In the present embodiment, Si is used as the material of the semiconductor, but other materials such as GaAs, Ge, and Ce can be similarly used.

The characteristics of each of the thin film transistors manufactured in the present embodiment are as follows: field effect mobility: 50 cm ² / V · s, threshold voltage: 2.2 ± 0.1 in the peripheral circuit portion.
V, and an off-state current of 2 to 6 × 10 to ¹² A (Vg = −5 V). In the pixel portion, a field-effect mobility of 0.3 to
0.6 cm ² / V · s, threshold voltage; 1.5 ± 0.2 V,
An off-current of 1 to 3 × 10 to ¹² A is obtained.

[0030]

According to the present invention, the ON current of the field-effect thin film transistor having the second inverted staggered structure flows through the channel region of the polycrystalline semiconductor layer, and the trap density of the polycrystalline layer is extremely low. Mobility is obtained. On the other hand, the first field-effect thin film transistor having the inverted staggered structure can achieve large area uniformity by a normal plasma CVD method. The first and second field-effect thin-film transistors having an inverted staggered structure can be formed on the same substrate by matching the processes because the processes can proceed almost simultaneously. Further, the manufacturing process is simple, the uniformity and reproducibility are excellent, and the yield is high.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a thin film semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view of a thin-film semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 3 is a longitudinal sectional view of the thin-film semiconductor device according to the embodiment of the present invention for each manufacturing process.

FIG. 4 is a longitudinal sectional view of a thin-film semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 5 is a longitudinal sectional view of a thin-film semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 6 is a longitudinal sectional view of a thin-film semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 7 is a longitudinal sectional view of the thin film semiconductor device according to the embodiment of the present invention for each manufacturing process.

FIG. 8 is a longitudinal sectional view of a thin-film semiconductor device according to an embodiment of the present invention for each manufacturing process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating substrate 2 gate electrode 3 gate insulating layer 4 amorphous silicon layer 5 polycrystalline silicon layer 6 amorphous silicon layer 7 n-type amorphous silicon layer 8 pixel transparent electrode layer 9 source electrode layer 10 drain electrode layer 11 Passivation layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 G02F 1/136 500 H01L 27/12

Claims (6)

(57) [Claims] 1. A gate electrode, a gate insulating layer and a first amorphous semiconductor layer are sequentially formed on the same insulating substrate, and laser annealing is performed on a selected region on the first amorphous semiconductor layer. An unnecessary region of the first amorphous semiconductor layer is removed by etching to form a polycrystalline semiconductor layer, and a second amorphous semiconductor layer, a source electrode, and a drain electrode are formed on the polycrystalline semiconductor layer. A method for manufacturing a liquid crystal display device, comprising: forming an active matrix substrate by a method. 2. A gate electrode, a gate insulating layer and a first amorphous semiconductor layer are sequentially formed on the same insulating substrate, and laser annealing is performed on a selected region on the first amorphous semiconductor layer. An unnecessary region of the first amorphous semiconductor layer is removed by etching to form a polycrystalline semiconductor layer, and the polycrystalline semiconductor layer and the gate insulating layer are treated in a plasma atmosphere mainly composed of hydrogen, followed by plasma CVD. A method for manufacturing a liquid crystal display device, comprising: forming a second amorphous semiconductor layer by a method, and then forming a source electrode and a drain electrode to form an active matrix substrate. 3. The first amorphous semiconductor layer is formed by a plasma CVD method using SiH ₄ and H _2, and the H ₂ content in the first amorphous semiconductor layer is set to 10% or less. The method for manufacturing a liquid crystal display device according to claim 1 or 2 , wherein: 4. A liquid crystal display device having an active matrix substrate in which a plurality of pixel driving thin film transistors and a plurality of peripheral driving circuit driving thin film transistors are formed on the same insulating substrate. A thin film transistor for driving a pixel includes a gate electrode formed of metal, a gate insulating layer formed on the gate electrode, and an amorphous semiconductor layer containing silicon as a main component formed on the insulating layer. And a source electrode and a drain electrode formed on the semiconductor layer so as to face each other. The thin film transistor for the peripheral driver circuit has a gate electrode formed of metal, and a thin film transistor formed on the gate electrode. The gate insulating layer formed and the amorphous semiconductor layer containing silicon as a main component formed on the insulating layer are recrystallized by a laser. A semiconductor layer, an amorphous semiconductor layer formed on the polycrystalline semiconductor layer, and a source electrode and a drain electrode formed on the semiconductor layer to face each other. Liquid crystal display device. 5. A liquid crystal display device manufactured by the method according to claim 1, claim of claims 3. 6. An active matrix substrate for a liquid crystal display device manufactured by the method according to claim 1, claim of claims 3.