JP5470519B2 - Thin film transistor, manufacturing method thereof, and liquid crystal display device - Google Patents

Thin film transistor, manufacturing method thereof, and liquid crystal display device Download PDF

Info

Publication number
JP5470519B2
JP5470519B2 JP2009173709A JP2009173709A JP5470519B2 JP 5470519 B2 JP5470519 B2 JP 5470519B2 JP 2009173709 A JP2009173709 A JP 2009173709A JP 2009173709 A JP2009173709 A JP 2009173709A JP 5470519 B2 JP5470519 B2 JP 5470519B2
Authority
JP
Japan
Prior art keywords
film
amorphous silicon
polysilicon
thin film
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009173709A
Other languages
Japanese (ja)
Other versions
JP2011029411A (en
Inventor
邦幸 濱野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
V Technology Co Ltd
Original Assignee
V Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by V Technology Co Ltd filed Critical V Technology Co Ltd
Priority to JP2009173709A priority Critical patent/JP5470519B2/en
Priority to CN201080033821.5A priority patent/CN102576733B/en
Priority to PCT/JP2010/062075 priority patent/WO2011010611A1/en
Priority to KR1020177003103A priority patent/KR101803691B1/en
Priority to KR1020127004740A priority patent/KR101713360B1/en
Priority to TW099124143A priority patent/TWI509810B/en
Publication of JP2011029411A publication Critical patent/JP2011029411A/en
Application granted granted Critical
Publication of JP5470519B2 publication Critical patent/JP5470519B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678—Beam shaping, e.g. using a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Description

本発明は、逆スタガ構造の薄膜トランジスタに関し、特に、液晶表示装置の表示部の画素トランジスタに好適の薄膜トランジスタと、その製造方法及び液晶表示装置に関する。   The present invention relates to a thin film transistor having an inverted stagger structure, and more particularly to a thin film transistor suitable for a pixel transistor in a display portion of a liquid crystal display device, a manufacturing method thereof, and a liquid crystal display device.

逆スタガ構造の薄膜トランジスタとしては、絶縁性基板上にＣｒ又はＡｌ等の金属層によりゲート電極を形成し、次いで、このゲート電極を含む基板上にゲート絶縁膜として例えばＳｉＮ膜を形成し、その後、全面に水素化アモルファスシリコン（以下、ａ−Ｓｉ：Ｈと記載する）膜を形成したアモルファスシリコントランジスタがある。このアモルファスシリコントランジスタは、更に、ａ−Ｓｉ：Ｈ膜上に、例えば、ｎ＋Ｓｉ膜を形成し、ａ−Ｓｉ：Ｈ膜及びｎ＋Ｓｉ膜をゲート電極上の所定領域にアイランド状にパターニングし、更に金属層によりソース・ドレイン電極を形成した後、このソース・ドレイン電極をマスクとしてｎ＋Ｓｉ膜をエッチングし、チャネル領域予定領域の上方のｎ＋Ｓｉ膜を除去することにより、ａ−Ｓｉ：Ｈ膜とＳｉＮゲート絶縁膜との境界で、チャネル領域を形成し、その後、全面にパッシベーション膜を形成することにより、完成する。この逆スタガ構造のアモルファスシリコン薄膜トランジスタは、オフ電流ＩＯＦＦが小さいため、例えば、液晶表示装置の画素トランジスタとして使用されている。 As a thin film transistor having an inverted stagger structure, a gate electrode is formed of a metal layer such as Cr or Al on an insulating substrate, and then, for example, a SiN film is formed as a gate insulating film on the substrate including the gate electrode. There is an amorphous silicon transistor in which a hydrogenated amorphous silicon (hereinafter referred to as a-Si: H) film is formed on the entire surface. In this amorphous silicon transistor, for example, an n + Si film is formed on the a-Si: H film, and the a-Si: H film and the n + Si film are patterned in an island shape in a predetermined region on the gate electrode. and, after further forming the source and drain electrode by the metal layer, by the source of the n + Si film is etched the drain electrode as a mask to remove the upper n + Si layer in the channel region scheduled region, a- A channel region is formed at the boundary between the Si: H film and the SiN gate insulating film, and then a passivation film is formed over the entire surface, thereby completing the process. The amorphous silicon thin film transistor having the inverted stagger structure has a small off current I OFF and is used, for example, as a pixel transistor of a liquid crystal display device.

しかしながら、アモルファスシリコントランジスタは、ａ−Ｓｉ：Ｈ膜をチャネル領域に使用しているので、チャネル領域における電荷の移動度が小さいという難点がある。近時、画素部が形成された基板の周辺部に駆動回路を形成した液晶表示装置が提案されているが、この液晶表示装置において、アモルファスシリコントランジスタは、画素部の画素トランジスタとしては使用可能レベルではあるものの、より高速な書換が必要な周辺駆動回路の構成トランジスタとしては、チャネル領域の電荷移動度が小さすぎて、使用することが困難である。   However, since an amorphous silicon transistor uses an a-Si: H film for the channel region, there is a drawback that the mobility of charges in the channel region is small. Recently, a liquid crystal display device in which a drive circuit is formed in the peripheral portion of a substrate on which a pixel portion is formed has been proposed. In this liquid crystal display device, an amorphous silicon transistor is a usable level as a pixel transistor in the pixel portion. However, as a constituent transistor of a peripheral driver circuit that requires faster rewriting, the charge mobility of the channel region is too small to be used.

そこで、ａ−Ｓｉにレーザを照射してアニールすることにより、ａ−Ｓｉを多結晶シリコン（以下、ポリシリコンという）に結晶化させ、チャネル領域にポリシリコン膜を形成した逆スタガ構造の低温ポリシリコントランジスタが提案されている（特許文献１）。   Therefore, a-Si is irradiated with a laser and annealed to crystallize a-Si into polycrystalline silicon (hereinafter referred to as polysilicon) and form a polysilicon film in the channel region. A silicon transistor has been proposed (Patent Document 1).

特許文献１に記載された低温ポリシリコントランジスタは、以下のようにして形成される。即ち、図７に示すように、ガラス基板１０１上にＣｒ又はＡｌ等のゲート電極１０２を形成し、更に、ゲート電極１０２を含む基板１０１の全面にＳｉＮからなるゲート絶縁膜１０３を形成し、更にその上にａ−Ｓｉ：Ｈ膜を１０〜４０ｎｍの厚さに形成する。そして、このａ−Ｓｉ：Ｈ膜に対し、ライン状にレーザビームを照射するレーザ照射部材を、前記ラインに垂直の方向にスキャンさせることにより、ａ−Ｓｉ：Ｈ膜の全面にエキシマレーザ光を照射してアニールし、ａ−Ｓｉ：Ｈ膜の全体をポリシリコン膜１０４に改質させる。そして、改質後のポリシリコン膜１０４上に、再度、ａ−Ｓｉ：Ｈ膜１０５を形成し、更に、ａ−Ｓｉ：Ｈ膜１０５上にｎ＋Ｓｉ膜１０６を形成し、これらのｎ＋Ｓｉ膜１０６、ａ−Ｓｉ：Ｈ膜１０５及びポリシリコン膜１０４を、ゲート電極１０２の上方でアイランド状にエッチング加工する。そして、このアイランド状Ｓｉ３層膜の上に、ソース・ドレイン電極１０７を形成し、このソース・ドレイン電極１０７をマスクとして、ｎ＋Ｓｉ膜１０６を除去し、その後、全面に、パッシベーション膜１０８を形成する。 The low-temperature polysilicon transistor described in Patent Document 1 is formed as follows. That is, as shown in FIG. 7, a gate electrode 102 such as Cr or Al is formed on a glass substrate 101, and a gate insulating film 103 made of SiN is further formed on the entire surface of the substrate 101 including the gate electrode 102. An a-Si: H film is formed thereon with a thickness of 10 to 40 nm. Then, the a-Si: H film is scanned with a laser irradiation member that irradiates a laser beam in a line shape in a direction perpendicular to the line, thereby excimer laser light is applied to the entire surface of the a-Si: H film. Irradiation and annealing are performed to modify the entire a-Si: H film into the polysilicon film 104. Then, an a-Si: H film 105 is formed again on the modified polysilicon film 104, and an n + Si film 106 is further formed on the a-Si: H film 105, and these n + The Si film 106, the a-Si: H film 105, and the polysilicon film 104 are etched into an island shape above the gate electrode 102. Then, a source / drain electrode 107 is formed on the island-like Si3 layer film, the n + Si film 106 is removed using the source / drain electrode 107 as a mask, and then a passivation film 108 is formed on the entire surface. To do.

このようにして形成した低温ポリシリコントランジスタは、チャネル領域がポリシリコン膜１０４とａ−Ｓｉ：Ｈ膜１０５との２層膜で構成され、ポリシリコン膜１０４がＳｉＮゲート絶縁膜１０３に接触しているので、チャネル領域の電荷移動度が速く、オン電流が高くなり、動作速度が速くなるため、液晶表示装置の周辺駆動回路用のトランジスタとして十分に使用することができる。   In the low-temperature polysilicon transistor formed in this way, the channel region is composed of a two-layer film of the polysilicon film 104 and the a-Si: H film 105, and the polysilicon film 104 is in contact with the SiN gate insulating film 103. Therefore, the charge mobility in the channel region is high, the on-current is increased, and the operation speed is increased, so that it can be sufficiently used as a transistor for a peripheral driver circuit of a liquid crystal display device.

特開平５−６３１９６号公報JP-A-5-63196

しかしながら、上述の従来の低温ポリシリコントランジスタは、オン電流が高いものの、オフ電流も高くなり、電位保持特性が低いと共に、漏洩する電流が多くなるため、消費電力が高いという問題点がある。   However, although the above-described conventional low-temperature polysilicon transistor has a high on-current, it also has a problem that the off-current is also high, the potential holding characteristic is low, and the leakage current is large, resulting in high power consumption.

本発明はかかる問題点に鑑みてなされたものであって、オフ電流が小さく、電位保持特性が優れており、消費電力が低いと共に、動作速度も速い低温ポリシリコントランジスタを含む薄膜トランジスタ、この薄膜トランジスタの製造方法及びそれを使用した液晶表示装置を提供することを目的とする。   The present invention has been made in view of such problems. A thin film transistor including a low-temperature polysilicon transistor having a low off-state current, excellent potential holding characteristics, low power consumption, and high operation speed. It is an object to provide a manufacturing method and a liquid crystal display device using the same.

本発明に係る薄膜トランジスタは、絶縁性基板と、この絶縁性基板の上に形成されたゲート電極と、このゲート電極上に形成されたゲート絶縁膜と、このゲート絶縁膜上の前記ゲート電極に対応する位置にアイランド状に形成されたポリシリコン膜と、このポリシリコン膜の上面及び側面を覆うように形成されたアモルファスシリコン膜と、このアモルファスシリコン膜の両端部に電気的に接続するように形成されたソース・ドレイン電極と、を有し、前記ポリシリコン膜は、第１のアモルファスシリコン膜を全面に形成した後、前記アイランドの部分のみをアニールして結晶化したものであり、前記アモルファスシリコン膜における前記ポリシリコン膜の側面を覆う部分は、前記第１のアモルファスシリコン膜の前記アイランドの周辺部分を残して他の部分を除去することにより形成したものであり、前記アモルファスシリコン膜における前記ポリシリコン膜の上面を覆う部分は、第２のアモルファスシリコン膜により形成されたものであることを特徴とする逆スタガ構造の薄膜トランジスタである。

The thin film transistor according to the present invention corresponds to an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode, and the gate electrode on the gate insulating film. A polysilicon film formed in an island shape at a position where it is formed, an amorphous silicon film formed so as to cover the upper and side surfaces of the polysilicon film, and formed so as to be electrically connected to both ends of the amorphous silicon film possess a source-drain electrode, wherein the polysilicon film is formed by forming a first amorphous silicon film on the entire surface, which crystallized by annealing only a portion of the island, the amorphous silicon The portion of the film covering the side surface of the polysilicon film is a peripheral portion of the island of the first amorphous silicon film Leaving are those formed by removing the other portion, the portion covering the upper surface of the polysilicon film in the amorphous silicon film is characterized in that it is one that is formed by the second amorphous silicon film This is a thin film transistor having an inverted staggered structure.

前記ゲート絶縁膜は、例えば、ＳｉＮ膜である。   The gate insulating film is, for example, a SiN film.

本発明に係る薄膜トランジスタの製造方法は、絶縁性基板上にゲート電極を形成する工程と、前記ゲート電極を含む前記基板上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に第１のアモルファスシリコン膜を形成する工程と、前記第１のアモルファスシリコン膜に対し前記ゲート電極に対応するアイランド状領域にレーザ光を照射してこの領域をポリシリコン膜に改質する工程と、この改質ポリシリコン領域及び第１のアモルファスシリコン領域上に第２のアモルファスシリコン膜を形成する工程と、前記改質ポリシリコン膜の上面及び側面を覆うアモルファスシリコン膜を残して他の部分のアモルファスシリコン膜を除去する工程と、残存したアモルファスシリコン膜の両端部に電気的に接続するようにソース・ドレイン電極を形成する工程と、を有することを特徴とする逆スタガ構造の薄膜トランジスタの製造方法である。なお、上記アモルファスシリコン膜には、水素を含まない膜（ａ−Ｓｉ膜）の他、水素を含む水素化アモルファスシリコン膜（ａ−Ｓｉ：Ｈ膜）等も含む。   The method of manufacturing a thin film transistor according to the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film on the substrate including the gate electrode, and a first step on the gate insulating film. A step of forming an amorphous silicon film, a step of irradiating the island-like region corresponding to the gate electrode with respect to the first amorphous silicon film with a laser beam, and modifying the region into a polysilicon film; Forming a second amorphous silicon film on the polysilicon region and the first amorphous silicon region, and leaving an amorphous silicon film covering the upper and side surfaces of the modified polysilicon film, The source and drain electrodes are electrically connected to both ends of the remaining amorphous silicon film. A step of forming a manufacturing method of a thin film transistor of a reverse stagger structure characterized by having a. The amorphous silicon film includes a hydrogen-free amorphous silicon film (a-Si: H film) containing hydrogen in addition to a film not containing hydrogen (a-Si film).

前記レーザ光の照射工程においては、複数個のマイクロレンズを配置したマイクロレンズアレイによりレーザ光を集光して複数個のレーザビームを得、マトリクス状に配置された複数個の薄膜トランジスタの前記アイランド状領域を前記各レーザビームにより照射して、複数個の薄膜トランジスタのポリシリコン領域を形成することができる。   In the laser light irradiation step, the laser light is collected by a microlens array in which a plurality of microlenses are arranged to obtain a plurality of laser beams, and the island shape of the plurality of thin film transistors arranged in a matrix is obtained. By irradiating the region with each laser beam, polysilicon regions of a plurality of thin film transistors can be formed.

また、本発明に係る液晶表示装置は、前記薄膜トランジスタを、表示部の画素トランジスタ及び周辺駆動回路の駆動トランジスタとして使用することを特徴とする。   The liquid crystal display device according to the present invention is characterized in that the thin film transistor is used as a pixel transistor of a display portion and a driving transistor of a peripheral driving circuit.

本発明に係る薄膜トランジスタによれば、ＳｉＮ膜等のゲート絶縁膜とポリシリコン膜との境界にて、チャネル領域が形成されているので、電荷の移動速度が速く、オン電流が高く、書き込み速度が速いため、動作速度が速い。そして、ポリシリコン膜の側面をアモルファスシリコン膜が覆っており、このアモルファスシリコン膜は電荷の移動速度が遅いので、アモルファスシリコン膜が存在しない場合に比してリーク電流が低減され、電位の保持特性が優れていると共に、消費電力が低減される。   In the thin film transistor according to the present invention, since the channel region is formed at the boundary between the gate insulating film such as the SiN film and the polysilicon film, the charge movement speed is high, the on-current is high, and the writing speed is high. Because it is fast, the operation speed is fast. Since the amorphous silicon film covers the side surface of the polysilicon film, and the amorphous silicon film has a low charge transfer speed, the leakage current is reduced as compared with the case where the amorphous silicon film does not exist, and the potential holding characteristic. Is excellent and power consumption is reduced.

また、本発明に係る薄膜トランジスタの製造方法によれば、第１のアモルファスシリコン膜に対し、ゲート電極に対応するアイランド状領域に局部的にレーザ光を照射して、この領域をポリシリコン膜に改質し、更に、このポリシリコン膜及び第１のアモルファスシリコン膜上に、第２のアモルファスシリコン膜を形成した後、前記ポリシリコン膜とこのポリシリコン膜の側面及び上面を覆うアモルファスシリコン膜からなるチャネル領域を形成するから、本発明の薄膜トランジスタを容易に製造することができる。   Further, according to the method of manufacturing a thin film transistor according to the present invention, the first amorphous silicon film is irradiated with laser light locally on the island-shaped region corresponding to the gate electrode, and this region is changed to the polysilicon film. Furthermore, after the second amorphous silicon film is formed on the polysilicon film and the first amorphous silicon film, the polysilicon film and the amorphous silicon film covering the side surface and the upper surface of the polysilicon film are formed. Since the channel region is formed, the thin film transistor of the present invention can be easily manufactured.

更に、本発明に係る液晶表示装置によれば、駆動回路の動作が速く、漏れ電流が少なく、低消費電力化することができる。   Furthermore, according to the liquid crystal display device of the present invention, the operation of the drive circuit is fast, the leakage current is small, and the power consumption can be reduced.

本発明の実施形態に係る薄膜トランジスタを示し、（ａ）は平面図、（ｂ）は（ａ）のＢ−Ｂ線による断面図、（ｃ）は（ａ）のＣ−Ｃ線による断面図である。1A and 1B show a thin film transistor according to an embodiment of the present invention, where FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A, and FIG. is there. 本発明の実施形態における液晶表示装置の表示部の１画素を示す平面図である。It is a top view which shows 1 pixel of the display part of the liquid crystal display device in embodiment of this invention. 本発明の実施形態に係る製造方法にて使用するマイクロレンズアレイを使用したレーザ照射装置を示す図であり、（ａ）は全体図、（ｂ）はマイクロレンズアレイを示す。It is a figure which shows the laser irradiation apparatus using the micro lens array used with the manufacturing method which concerns on embodiment of this invention, (a) is a general view, (b) shows a micro lens array. （ａ）乃至（ｃ）は本発明の実施形態に係る薄膜トランジスタの製造方法を工程順に示す断面図である。(A) thru | or (c) are sectional drawings which show the manufacturing method of the thin-film transistor which concerns on embodiment of this invention in order of a process. （ａ）乃至（ｃ）は本発明の実施形態に係る薄膜トランジスタの製造方法を工程順に示す断面図であり、図４の次の工程を示す。(A) thru | or (c) is sectional drawing which shows the manufacturing method of the thin-film transistor which concerns on embodiment of this invention in order of a process, and shows the process following FIG. （ａ）乃至（ｃ）は本発明の実施形態に係る薄膜トランジスタの製造方法を工程順に示す断面図であり、図５の次の工程を示す。(A) thru | or (c) are sectional drawings which show the manufacturing method of the thin-film transistor which concerns on embodiment of this invention in order of a process, and shows the process following FIG. 従来の逆スタガ構造の薄膜トランジスタを示す断面図である。It is sectional drawing which shows the thin film transistor of the conventional reverse stagger structure.

以下、本発明の実施形態について、添付の図面を参照して具体的に説明する。図１は本発明の実施形態に係る薄膜トランジスタを示し、図２は液晶表示装置の表示部の１画素を示す平面図である。液晶表示装置においては、表示部と、この表示部の周辺部に駆動用の周辺回路とが配置されており、表示部においては、図２に示すように、複数本の走査線ＳＬと複数本の信号線ＤＬとが直交するように形成されており、この走査線ＳＬと信号線ＤＬとに囲まれた単位領域に１画素が形成される。各画素には、ＩＴＯ（Indium Tin Oxide）からなる透明電極ＴＥとスイッチングトランジスタＴが形成されており、このトランジスタＴのゲート電極は走査線ＳＬに接続され、トランジスタＴのドレインは信号線ＤＬに接続され、ソースはＩＴＯからなる透明電極ＴＥに接続されている。   Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 shows a thin film transistor according to an embodiment of the present invention, and FIG. 2 is a plan view showing one pixel of a display unit of a liquid crystal display device. In the liquid crystal display device, a display unit and a peripheral circuit for driving are arranged at the periphery of the display unit. In the display unit, as shown in FIG. 2, a plurality of scanning lines SL and a plurality of lines are arranged. The signal line DL is formed to be orthogonal to each other, and one pixel is formed in a unit region surrounded by the scanning line SL and the signal line DL. Each pixel is formed with a transparent electrode TE made of ITO (Indium Tin Oxide) and a switching transistor T. The gate electrode of the transistor T is connected to the scanning line SL, and the drain of the transistor T is connected to the signal line DL. The source is connected to the transparent electrode TE made of ITO.

図１（ａ）はトランジスタ１（Ｔ）の平面図、図１（ｂ）は図１（ａ）のＢ−Ｂ線による断面図、図１（ｃ）は図１（ａ）のＣ−Ｃ線による断面図である。図１（ａ）に示すように、トランジスタＴは、そのゲートＧが走査線ＳＬに接続され、そのドレインＤが信号線ＤＬに接続され、ソースＳが透明電極ＴＥに接続されている。チャネル領域を構成するアイランドＩＬがゲートＧの上方に形成されており、ドレインＤ及びソースＳが、アイランドＩＬの上方にて適長間隔をおいて対向するように形成されている。   1A is a plan view of the transistor 1 (T), FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line CC in FIG. It is sectional drawing by a line. As shown in FIG. 1A, the transistor T has a gate G connected to the scanning line SL, a drain D connected to the signal line DL, and a source S connected to the transparent electrode TE. An island IL constituting the channel region is formed above the gate G, and a drain D and a source S are formed above the island IL so as to face each other with an appropriate length interval.

図１（ｂ）及び図１（ｃ）に示すように、本実施形態の薄膜トランジスタ１（Ｔ）においては、透明絶縁性のガラス基板１０上に、走査線ＳＬに接続されたゲート電極１１（Ｇ）が形成されており、このゲート電極１１上を含めて基板１０上に、ＳｉＮからなるゲート絶縁膜１２が形成されている。ゲート電極１１は、Ｃｒ又はＡｌ等の金属層であり、スパッタ法により形成することができる。ゲート絶縁膜１２上には、ゲート電極１１上の位置に、アイランド（ＩＬ）状にポリシリコン膜１３が形成されており、このポリシリコン膜１３の上面及び側面を覆うようにして、水素化アモルファスシリコン膜（以下、ａ−Ｓｉ：Ｈ膜という）１４が形成されている。このａ−Ｓｉ：Ｈ膜１４の両端部上に重なるようにして、信号線ＤＬに接続されたドレイン電極１５ａ（Ｄ）及び画素の透明電極（ＴＥ）に接続されたソース電極１５ｂ（Ｓ）が形成されている。そして、全面にＳｉＮからなる保護膜１６が形成されている。   As shown in FIG. 1B and FIG. 1C, in the thin film transistor 1 (T) of this embodiment, the gate electrode 11 (G) connected to the scanning line SL on the transparent insulating glass substrate 10. The gate insulating film 12 made of SiN is formed on the substrate 10 including the gate electrode 11. The gate electrode 11 is a metal layer such as Cr or Al, and can be formed by sputtering. On the gate insulating film 12, a polysilicon film 13 is formed in an island (IL) shape at a position on the gate electrode 11. The polysilicon film 13 is covered with a hydrogenated amorphous film so as to cover the upper surface and side surfaces of the polysilicon film 13. A silicon film (hereinafter referred to as a-Si: H film) 14 is formed. The drain electrode 15a (D) connected to the signal line DL and the source electrode 15b (S) connected to the transparent electrode (TE) of the pixel are overlapped on both ends of the a-Si: H film 14. Is formed. A protective film 16 made of SiN is formed on the entire surface.

このように構成された逆スタガ構造の薄膜トランジスタにおいては、ａ−Ｓｉ：Ｈ膜１４がドレイン電極１５ａ及びソース電極１５ｂに電気的に接続されており、このａ−Ｓｉ：Ｈ膜１４とポリシリコン膜１３とによりチャネル領域が形成されている。そして、トランジスタの動作時には、電荷は、ポリシリコン膜１３とＳｉＮゲート絶縁膜１２との境界に生成し、この境界を移動するので、本実施形態の薄膜トランジスタは、電荷移動度が高く、オン電流が高い。このように、本実施形態の薄膜トランジスタは、オン電流が高いため、書き込み時間が短く、高速動作が可能である。   In the inverted staggered thin film transistor thus configured, the a-Si: H film 14 is electrically connected to the drain electrode 15a and the source electrode 15b. The a-Si: H film 14 and the polysilicon film 13 forms a channel region. During the operation of the transistor, charge is generated at the boundary between the polysilicon film 13 and the SiN gate insulating film 12 and moves along this boundary. Therefore, the thin film transistor of this embodiment has high charge mobility and high on-current. high. Thus, since the thin film transistor of this embodiment has a high on-state current, the writing time is short and high-speed operation is possible.

しかも、このポリシリコン膜１３からなるアイランドの周囲、即ち、ポリシリコン膜１３の側面には、非晶質ａ−Ｓｉ：Ｈ膜１４が形成されているので、アイランドの周囲を経路とする漏れ電流が少なく、オフ電流が低い。このように、オフ電流が低いため、電位の保持特性が優れており、液晶表示装置の表示部の画素トランジスタの電位が経時的に低下することを防止できる。このように、本実施形態によれば、オン電流が高く、オフ電流が低いトランジスタを得ることができる。従って、このトランジスタは、高速動作が可能であると共に、電位保持特性が優れており、消費電力が小さい。   In addition, since the amorphous a-Si: H film 14 is formed around the island made of the polysilicon film 13, that is, on the side surface of the polysilicon film 13, the leakage current is routed around the island. And low off-state current. In this manner, since the off-state current is low, the potential holding characteristics are excellent, and the potential of the pixel transistor in the display portion of the liquid crystal display device can be prevented from decreasing with time. Thus, according to this embodiment, a transistor having a high on-current and a low off-current can be obtained. Therefore, this transistor can operate at high speed, has excellent potential holding characteristics, and consumes little power.

次に、上述のごとく構成された薄膜トランジスタの製造方法について説明する。図４（ａ）乃至（ｃ）、図５（ａ）乃至（ｃ）及び図６（ａ）乃至（ｃ）は、本実施形態の製造方法を工程順に示す断面図である。図４（ａ）に示すように、ガラス基板１上に、Ｍｏ、Ｃｒ又はＡｌ等の金属膜からなるゲート電極２を、スパッタにより例えば２０００〜３０００Åの厚さに形成する。このゲート電極は、走査線ＳＬと同時にガラス基板１上にパターン形成することができる。   Next, a manufacturing method of the thin film transistor configured as described above will be described. 4A to 4C, FIGS. 5A to 5C, and FIGS. 6A to 6C are cross-sectional views illustrating the manufacturing method of this embodiment in the order of steps. As shown in FIG. 4A, a gate electrode 2 made of a metal film such as Mo, Cr or Al is formed on a glass substrate 1 to a thickness of, for example, 2000 to 3000 mm by sputtering. This gate electrode can be patterned on the glass substrate 1 simultaneously with the scanning line SL.

次に、図４（ｂ）に示すように、例えば、シラン及びＨ２ガスを原料ガスとし、２５０〜３００℃の低温のプラズマＣＶＤ法により、全面にＳｉＮ膜からなるゲート絶縁膜３を、例えば２５００〜５０００Åの厚さに形成する。その後、図４（ｃ）に示すように、ゲート絶縁膜３上に、例えば、プラズマＣＶＤ法により、第１のａ−Ｓｉ：Ｈ膜４ａを、例えば２００〜１０００Åの厚さに形成する。このａ−Ｓｉ：Ｈ膜４ａは、ＳｉＮ膜の形成後、基板を空気中に出さずに、別のチャンバに移動させて連続的に成膜する。ａ−Ｓｉ：Ｈ膜４ａは、シランとアンモニアとＨ２ガスを原料ガスとして成膜するが、Ｈ２ガスの混合は膜質改善に寄与するものの、その添加は任意である。その後、基板を取り出して、ａ−Ｓｉ：Ｈ膜４ａに対し、図３（ａ）に示すマイクロレンズアレイを使用したレーザアニールにより、チャネル領域形成予定領域のみにレーザ光を照射してアニールし、このチャネル領域形成予定領域を多結晶化し、ポリシリコン膜４を形成する。 Next, as shown in FIG. 4B, for example, the gate insulating film 3 made of an SiN film is formed on the entire surface by, for example, a low-temperature plasma CVD method using silane and H 2 gas at 250 to 300 ° C. It is formed to a thickness of 2500 to 5000 mm. Thereafter, as shown in FIG. 4C, a first a-Si: H film 4a is formed on the gate insulating film 3 by a plasma CVD method, for example, to a thickness of 200 to 1000 mm, for example. The a-Si: H film 4a is continuously formed after the SiN film is formed by moving the substrate to another chamber without taking it out into the air. The a-Si: H film 4a is formed by using silane, ammonia, and H 2 gas as source gases. Although the mixing of H 2 gas contributes to the improvement of the film quality, its addition is optional. Thereafter, the substrate is taken out, and the a-Si: H film 4a is annealed by irradiating only the channel region formation scheduled region with laser light by laser annealing using the microlens array shown in FIG. The channel region formation planned region is polycrystallized to form a polysilicon film 4.

図３に示すように、このマイクロレンズアレイを使用したレーザアニール装置は、光源３１から出射されたレーザ光を、レンズ群３２により平行ビームに成形し、マイクロレンズアレイ３５を介して被照射体３６に照射する。レーザ光源３１は、例えば、波長が３０８ｎｍ又は３５３ｎｍのレーザ光を例えば５０Ｈｚの繰り返し周期で放射するエキシマレーザである。マイクロレンズアレイ３５は、透明基板３４に多数のマイクロレンズ３５が配置されたものであり、レーザ光を被照射体３６としての薄膜トランジスタ基板に設定された薄膜トランジスタ形成領域に集光させるものである。透明基板３４は被照射体３６に平行に配置され、マイクロレンズ３５は、トランジスタ形成領域の配列ピッチの２以上の整数倍（例えば２）のピッチで配置されている。本実施形態の被照射体３６は、薄膜トランジスタ１であり、図４（ｃ）に示すチャネル領域形成予定領域にマイクロレンズ３５により集光されたレーザ光を照射する。なお、レンズ群３２により平行ビームに整形されたレーザビームは、その途中に遮光部材３３が配置されており、この遮光部材３３により、マイクロレンズ３４により集光されて被照射体３６に照射されたレーザビームのビーム形状を、例えば、矩形に整形することができる。従って、図１（ａ）に示すように、チャネル領域形成予定領域が矩形であっても、マイクロレンズ３４によりその領域を選択的に照射することができる。   As shown in FIG. 3, the laser annealing apparatus using the microlens array forms laser light emitted from the light source 31 into a parallel beam by the lens group 32, and the irradiated object 36 through the microlens array 35. Irradiate. The laser light source 31 is, for example, an excimer laser that emits laser light having a wavelength of 308 nm or 353 nm at a repetition period of, for example, 50 Hz. The microlens array 35 has a large number of microlenses 35 arranged on a transparent substrate 34, and condenses laser light on a thin film transistor formation region set on a thin film transistor substrate as an irradiated body 36. The transparent substrate 34 is arranged in parallel to the irradiation object 36, and the microlenses 35 are arranged at a pitch of an integer multiple of 2 (for example, 2) or more of the arrangement pitch of the transistor formation regions. The irradiated object 36 of the present embodiment is the thin film transistor 1 and irradiates the laser beam condensed by the microlens 35 onto the channel region formation scheduled region shown in FIG. The laser beam shaped into a parallel beam by the lens group 32 is provided with a light shielding member 33 in the middle thereof, and is condensed by the microlens 34 by this light shielding member 33 and applied to the irradiated object 36. The beam shape of the laser beam can be shaped into a rectangle, for example. Therefore, as shown in FIG. 1A, even if the channel region formation scheduled region is rectangular, the region can be selectively irradiated by the microlens 34.

次いで、図５（ａ）に示すように、ポリシリコン膜４及び第１のａ−Ｓｉ：Ｈ膜４ａの層の上の全面に、第２のａ−Ｓｉ：Ｈ膜５ａを、例えば２０００〜３０００Åの厚さに形成する。この第２のａ−Ｓｉ：Ｈ膜５ａの成膜条件は、第１のａ−Ｓｉ：Ｈ膜４ａの成膜条件と同様である。その後、基板をチャンバから取り出さずに連続的に、図５（ｂ）に示すように、ａ−Ｓｉ：Ｈ膜５ａの上に、ｎ＋Ｓｉ膜６ａを、例えば５００Å程度の厚さに形成する。このｎ＋Ｓｉ膜６ａは、シランにホスフィン等のＰを含有するガスを混合したガスを原料ガスとして、プラズマＣＶＤにより成膜することができる。この場合に、Ｈ２ガスを原料ガスに混合することもできる。次いで、基板を取り出し、図５（ｃ）に示すように、ａ−Ｓｉ：Ｈ膜４ａ、ａ−Ｓｉ：Ｈ膜５ａ及びｎ＋膜６ａを、ポリシリコン膜４の上方の部分と、ポリシリコン膜４の側面のａ−Ｓｉ：Ｈ膜４ａのみを残して、他の部分を除去し、アイランド状のチャネル領域をパターン形成する。 Next, as shown in FIG. 5A, a second a-Si: H film 5a is formed on the entire surface of the polysilicon film 4 and the first a-Si: H film 4a, for example, 2000 to 2000. It is formed to a thickness of 3000 mm. The film forming conditions for the second a-Si: H film 5a are the same as the film forming conditions for the first a-Si: H film 4a. Thereafter, without removing the substrate from the chamber, as shown in FIG. 5B, an n + Si film 6a is formed on the a-Si: H film 5a to a thickness of about 500 mm, for example. . The n + Si film 6a can be formed by plasma CVD using a gas in which a gas containing P such as phosphine is mixed with silane as a source gas. In this case, H 2 gas can be mixed with the raw material gas. Next, the substrate is taken out, and as shown in FIG. 5C, the a-Si: H film 4a, the a-Si: H film 5a, and the n + film 6a are formed on the polysilicon film 4 and the polysilicon film. Only the a-Si: H film 4a on the side surface of the film 4 is left, and other portions are removed, and an island-like channel region is patterned.

その後、図６（ａ）に示すように、ｎ＋Ｓｉ膜６ａの端部に接触するようにして、ドレイン電極７ａ及びソース電極７ｂを、例えば２０００〜５０００Åの厚さに形成する。次いで、図６（ｂ）に示すように、これらのドレイン電極７ａ及びソース電極７ｂをマスクとして、ｎ＋Ｓｉ膜６ａをエッチング除去することにより、ドレイン電極７ａ及びソース電極７ｂとａ−Ｓｉ：Ｈ膜５との間にのみｎ＋膜６を残す。 Thereafter, as shown in FIG. 6A, the drain electrode 7a and the source electrode 7b are formed to have a thickness of, for example, 2000 to 5000 mm so as to be in contact with the end portion of the n + Si film 6a. Next, as shown in FIG. 6B, the n + Si film 6a is removed by etching using the drain electrode 7a and the source electrode 7b as a mask, so that the drain electrode 7a and the source electrode 7b and the a-Si: H are removed. The n + film 6 is left only between the film 5.

その後、図６（ｃ）に示すように、ＳｉＮ膜からなる保護膜８を全面に形成する。図６（ｃ）には、図１（ｂ）の構造の対応する部分の符号を括弧書きで示している。図６（ｃ）に示す構造は、ソース・ドレイン電極とａ−Ｓｉ：Ｈ膜との間に、ｎ＋Ｓｉ膜６を設けた点が、図１（ｂ）の構造と異なる。このｎ＋Ｓｉ膜６は、ソース・ドレイン電極とａ−Ｓｉ：Ｈ膜との間の密着性を高め、接触抵抗を下げるためのものである。しかし、このｎ＋Ｓｉ膜の形成は任意であり、図１に示すようにｎ＋Ｓｉ膜を形成しなくても良く、又は他の手段で、ソース・ドレイン電極とａ−Ｓｉ：Ｈ膜との間の接触抵抗の低減を図ってもよい。 Thereafter, as shown in FIG. 6C, a protective film 8 made of a SiN film is formed on the entire surface. In FIG. 6 (c), the reference numerals of the corresponding parts of the structure of FIG. 1 (b) are shown in parentheses. The structure shown in FIG. 6C is different from the structure shown in FIG. 1B in that an n + Si film 6 is provided between the source / drain electrodes and the a-Si: H film. The n + Si film 6 is for increasing the adhesion between the source / drain electrodes and the a-Si: H film and decreasing the contact resistance. However, the formation of the n + Si film is optional, and the n + Si film may not be formed as shown in FIG. 1, or the source / drain electrode, the a-Si: H film, The contact resistance between the two may be reduced.

このようにして、図１に示す薄膜トランジスタを製造することができる。上記製造方法においては、マイクロレンズアレイを使用して、薄膜トランジスタのチャネル領域にのみレーザビームを照射することができるので、このレーザビームの照射によるａ−Ｓｉ：Ｈ膜のアニールにより、チャネル領域形成予定領域のみ結晶化してアイランド状のポリシリコン膜４を形成することができる。よって、ポリシリコン膜１３（４）の側面及び上面をａ−Ｓｉ：Ｈ膜１４（４ａ）が覆う構造の薄膜トランジスタを容易に製造することができる。   In this way, the thin film transistor shown in FIG. 1 can be manufactured. In the above manufacturing method, the microlens array can be used to irradiate only the channel region of the thin film transistor with the laser beam. Therefore, the channel region is scheduled to be formed by annealing the a-Si: H film by this laser beam irradiation. Only the region can be crystallized to form the island-shaped polysilicon film 4. Therefore, a thin film transistor having a structure in which the a-Si: H film 14 (4a) covers the side surface and the upper surface of the polysilicon film 13 (4) can be easily manufactured.

また、上述の説明から明らかなように、本実施形態の逆スタガ構造の薄膜トランジスタを、液晶表示装置の表示部の画素トランジスタとして使用することにより、表示部の画素トランジスタの高速化及び漏れ電流の低減による電位安定化が可能となる。また、本実施形態の逆スタガ構造の薄膜トランジスタを、液晶表示装置の周辺駆動回路のトランジスタとして使用することもでき、本実施形態の薄膜トランジスタは、チャネル領域にポリシリコン膜を使用しているので、高速動作が可能である。いずれにおいても、本実施形態の薄膜トランジスタは、オン電流が高く、オフ電流が低いので、液晶表示装置のトランジスタとして好適である。   Further, as apparent from the above description, the use of the inverted staggered thin film transistor of the present embodiment as the pixel transistor of the display unit of the liquid crystal display device speeds up the pixel transistor of the display unit and reduces the leakage current. This makes it possible to stabilize the potential. In addition, the thin film transistor having the inverted staggered structure of this embodiment can also be used as a transistor of a peripheral drive circuit of a liquid crystal display device. Since the thin film transistor of this embodiment uses a polysilicon film in the channel region, the high speed Operation is possible. In any case, since the thin film transistor of this embodiment has a high on-state current and a low off-state current, it is suitable as a transistor of a liquid crystal display device.

１，１０：ガラス基板
２，１１：ゲート電極
３，１２：ゲート絶縁膜
４，１３：ポリシリコン膜
４ａ，５，５ａ，１４：ａ−Ｓｉ：Ｈ膜
６，６ａ：ｎ＋膜
７ａ，１５ａ：ドレイン電極
７ｂ，１５ｂ：ソース電極
８，１６：保護膜 DESCRIPTION OF SYMBOLS 1,10: Glass substrate 2, 11: Gate electrode 3, 12: Gate insulating film 4, 13: Polysilicon film 4a, 5, 5a, 14: a-Si: H film 6, 6a: n + film 7a, 15a : Drain electrodes 7b, 15b: source electrodes 8, 16: protective film

Claims (5)

絶縁性基板と、この絶縁性基板の上に形成されたゲート電極と、このゲート電極上に形成されたゲート絶縁膜と、このゲート絶縁膜上の前記ゲート電極に対応する位置にアイランド状に形成されたポリシリコン膜と、このポリシリコン膜の上面及び側面を覆うように形成されたアモルファスシリコン膜と、このアモルファスシリコン膜の両端部に電気的に接続するように形成されたソース・ドレイン電極と、を有し、前記ポリシリコン膜は、第１のアモルファスシリコン膜を全面に形成した後、前記アイランドの部分のみをアニールして結晶化したものであり、前記アモルファスシリコン膜における前記ポリシリコン膜の側面を覆う部分は、前記第１のアモルファスシリコン膜の前記アイランドの周辺部分を残して他の部分を除去することにより形成したものであり、前記アモルファスシリコン膜における前記ポリシリコン膜の上面を覆う部分は、第２のアモルファスシリコン膜により形成されたものであることを特徴とする逆スタガ構造の薄膜トランジスタ。 An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode, and an island shape at a position corresponding to the gate electrode on the gate insulating film A polysilicon film formed, an amorphous silicon film formed so as to cover an upper surface and a side surface of the polysilicon film, and source / drain electrodes formed so as to be electrically connected to both ends of the amorphous silicon film, , have a, the polysilicon film is formed by forming a first amorphous silicon film on the entire surface, which crystallized by annealing only a portion of said island of said polysilicon film in the amorphous silicon film The part covering the side surface is to remove the other part leaving the peripheral part of the island of the first amorphous silicon film. Ri is obtained by forming the portion covering the upper surface of the polysilicon film in the amorphous silicon film, a thin film transistor of a reverse stagger structure, characterized in that one formed by the second amorphous silicon film. 前記ゲート絶縁膜はＳｉＮ膜であることを特徴とする請求項１に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the gate insulating film is a SiN film. 絶縁性基板上にゲート電極を形成する工程と、前記ゲート電極を含む前記基板上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に第１のアモルファスシリコン膜を形成する工程と、前記第１のアモルファスシリコン膜に対し前記ゲート電極に対応するアイランド状領域にレーザ光を照射してこの領域をポリシリコン膜に改質する工程と、この改質ポリシリコン領域及び第１のアモルファスシリコン領域上に第２のアモルファスシリコン膜を形成する工程と、前記改質ポリシリコン膜の上面及び側面を覆うアモルファスシリコン膜を残して他の部分のアモルファスシリコン膜を除去する工程と、残存したアモルファスシリコン膜の両端部に電気的に接続するようにソース・ドレイン電極を形成する工程と、を有することを特徴とする逆スタガ構造の薄膜トランジスタの製造方法。 Forming a gate electrode on an insulating substrate; forming a gate insulating film on the substrate including the gate electrode; forming a first amorphous silicon film on the gate insulating film; Irradiating the island region corresponding to the gate electrode with a laser beam to the first amorphous silicon film to modify the region into a polysilicon film, and the modified polysilicon region and the first amorphous silicon region; A step of forming a second amorphous silicon film thereon, a step of removing the amorphous silicon film in other portions while leaving the amorphous silicon film covering the upper and side surfaces of the modified polysilicon film, and the remaining amorphous silicon film And forming a source / drain electrode so as to be electrically connected to both ends of the The method for fabricating the thin film transistor hoop structure. 前記レーザ光の照射工程において、複数個のマイクロレンズを配置したマイクロレンズアレイによりレーザ光を集光して複数個のレーザビームを得、マトリクス状に配置された複数個の薄膜トランジスタの前記アイランド状領域を前記各レーザビームにより照射して、複数個の薄膜トランジスタのポリシリコン領域を形成することを特徴とする請求項３に記載の薄膜トランジスタの製造方法。 In the laser light irradiation step, the laser light is collected by a microlens array having a plurality of microlenses to obtain a plurality of laser beams, and the island regions of the plurality of thin film transistors arranged in a matrix form 4. The method of manufacturing a thin film transistor according to claim 3, wherein polysilicon regions of a plurality of thin film transistors are formed by irradiating each of the plurality of thin film transistors with a laser beam. 前記請求項１又は２に記載の薄膜トランジスタを、表示部の画素トランジスタとして使用することを特徴とする液晶表示装置。 A liquid crystal display device using the thin film transistor according to claim 1 or 2 as a pixel transistor of a display portion.
JP2009173709A 2009-07-24 2009-07-24 Thin film transistor, manufacturing method thereof, and liquid crystal display device Active JP5470519B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009173709A JP5470519B2 (en) 2009-07-24 2009-07-24 Thin film transistor, manufacturing method thereof, and liquid crystal display device
CN201080033821.5A CN102576733B (en) 2009-07-24 2010-07-16 Thin-film transistor, manufacturing method therefor, and liquid-crystal display device
PCT/JP2010/062075 WO2011010611A1 (en) 2009-07-24 2010-07-16 Thin-film transistor, manufacturing method therefor, and liquid-crystal display device
KR1020177003103A KR101803691B1 (en) 2009-07-24 2010-07-16 Thin-film transistor, manufacturing method therefor, and liquid-crystal display device
KR1020127004740A KR101713360B1 (en) 2009-07-24 2010-07-16 Thin-film transistor, manufacturing method therefor, and liquid-crystal display device
TW099124143A TWI509810B (en) 2009-07-24 2010-07-22 Thin-film transistor,manufacturing method thereof, and liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009173709A JP5470519B2 (en) 2009-07-24 2009-07-24 Thin film transistor, manufacturing method thereof, and liquid crystal display device

Publications (2)

Publication Number Publication Date
JP2011029411A JP2011029411A (en) 2011-02-10
JP5470519B2 true JP5470519B2 (en) 2014-04-16

Family

ID=43499084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009173709A Active JP5470519B2 (en) 2009-07-24 2009-07-24 Thin film transistor, manufacturing method thereof, and liquid crystal display device

Country Status (5)

Country Link
JP (1) JP5470519B2 (en)
KR (2) KR101803691B1 (en)
CN (1) CN102576733B (en)
TW (1) TWI509810B (en)
WO (1) WO2011010611A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11004682B2 (en) 2016-12-15 2021-05-11 Sakai Display Products Corporation Laser annealing apparatus, laser annealing method, and mask
US11024503B2 (en) 2016-03-04 2021-06-01 Sakai Display Products Corporation Laser annealing device, mask, thin film transistor, and laser annealing method

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012117439A1 (en) 2011-02-28 2012-09-07 パナソニック株式会社 Thin-film semiconductor device and manufacturing method therefor
KR102094568B1 (en) * 2012-10-17 2020-03-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
WO2016072024A1 (en) * 2014-11-07 2016-05-12 堺ディスプレイプロダクト株式会社 Method for manufacturing thin-film transistor, thin-film transistor, and display panel
JP6471379B2 (en) 2014-11-25 2019-02-20 株式会社ブイ・テクノロジー Thin film transistor, thin film transistor manufacturing method, and laser annealing apparatus
CN104460165B (en) * 2014-12-31 2017-06-16 深圳市华星光电技术有限公司 A kind of liquid crystal display and liquid crystal panel and array base palte
US10243003B2 (en) 2015-03-27 2019-03-26 Sakai Display Products Corporation Thin film transistor and display panel
JPWO2016157351A1 (en) * 2015-03-30 2018-01-18 堺ディスプレイプロダクト株式会社 Thin film transistor and display panel
JP6503458B2 (en) * 2015-04-20 2019-04-17 堺ディスプレイプロダクト株式会社 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND DISPLAY PANEL
WO2017046932A1 (en) * 2015-09-17 2017-03-23 堺ディスプレイプロダクト株式会社 Thin film transistor and method for manufacturing thin film transistor
CN108028283B (en) 2015-09-18 2021-03-02 堺显示器制品株式会社 Method for manufacturing thin film transistor and thin film transistor
WO2017072921A1 (en) * 2015-10-29 2017-05-04 堺ディスプレイプロダクト株式会社 Thin film transistor substrate manufacturing method
CN105633101A (en) * 2016-04-01 2016-06-01 京东方科技集团股份有限公司 TFT array substrate and manufacture method thereof, and display device
CN105870203B (en) * 2016-06-24 2019-05-10 京东方科技集团股份有限公司 A kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device
US10811286B2 (en) 2016-09-28 2020-10-20 Sakai Display Products Corporation Laser annealing device and laser annealing method
USD944655S1 (en) 2019-11-29 2022-03-01 Jirasak Rattanapaibooncharoen Double cup carrier

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0473988A1 (en) * 1990-08-29 1992-03-11 International Business Machines Corporation Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region
JP2814319B2 (en) * 1991-08-29 1998-10-22 株式会社日立製作所 Liquid crystal display device and method of manufacturing the same
JPH0563196A (en) 1991-09-04 1993-03-12 Hitachi Ltd Thin film semiconductor device, manufacture thereof and liquid crystal display device
SG46344A1 (en) * 1992-11-16 1998-02-20 Tokyo Electron Ltd Method and apparatus for manufacturing a liquid crystal display substrate and apparatus and method for evaluating semiconductor crystals
JPH07162006A (en) * 1993-12-09 1995-06-23 Hitachi Ltd Thin-film semiconductor device and manufacture thereof
JP2005057056A (en) * 2003-08-04 2005-03-03 Sharp Corp Thin film transistor and its manufacturing method
JP2005311164A (en) * 2004-04-23 2005-11-04 Nikon Corp Laser annealing apparatus
KR20070063969A (en) * 2005-12-16 2007-06-20 삼성전자주식회사 Thin film transistor array panel and method for manufacturing the same
JP2008140984A (en) * 2006-12-01 2008-06-19 Sharp Corp Semiconductor device, method of manufacturing the same, and display device
KR20080061924A (en) * 2006-12-28 2008-07-03 엘지디스플레이 주식회사 Thin film transistor substrate and manufacturing method thereof
JP5226259B2 (en) * 2007-08-21 2013-07-03 株式会社ジャパンディスプレイイースト Liquid crystal display
KR20090028318A (en) * 2007-09-14 2009-03-18 엘지디스플레이 주식회사 Array substrate and method of manufacturing the same
JP2009076707A (en) * 2007-09-21 2009-04-09 Hitachi Displays Ltd Method of manufacturing display device
JP5309387B2 (en) * 2007-09-28 2013-10-09 株式会社日立製作所 Semiconductor layer and semiconductor device and display device using the semiconductor layer
TWI481029B (en) * 2007-12-03 2015-04-11 半導體能源研究所股份有限公司 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024503B2 (en) 2016-03-04 2021-06-01 Sakai Display Products Corporation Laser annealing device, mask, thin film transistor, and laser annealing method
US11004682B2 (en) 2016-12-15 2021-05-11 Sakai Display Products Corporation Laser annealing apparatus, laser annealing method, and mask

Also Published As

Publication number Publication date
TW201115742A (en) 2011-05-01
CN102576733B (en) 2015-04-22
WO2011010611A1 (en) 2011-01-27
JP2011029411A (en) 2011-02-10
KR101803691B1 (en) 2017-12-28
KR20120033353A (en) 2012-04-06
KR101713360B1 (en) 2017-03-22
KR20170017008A (en) 2017-02-14
CN102576733A (en) 2012-07-11
TWI509810B (en) 2015-11-21

Similar Documents

Publication Publication Date Title
JP5470519B2 (en) Thin film transistor, manufacturing method thereof, and liquid crystal display device
US5895935A (en) Display device having a switch with floating regions in the active layer
JP2010003910A (en) Display element
JPWO2002095834A1 (en) Thin film transistor, active matrix display device, and manufacturing method thereof
WO2016157351A1 (en) Thin film transistor and display panel
JPWO2016170571A1 (en) Thin film transistor manufacturing method and display panel
JP6334057B2 (en) Thin film transistor and display panel
WO2016072024A1 (en) Method for manufacturing thin-film transistor, thin-film transistor, and display panel
CN110660867B (en) Thin film transistor, display device, and method for manufacturing thin film transistor
JP4683696B2 (en) Method for manufacturing semiconductor device
JP5363009B2 (en) Display device and manufacturing method thereof
JP2008085091A (en) Method for manufacturing thin film transistor, thin film transistor, and display unit
JP4986333B2 (en) Method for manufacturing semiconductor device
JP4656685B2 (en) Semiconductor device
KR20080047773A (en) Poly silicon thin film transistor substrate and manufacturing method thereof
TW583890B (en) Manufacturing method of active type organic electroluminescent display
JP2734359B2 (en) Thin film transistor and method of manufacturing the same
JP4545260B2 (en) Method for manufacturing semiconductor device
KR20100065739A (en) Fabricating method of electric device
KR20100130523A (en) Array substrate including thin film transistor of polycrystalline silicon and method of fabricating the same
JP4637333B2 (en) Method for manufacturing semiconductor device
KR100620888B1 (en) Method of Manufacturing Thin Film Transistor Using Crystallization Method of Amorphous Semiconductor Thin Film
JP3788021B2 (en) Thin film transistor and manufacturing method thereof
JP3845569B2 (en) Thin film semiconductor device, method for manufacturing the same, and electronic device including the device
KR100678737B1 (en) Method for fabricating polycrystalline silicon thin film transistor array substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120413

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131101

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131127

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131210

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250