CN105870203B - A kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device - Google Patents
A kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device Download PDFInfo
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- CN105870203B CN105870203B CN201610472946.7A CN201610472946A CN105870203B CN 105870203 B CN105870203 B CN 105870203B CN 201610472946 A CN201610472946 A CN 201610472946A CN 105870203 B CN105870203 B CN 105870203B
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- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 239000010409 thin film Substances 0.000 title claims abstract description 57
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- 239000004065 semiconductor Substances 0.000 claims abstract description 202
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 142
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- 239000012528 membrane Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
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- 230000000694 effects Effects 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims 2
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 31
- 150000002500 ions Chemical class 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 6
- -1 phosphonium ion Chemical class 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Thin Film Transistor (AREA)
Abstract
The embodiment of the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device, is related to field of display technology, can reduce leakage current while improving on-state current.The thin film transistor (TFT) includes source electrode, drain electrode, grid and semiconductor active layer, which includes the first sub- semiconductor layer and the second sub- semiconductor layer, and the first sub- semiconductor layer is close to grid；Wherein, in the first sub- semiconductor layer, the corresponding part in region at least between source electrode and drain electrode is made of polysilicon；In second sub- semiconductor layer, the corresponding part in region between source electrode and drain electrode includes at least amorphous silicon.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT) and preparation method thereof, array substrate, show
Showing device.
Background technique
With the development of LCD technology, to thin film transistor (TFT) (Thin Film Transistor, TFT) semiconductor layer
Electron mobility require to carry out higher, low-temperature polysilicon film transistor (Low Temperature Poly-silicon
Thin Film Transistor, LTPS TFT) it comes into being, since LTPS TFT mobility is high, while can be compared with low temperature
The advantages that condition is prepared under (being lower than 600 DEG C), and choice of the substrates is flexible, and preparation cost is lower, therefore be widely used
In the various electronic consoles including the electronic products such as computer, mobile phone.
Two of them important indicator about evaluation LTPS TFT device property superiority and inferiority is on-state current and leakage current, is opened
State electric current is bigger and the performance of the smaller then LTPS TFT device of leakage current is better.However, in the prior art, by improving source electrode
Electron mobility between drain electrode, Lai Tigao on-state current, so, when TFT is in OFF state, due to source electrode and drain electrode
Between electron mobility it is larger so that being difficult to form thorough PN structure in drain electrode side, and then leakage current is caused also to increase.
Certainly, the electron mobility between source electrode and drain electrode must be reduced accordingly if in order to reduce leakage current, cause ON state electric
Stream reduces.Therefore, in the prior art, it cannot guarantee that the on-state current of LTPS TFT device is larger and leakage current is smaller simultaneously.
Summary of the invention
The embodiment of the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device, Neng Gou
Leakage current is reduced while improving on-state current.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
On the one hand the embodiment of the present invention provides a kind of thin film transistor (TFT), including source electrode, drain electrode, grid and semiconductor active
Layer, the semiconductor active layer includes the first sub- semiconductor layer and the second sub- semiconductor layer stacked gradually, first son half
Conductor layer is close to the grid；Wherein, in the described first sub- semiconductor layer, the area at least between the source electrode and the drain electrode
The corresponding part in domain is made of polysilicon；In the second sub- semiconductor layer, with the area between the source electrode and the drain electrode
The corresponding part in domain includes at least amorphous silicon.
Further, the described first sub- semiconductor layer is made of polysilicon.
Further, the ratio of the thickness of the thickness of the described second sub- semiconductor layer and the described first sub- semiconductor layer is 2
~4.
Further, the described second sub- semiconductor layer is in the corresponding portion in region between the source electrode and the drain electrode
In point, partially it is made of amorphous silicon, rest part is made of polysilicon.
Further, in the described second sub- semiconductor layer, the region between the source electrode and the drain electrode is corresponding
Part is made of amorphous silicon.
Further, in the described second sub- semiconductor layer, in addition to the region between the source electrode and the drain electrode is opposite
Part other than the part answered is made of polysilicon.
Further, in the described second sub- semiconductor layer, along the thin film transistor channel width direction, by amorphous silicon
Its width of the part of composition is of same size with the semiconductor active layer；And/or the second sub- semiconductor layer and the source
In the corresponding part in region between pole and the drain electrode, along the thin film transistor channel length direction, it is made of amorphous silicon
Its length of part and the thin film transistor channel lenth ratio be 5%~20%.
Further, between the source electrode and the semiconductor active layer and it is described drain electrode with the semiconductor active
Ohmic contact layer is provided between layer.
The another aspect of the embodiment of the present invention provides a kind of array substrate, including film crystal described in any of the above-described kind
Pipe.
The another further aspect of the embodiment of the present invention provides a kind of display device, including above-mentioned array substrate.
The another further aspect of the embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), comprising: on underlay substrate
The step of forming source electrode, drain electrode and grid, further includes: the first amorphous silicon membrane is formed on the underlay substrate；To described
First amorphous silicon membrane is made annealing treatment to form the first sub- semiconductor layer；Wherein, in the described first sub- semiconductor layer, at least
The corresponding part in region between the source electrode and the drain electrode is made of polysilicon, and the first sub- semiconductor layer leans on
The nearly grid；The second amorphous silicon membrane is formed on the underlay substrate；The part of second amorphous silicon membrane is carried out
Annealing is to form the second sub- semiconductor layer；Wherein, in the described second sub- semiconductor layer, with the source electrode and the drain electrode
Between the corresponding part in region include at least amorphous silicon.
Further, after forming the first sub- semiconductor layer and the second sub- semiconductor layer, the method is also
It include: the described first sub- semiconductor layer and/or described second using ion lightly doped technique to the semiconductor active layer of composition
Sub- semiconductor layer is handled.
Further, the part to second amorphous silicon membrane is made annealing treatment to form the second sub- semiconductor
Layer includes: that the laser irradiation that laser transmitter projects go out is deviated from the underlay substrate one to second amorphous silicon membrane is located at
The mask plate of side, and between the mask plate and second amorphous silicon membrane, and with the mask plate through area
At the corresponding prism structure in position；In the prism structure under light convergence effect, second amorphous silicon membrane is right
Answer the mask plate through the position in area by the laser irradiation, to be made annealing treatment；Second amorphous silicon membrane exists
The zone position of blocking of the corresponding mask plate is not affected by the laser irradiation, so that in the second sub- semiconductor layer, with institute
The corresponding part in region stated between source electrode and the drain electrode includes at least amorphous silicon.
The another further aspect of the embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), comprising: on underlay substrate
The step of forming source electrode, drain electrode and grid, further includes: form amorphous silicon membrane on the underlay substrate；To the amorphous
Silicon thin film is made annealing treatment away from the side of the underlay substrate, so that the amorphous silicon membrane deviates from the underlay substrate
Side, and the corresponding portions turn in region at least between the source electrode and the drain electrode is polysilicon, to form the
One sub- semiconductor layer, the amorphous thin Film layers remain as amorphous silicon layer close to the side of the underlay substrate.
Further, it is formed after the first sub- semiconductor layer, the method also includes: by part annealing process,
The amorphous silicon membrane is handled so that the amorphous silicon membrane is close to the side of the underlay substrate, and with it is described
The corresponding part in region between source electrode and the drain electrode includes at least the amorphous silicon retained without annealing, to form the
Two sub- semiconductor layers.
The embodiment of the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device, and wherein this is thin
Film transistor includes source electrode, drain electrode, grid and semiconductor active layer, and semiconductor active layer includes the first sub- semiconductor layer and the
Two sub- semiconductor layers, the first sub- semiconductor layer is close to grid.Wherein, in the first sub- semiconductor layer, at least with source electrode and drain electrode it
Between the corresponding part in region be made of polysilicon；In second sub- semiconductor layer, the region between source electrode and drain electrode is opposite
The part answered includes at least amorphous silicon.
So, when thin film transistor (TFT) is in the conductive state, grid has one to the electronics between source electrode and drain electrode
Fixed attraction, so that become the main guiding region of electronics in semiconductor active layer close to grid side, and the semiconductor
In active layer in the first sub- semiconductor layer of grid side, the corresponding part in region at least between source electrode and drain electrode
It is made of the high polysilicon of electron mobility, the electronics under the influence of polysilicon of the high mobility, between source electrode and drain electrode
Movement speed increases, so that on-state current is larger；On this basis, when the thin film transistor (TFT) is in off state, grid pair
Electronics between source electrode and drain electrode has certain repulsive force, so that becoming electricity away from grid side in semiconductor active layer
The main guiding region of son, and in the semiconductor active layer in the second sub- semiconductor layer of grid side, in source electrode and drain electrode
Between include at least the low amorphous silicon of electron mobility and enable to source electrode and leakage under the influence of the amorphous silicon of the low mobility
Resistivity between pole increases, and the mobility between source electrode and drain electrode is thereby reduced, so that leakage current is smaller.I.e. should
Thin film transistor (TFT) can meet on-state current it is larger while leakage current it is smaller.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 a is a kind of structural schematic diagram of bottom gate type TFT provided in an embodiment of the present invention；
Fig. 1 b is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Fig. 2 a is a kind of structural schematic diagram of top gate type TFT provided in an embodiment of the present invention；
Fig. 2 b is a kind of structural schematic diagram of U-shaped TFT provided in an embodiment of the present invention；
Fig. 3 a is a kind of partial structure diagram of TFT provided in an embodiment of the present invention；
Fig. 3 b is the partial structure diagram of another kind TFT provided in an embodiment of the present invention；
Fig. 4 a is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Fig. 4 b is the structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention；
Fig. 5 a is a kind of partial structure diagram of TFT provided in an embodiment of the present invention；
Fig. 5 b is the partial structure diagram of another TFT provided in an embodiment of the present invention；
Fig. 5 c is the partial structure diagram of another TFT provided in an embodiment of the present invention；
Fig. 5 d is the partial structure diagram of another TFT provided in an embodiment of the present invention；
Fig. 6 a is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Fig. 6 b is the structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention；
Fig. 7 a is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Fig. 7 b is the structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention；
Fig. 8 a is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Fig. 8 b is the structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of another bottom gate type TFT provided in an embodiment of the present invention；
Figure 10 is a kind of structural schematic diagram of ADS type array substrate provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram of TN type array substrate provided in an embodiment of the present invention；
Figure 12 a is a kind of one of structural schematic diagram prepared during bottom gate type TFT provided in an embodiment of the present invention；
Figure 12 b is a kind of one of structural schematic diagram prepared during bottom gate type TFT provided in an embodiment of the present invention；
Figure 12 c is a kind of one of structural schematic diagram prepared during bottom gate type TFT provided in an embodiment of the present invention；
Figure 12 d is a kind of one of structural schematic diagram prepared during bottom gate type TFT provided in an embodiment of the present invention；
Figure 13 is a kind of structural schematic diagram of TFT in the prior art；
Figure 14 a is a kind of one of structural schematic diagram prepared during top gate type TFT provided in an embodiment of the present invention；
Figure 14 b is a kind of one of structural schematic diagram prepared during top gate type TFT provided in an embodiment of the present invention；
Figure 14 c is a kind of structural schematic diagram for preparing top gate type TFT provided in an embodiment of the present invention；
Figure 15 is a kind of structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention；
Figure 16 is the structural schematic diagram of another top gate type TFT provided in an embodiment of the present invention.
Appended drawing reference:
10- polysilicon；20- amorphous silicon；11- mask plate；12- prism structure；30- pixel electrode；40- public electrode；
100- underlay substrate；101- source electrode；102- drain electrode；103- grid；104- ohmic contact layer；105- light shield layer；200- grid is exhausted
Edge layer；300- semiconductor active layer；The sub- semiconductor layer of 301- first；The sub- semiconductor layer of 302- second；The first amorphous silicon of 110- is thin
Film；The second amorphous silicon membrane of 120-；130- amorphous silicon membrane；131- amorphous silicon layer.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of thin film transistor (TFT), as described in Fig. 1 a, including source electrode 101, drain electrode 102, grid 103
And semiconductor active layer 300, the semiconductor active layer 300 include the first sub- semiconductor layer 301 and the second sub- semiconductor layer
302, the first sub- semiconductor layer 301 is close to grid 103.Wherein, in the first sub- semiconductor layer 301, at least with source electrode 101 and drain electrode
The corresponding part region A1 between 102 is made of polysilicon 10, in the second sub- semiconductor layer 302, with source electrode 101 and drain electrode
The corresponding part in region between 102 includes at least amorphous silicon 20.
Herein it should be noted that the corresponding part region A1 between above-mentioned source electrode 101 and drain electrode 102 refers to, such as
Shown in Fig. 3 a, region after TFT conducting where the TFT channel that is formed, therefore, for convenience of explanation, below by source electrode 101 and leakage
Region A1 between pole 102 is referred to as channel region A1).Wherein, the length L of TFT channel is between source electrode 101 and drain electrode 102
Distance；The width W of TFT channel is the width of source electrode 101 or drain electrode 102 and 103 lap of semiconductor active layer.
So, when thin film transistor (TFT) is in the conductive state, grid has one to the electronics between source electrode and drain electrode
Fixed attraction, so that become the main guiding region of electronics in semiconductor active layer close to grid side, and the semiconductor
In active layer in the first sub- semiconductor layer of grid side, the corresponding part in region at least between source electrode and drain electrode
It is made of the high polysilicon of electron mobility, the electronics under the influence of polysilicon of the high mobility, between source electrode and drain electrode
Movement speed increases, so that on-state current is larger；On this basis, when the thin film transistor (TFT) is in off state, grid pair
Electronics between source electrode and drain electrode has certain repulsive force, so that becoming electricity away from grid side in semiconductor active layer
The main guiding region of son, and in the semiconductor active layer in the second sub- semiconductor layer of grid side, in source electrode and drain electrode
Between include at least the low amorphous silicon of electron mobility and enable to source electrode and leakage under the influence of the amorphous silicon of the low mobility
Resistivity between pole increases, and the mobility between source electrode and drain electrode is thereby reduced, so that leakage current is smaller.I.e. should
Thin film transistor (TFT) can meet on-state current it is larger while leakage current it is smaller.
Herein it should also be noted that, first, above-mentioned first sub- semiconductor layer 301 refers to close to grid 103, such as
It is as shown in Figure 1a, grid 103 relative to gate insulating layer 200 closer to for the bottom gate type TFT of underlay substrate 100, at this
The first sub- semiconductor layer 301 and the second sub- semiconductor layer 302 are stacked gradually on gate insulating layer 200, so that the first son half
Conductor layer 301 is close to grid 103；
In another example for as shown in Figure 2 a, gate insulating layer 200 is relative to grid 103 closer to underlay substrate 100
For top gate type TFT, the first sub- semiconductor layer 301 and the second sub- semiconductor have been stacked gradually below the gate insulating layer 200
Layer 302, so that the first sub- semiconductor layer 301 is close to grid 103, certainly preferred top gate type TFT further includes light shield layer 105,
Illumination leakage current is generated to avoid because of illumination.
Second, TFT of the invention can be as shown in Figure 3a source electrode 101 and drain electrode 102 symmetrical TFT, or such as
U-shaped structure TFT shown in Fig. 2 b.This is not limited by the present invention.
Detailed illustration is carried out to the structure of the above-mentioned first sub- semiconductor layer 301 below.
The corresponding part in region in above-mentioned first sub- semiconductor layer 301, at least between source electrode 101 and drain electrode 102
It is made of and refers to polysilicon 10, part corresponding with channel region A1 is only by 10 structure of polysilicon in the first sub- semiconductor layer 301
At, and in the corresponding part in region other than channel region A1 whether include polysilicon 10 without limitation.For example, can be with
It as shown in Figure 1a, include polysilicon in part corresponding with the region other than channel region A1 in the first sub- semiconductor layer 301
10；Can also be as shown in Figure 1 b, part corresponding with the region other than channel region A1 is whole in the first sub- semiconductor layer 301
It is made of amorphous silicon 20.
On this basis, to part corresponding with channel region A1 in the first sub- semiconductor layer 301 only by polysilicon 10
Composition is illustrated.
Specifically, part corresponding with channel region A1 is by polysilicon 10 in semiconductor layer 301 for example sub- for first
The region of composition, can be as shown in Figure 3a, on TFT channel length direction O-O ', the length and TFT channel in 10 region of polysilicon
Length L it is identical；On TFT channel width direction P-P ', the width in 10 region of polysilicon and the width W of TFT channel are identical.?
Can be as shown in Figure 3b, on TFT channel length direction O-O ', the length and the length L phase of TFT channel in 10 region of polysilicon
Together, on TFT channel width direction P-P ', the width in 10 region of polysilicon is of same size with the first sub- semiconductor layer 301.
Since in TFT, during conducting, electronics mainly passes through channel region A1 and is moved to drain electrode 102 from source electrode 101,
So, the electron mobility of two kinds of TFT shown in Fig. 3 a and Fig. 3 b is close to identical, but from the aspect of manufacture craft, by
The equivalent width of polysilicon 10 peak width and channel region A1 in the sub- semiconductor layer 301 of first of the TFT shown in Fig. 3 a,
It is more demanding to manufacture craft, it is therefore, currently preferred, using 10 peak width of polysilicon shown in Fig. 3 b and the first son half
Conductor layer 301 it is of same size, do not need the equivalent width of stringent control polysilicon 10 peak width and channel region A1, energy
It is enough to simplify manufacture craft on the basis of reaching identical electron mobility, reduce cost of manufacture.
On this basis, in order to further increase the electron mobility between source electrode 101 and drain electrode 102, as shown in fig. 4 a
Bottom gate type TFT or top gate type TFT as shown in Figure 4 b, the first sub- semiconductor layer 301 can be all by 10 structure of polysilicon
At.So, when TFT is connected, the main guiding region close to 103 side of grid is all made of polysilicon 10, Neng Gougeng
The electron mobility between source electrode 101 and drain electrode 102 is improved in big degree.
The above-mentioned second sub- semiconductor layer 301 is illustrated below.
It at least wraps the corresponding part in region in above-mentioned second sub- semiconductor layer 302 between source electrode 101 and drain electrode 102
It includes amorphous silicon 20 to refer to, part corresponding with channel region A1 includes amorphous silicon 20 in the second sub- semiconductor layer 302, and right
In the corresponding part in region other than channel region A1 whether include amorphous silicon 20 without limitation.For example, can be such as Fig. 1 a
It is shown, it include amorphous silicon 20 in part corresponding with the region other than channel region A1 in the second sub- semiconductor layer 302；?
Can be as shown in Figure 1 b, it does not include by non-that the corresponding part in region other than channel region A1, which is all made of polysilicon 10,
The part that crystal silicon 20 is constituted.
In addition, in semiconductor layer 302 sub- for second in part corresponding with channel region A1 amorphous silicon 20 shape
Without limitation with number.It can also as shown in Figure 5 b be multiple circles for example, can as shown in Figure 5 a be a rectangle.
Below by way of specific embodiment in the second sub- semiconductor layer 302 part corresponding with channel region A1 it is specific
Structure is illustrated.
Embodiment one
As shown in Figure 1 b, part corresponding with channel region A1 in the second sub- semiconductor layer 302 is all set to non-
Crystal silicon 20.
Embodiment two
Part is set by 20 structure of amorphous silicon by part corresponding with channel region A1 in the second sub- semiconductor layer 302
At, rest part is made of polysilicon 10, below in the corresponding part channel region A1, partially it is made of amorphous silicon 20,
Rest part is made of polysilicon 10 and is described in detail.
For example, top gate type TFT shown in bottom gate type TFT and Fig. 6 b as shown in Figure 6 a, in the second sub- 302 ditch of semiconductor layer
In the A1 of road region, middle section is to be made of amorphous silicon 20, and two side portions are to be made of polysilicon 10.
On this basis, in the second sub- semiconductor layer 302 in part corresponding with channel region A1, in TFT channel
On the direction width P-P ', such as shown in Fig. 5 a, the width in 20 region of amorphous silicon can be less than the width W of TFT channel region A1；When
So, the width in 20 region of amorphous silicon can also be more than or equal to the width W of TFT channel region A1, such as shown in Fig. 5 c, amorphous silicon 20
The width in region can be D with the width of the second sub- semiconductor layer 302, the width W greater than channel region A1.
In the TFT as shown in above-mentioned Fig. 5 a, on the direction channel width P-P ', there is no pass through completely in amorphous silicon 20 region
The width of entire channel region A1 is worn, so, when TFT is in OFF state, part electronics can be from 20 region of amorphous silicon
Two sides in width direction enter source electrode 101 by drain electrode 102, so that leakage current cannot be effectively reduced, therefore, the present invention is excellent
In the second sub- semiconductor layer 302 of use of choosing in part corresponding with channel region A1, the width in 20 region of amorphous silicon should
Width W more than or equal to channel region A1 includes so amorphous by the width direction in entire channel region A1
20 region of silicon, can effectively reduce leakage current.
Further, currently preferred, it, will be in the second sub- semiconductor layer 302 using in above-mentioned TFT as shown in Figure 5 c
The width in 20 region of amorphous silicon is set as the width phase with the second sub- semiconductor layer 302 in part corresponding with channel region A1
Together, the width for not needing strict control 10 region of polysilicon in the production process is identical as the width W of channel region, so as to
It is enough to simplify technique on the basis of guaranteeing to effectively reduce leakage current, reduce cost of manufacture.
On this basis, as shown in Figure 5 c, the part corresponding with channel region A1 in the second sub- semiconductor layer 302
In, middle section is made of amorphous silicon portion 20, and two side portions are made of polysilicon 10, and along TFT channel width direction P-P '
On, the width in 20 region of amorphous silicon and the of same size of the second sub- semiconductor layer 302 are all D, along the side TFT channel length O-O '
To the ratio of part its length L1 and TFT channel length L that are made of amorphous silicon 20 are 5%~20%.For example, working as TFT channel
When length L is 5 μm, the length L2 in 20 region of amorphous silicon is between 0.5 μm to 1.0 μm.
Specifically, the above-mentioned length by 20 region of amorphous silicon and TFT channel lenth ratio are set as 5%~20%, be because
For when the length of amorphous silicon 20 and TFT channel lenth ratio are less than 5%, due to amorphous in region between source electrode 101 and drain electrode 102
The accounting in 20 region of silicon is too small, cannot effectively reduce the electron mobility of channel region A1, and then cannot effectively reduce TFT
Leakage current；If the length in 20 region of amorphous silicon and TFT channel lenth ratio are greater than 20%, due to source electrode 101 and drain electrode 102
Between in region amorphous silicon 20 accounting it is too big, the electron mobility of TFT channel can be made to be greatly reduced, so that TFT
On-state current reduces.
In another example top gate type TFT shown in bottom gate type TFT and Fig. 7 b as shown in Figure 7a, in the second sub- semiconductor layer 302
In in part corresponding with channel region A1, middle section is to be made of polysilicon 10, and two side portions are made of amorphous silicon 20.
On this basis, it is preferred that as fig 5d, corresponding with channel region A1 in the second sub- semiconductor layer 302
Part in, middle section is made of polysilicon 10, and two side portions are made of amorphous silicon 20, it is also preferred that along TFT channel
On width direction P-P ', the width in 20 region of amorphous silicon and the of same size of the second sub- semiconductor layer 302 are all D, along TFT channel
The ratio of the direction length O-O ', its length of part being made of amorphous silicon 20 and TFT channel length is 5%~20%.In this feelings
Under condition, although 20 region of amorphous silicon of two side portions is Chong Die in the close side of channel with source electrode 101 and drain electrode 102, due to this
Overlapping region very little, can be ignored, and be L2 when the two side portions are 20 zone length of amorphous silicon, TFT channel is long therefore
When degree is L, then the sum of the length in 20 region of two side portions amorphous silicon is 2*L2, and with TFT channel length L ratio, i.e. 2*L2/L exists
Between 5% to 20%.For example, 2*L2 is in 0.4 μ for the sum of the length in 20 region of two sides amorphous silicon when TFT channel length L is 4 μm
Between m to 0.8 μm, i.e., the length L2 in 20 region of unilateral amorphous silicon is between 0.2 μm to 0.4 μm.
For another example top gate type TFT shown in bottom gate type TFT and Fig. 8 b as shown in Figure 8 a, by the second sub- semiconductor layer 302
In part corresponding with channel region A1 be divided into two parts, a part is made of polysilicon 10, and another portion is by amorphous silicon 20
It constitutes.
On the basis of above-described embodiment one and embodiment two, in order to further increase between source electrode 101 and drain electrode 102
Electron mobility can will be opposite with exterior domain with channel region A1 in the second sub- semiconductor layer 302 as shown in Fig. 4 a and Fig. 6 b
The part answered is all set to polysilicon 10.So, electronics is enabled to pass through more 20th areas of polysilicon from source electrode 101
Domain enters drain electrode 102, and then can further increase the electron mobility between source electrode 101 and drain electrode 102.
Further, currently preferred, as shown in fig. 4 a, by of the thickness H1 of the second sub- semiconductor layer 302 and first
The ratio of the thickness H2 of semiconductor layer 301 is 2~4.
Specifically, the first sub- semiconductor layer 301 is the main guiding region of electronics, in TFT due to when TFT is in ON state
When in OFF state, the second sub- semiconductor layer 302 is the main guiding region of electronics, so, in 300 thickness of semiconductor active layer
In the case where certain, on the one hand, when the ratio of the thickness of the thickness and the first sub- semiconductor layer 301 of the second sub- semiconductor layer 302
When less than 2, so that the thickness of the first sub- semiconductor layer 301 is excessive, on-state current is larger, but due to the second sub- semiconductor layer
302 thickness is too small, to cannot effectively achieve the purpose that reduce leakage current；When the thickness of the second sub- semiconductor layer 302 and
When the ratio of the thickness of one sub- semiconductor layer 301 is greater than 4 so that the thickness of the second sub- semiconductor layer 302 is excessive, leakage current compared with
It is small, but since the thickness of the first sub- semiconductor layer 301 is too small, and cannot effectively achieve the purpose that increase on-state current.Cause
This, currently preferred, the ratio of the thickness H2 of the sub- semiconductor layer 301 of thickness H1 and first of the second sub- semiconductor layer 302 is 2
~4, can be while guaranteeing larger on-state current, leakage current is smaller.
On this basis, it in order to reduce the contact resistance between source electrode 101 and drain electrode 102 and semiconductor active layer 300, obtains
Obtain better TFT characteristic.By taking bottom gate type TFT as an example, as shown in figure 9, between source electrode 101 and semiconductor active layer 300, and
Ohmic contact layer 104 is provided between drain electrode 102 and semiconductor active layer 300.Wherein the ohmic contact layer 104 is mainly by amorphous
Silicon and conductive ion are constituted.Specifically, can be the amorphous silicon layer of doping phosphonium ion, or the amorphous silicon of doping boron ion
Layer, which is not limited by the present invention.
The embodiment of the present invention also provides a kind of array substrate, which includes any of the above-described kind of thin film transistor (TFT), tool
There is beneficial effect identical with the thin film transistor (TFT) that previous embodiment provides.Since previous embodiment is to the thin film transistor (TFT)
Beneficial effect be described in detail, details are not described herein again.
For example, as shown in Figure 10, which can be a kind of ADS (Advanced-Super Dimensional
Switching, referred to as ADS, advanced super dimension field switch) type array substrate, wherein in the ADS type array substrate, common electrical
Pole 40 and the setting of the different layer of pixel electrode 30, wherein the electrode for being located at upper layer includes multiple strip electrodes, positioned at the electrode packet of lower layer
Containing multiple plate-shaped electrodes.Optionally, as shown in Figure 10, the electrode comprising multiple strip electrodes positioned at upper layer is pixel electrode
30, the plate-shaped electrode positioned at lower layer is public electrode 40.It is of course also possible to be positioned at upper layer multiple strip electrodes be it is public
Electrode, the plate-shaped electrode positioned at lower layer is pixel electrode, and specific structure is no longer shown.
In another example as shown in figure 11, which can also be a kind of TN (Twist Nematic, twisted-nematic) type
Array substrate, wherein pixel electrode 30 is located in array substrate, and public electrode is located at the array substrate to the color membrane substrates of box
Upper (not shown).Certainly the above is only to applied to above-mentioned TFT array substrate for example, for other kinds of
Details are not described herein again for array substrate.
The embodiment of the present invention also provides a kind of display device, which includes above-mentioned array substrate, above-mentioned array base
Plate includes any of the above-described kind of thin film transistor (TFT) again, and therefore, which has the thin film transistor (TFT) provided with previous embodiment
Identical beneficial effect.Since previous embodiment is described in detail the beneficial effect of the thin film transistor (TFT), this
Place repeats no more
The embodiment of the present invention also provides a kind of preparation method of thin film transistor (TFT).
Below by taking bottom gate type TFT and top gate type TFT as shown in Figure 2 a as shown in Figure 1a as an example, to the specific system of TFT
Preparation Method is described in detail.
For example, the preparation method includes: when making bottom gate type TFT as shown in Figure 1a
It is initially formed gate metal layer on underlay substrate 100, which is patterned to form grid 103.?
It is formed with production gate insulating layer 200 on the underlay substrate 100 of grid 103.In the underlay substrate for being formed with gate insulating layer 200
On 100, semiconductor active layer 300, specific making step are made according to the following steps are as follows:
Step S101, the first amorphous as figure 12 a shows, is formed on the underlay substrate 100 for being formed with gate insulating layer 200
Silicon thin film 110.
Specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma can be used
Body enhances chemical vapour deposition technique) the first amorphous is formed in the underlay substrate 10 for being formed with grid 105 and gate insulating layer 106
Silicon thin film 110.
Step S102, as shown in Figure 12b, the first amorphous silicon membrane 110 is made annealing treatment to form the first son and partly lead
Body layer 301；Wherein, in the first sub- semiconductor layer 301, at least the position to be formed of source electrode 101 and drain electrode 102 positions to be formed it
Between the corresponding part in region be made of polysilicon 10.
Herein it should be noted that above-mentioned make annealing treatment the first amorphous silicon membrane 110 to form the first son and partly lead
Body layer 301 refers to, can make annealing treatment to the part of the first amorphous silicon membrane 110, to be formed in TFT as shown in Figure 1a
The first sub- semiconductor layer 301, source electrode 101 and drain electrode 102 between the corresponding part in region and the region other than
Partial region is made of polysilicon 10；Flood annealing can also be carried out to the first amorphous silicon membrane 110, be formed such as Fig. 4 a institute
The sub- semiconductor layer 301 of first in TFT shown, is all made of polysilicon 20.
Step S103, as shown in fig. 12 c, second is formed on the underlay substrate 100 for being formed with the first sub- semiconductor layer 301
Amorphous silicon membrane 120.
Specifically, it is non-to form second on the underlay substrate 10 for being formed with the first sub- semiconductor layer 301 using PECVD
Polycrystal silicon film 120.
Step S104, as shown in figure 12d, the part of the second amorphous silicon membrane 120 is made annealing treatment to form second
Sub- semiconductor layer 302；Wherein, in the second sub- semiconductor layer 302, in 102 positions to be formed of the position to be formed of source electrode 101 and drain electrode
Between the corresponding part in region include at least amorphous silicon 20.
Specifically, being made annealing treatment by taking the second amorphous silicon membrane 120 as an example to the part of the second amorphous silicon membrane 120
Can be to form the second sub- semiconductor layer 302, using selectively annealed (Selective Laser Annealing) technique pair
Second amorphous silicon membrane 120 carries out part annealing, specific selectively annealed process as shown in figure 12d, by laser emitter
The laser irradiation launched deviates from the mask plate 11 of 10 side of underlay substrate to the second amorphous silicon membrane 120 is located at, and is located at
Through the corresponding prism structure 12 in the position of area A between the mask plate 11 and the second amorphous silicon membrane 120 and with mask plate 11
Place.The prism structure 12 has certain convergence effect to light, can increase the exposure intensity of laser, thus in prism structure
Under 12 convergence effect so that the second amorphous silicon membrane 120 corresponding mask plate 11 through area A position by laser irradiation,
To be made annealing treatment, so that corresponding second amorphous silicon membrane, 120 region is by the transformation polycrystalline of amorphous silicon 20 at the position
Silicon 10 forms polysilicon region.In addition, laser cannot penetrate the blocked area B of mask plate 11, therefore the second amorphous silicon membrane 120
It is not affected by laser irradiation in the blocked area B location of corresponding mask plate 11, corresponding second amorphous silicon membrane, 120th area blocked area B
Domain remains amorphous silicon 20, forms amorphous silicon region, so as to shape in the second sub- semiconductor layer 302 and in source electrode 101
20 region of amorphous silicon is included at least at the corresponding part between 102 positions to be formed of position and drain electrode.
Finally, as shown in Figure 1a, forming data metal on the underlay substrate 100 for being formed with the second sub- semiconductor layer 302
Layer, is patterned the data metal layer, forms source electrode 101 and drain electrode 102.
For example, the preparation method includes: when making top gate type TFT as shown in Figure 2 a
S201, the second amorphous silicon membrane 120 is formed on the underlay substrate 100 for being formed with light shield layer 105.
S202, the part of the second amorphous silicon membrane 120 is made annealing treatment to form the second sub- semiconductor layer 302；Its
In, in the second sub- semiconductor layer 302, the region between 102 positions to be formed of the position to be formed of source electrode 101 and drain electrode is corresponding
Part include at least amorphous silicon 20.
S203, the first amorphous silicon membrane 110 is formed on the underlay substrate 100 for being formed with the second sub- semiconductor layer 302.
S204, the first amorphous silicon membrane 110 is made annealing treatment to form the first sub- semiconductor layer 301；Wherein, first
In sub- semiconductor layer 301, the region at least between 102 positions to be formed of the position to be formed of source electrode 101 and drain electrode is corresponding
Part is made of polysilicon 10, and the first sub- semiconductor layer 301 is close to grid 103.
Finally, forming gate insulating layer 200 on the underlay substrate 100 for being formed with the first sub- semiconductor layer 301, formed
Gate metal layer is formed on the underlay substrate 100 of gate insulating layer 200, which is patterned to form grid 103；
Passivation layer and data metal layer are once formed on the underlay substrate 100 for being formed with grid 103, structure is carried out to data metal layer
Figure forms source electrode 101 and drain electrode 102.
It should be noted that above-mentioned top gate type TFT and above-mentioned bottom gate type TFT are only different in the formation sequence of each layer,
The production method of corresponding layer is same or similar, and details are not described herein again.
Herein it should also be noted that, the composition in the embodiment of the present invention can refer to include photoetching process, or, including photoetching work
Skill and etch step, while can also include other techniques for being used to form predetermined pattern such as printing, ink-jet；Photoetching process,
Refer to the technique for forming figure using photoresist, mask plate, exposure machine etc. including technical process such as film forming, exposure, developments.It can
The corresponding patterning processes of structure choice formed according to the present invention.
It on this basis, can in order to reduce the contact resistance between source electrode 101 and drain electrode 102 and semiconductor active layer 300
Between the step of making source electrode 101 and drain electrode 102 and the step of making semiconductor active layer 300, ohmic contact layer is made
104, by taking TFT shown in Fig. 9 as an example, the preparation method of the TFT further include: in the substrate for being formed with the second sub- semiconductor layer 302
On substrate 10, in 102 positions to be formed of the corresponding position to be formed of source electrode 101 and drain electrode, ohmic contact layer 104 is formed.
Specifically, the ohmic contact layer 104 can be by by silane (CH4) and phosphine (PH3) be made of pecvd process
Adulterate the amorphous silicon layer of phosphonium ion；Silane (CH can certainly be used4) and borine (B2H6) amorphous silicon of doping boron ion is made
Layer, which is not limited by the present invention, as long as being capable of forming the ohmic contact layer 104 being made of amorphous silicon and conductive ion, with drop
Contact resistance between low source electrode 101 and drain electrode 102 and semiconductor active layer 300.
In summary, it can be seen that as shown in figure 9, the present invention in the second sub- semiconductor layer 302 by being located at source electrode
20 region of amorphous silicon is arranged in part between 101 and drain electrode 102, using the low electron mobility of amorphous silicon 20 itself, to reach
Reduce the purpose of TFT leakage current；By by region is corresponding between source electrode 101 and drain electrode 102 in the second sub- semiconductor layer 302
Part be made of polysilicon 10, using the high electron mobility of polysilicon 10 itself, improve TFT on-state current to reach
Purpose；And by the way that ohmic contact layer 104 is arranged between source electrode 101 and drain electrode 102 and semiconductor active layer 300, to reduce
Contact resistance between source electrode 101 and drain electrode 102 and semiconductor active layer 300.
And in the prior art, it as shown in figure 13, needs through ion doping technique twice, is just able to achieve identical as the present invention
Technical effect.Wherein, primary ions doping process is, to corresponding to source electrode 101 and drain electrode 102 in semiconductor active layer 300
Region is handled using the highly doped technique of ion, to reduce between source electrode 101 and drain electrode 102 and semiconductor active layer 300
Contact resistance；Another secondary ion doping process is, between source electrode 102 and the intrinsic area N, and drain electrode 102 with the intrinsic area N it
Between, using additional LDD (the Lightly Doped Drain) structure of ion lightly doped technique, to realize the base for guaranteeing on-state current
On plinth, the purpose of TFT leakage current is reduced.
Equipment due to carrying out ion doping technique is more complicated and more expensive and ion doping technics comparing is multiple
It is miscellaneous, need to be made annealing treatment after the completion of each ion implanting, and during ion implanting to the concentration of ion with
And the control accuracy requirement of distribution is higher, so that preparing the process complications of TFT, and cost of manufacture is higher.Therefore, in reality
Under the premise of existing identical technical effect, ion doping technique twice is used in the prior art, and the present invention is mixed without ion
It is miscellaneous, so as to reach simplified preparation process, reduce the purpose of cost of manufacture.
Further, since amorphous silicon 20 is after being changed into polysilicon 10, can to constitute region itself by polysilicon 10
With certain voltage, without being in neutrality, to bring certain influence to the threshold voltage of TFT.It is asked to solve the technology
It inscribes, after the semiconductor active layer 300 being made of the first sub- semiconductor layer 301 and the second sub- semiconductor layer 302 that can complete,
Using ion lightly doped technique to the first sub- semiconductor layer 301 and/or the second sub- semiconductor of the semiconductor active layer 300 of composition
Layer 302 is handled.So, low dense by being carried out to the first sub- semiconductor layer 301 and/or the second sub- semiconductor layer 302
After phosphonium ion or the boron ion injection of degree, the voltage on the semiconductor active layer 300 can be eliminated, and then eliminate to subsequent
The threshold voltage for the TFT being prepared affects.
The embodiment of the present invention also provides another preparation method of top gate type thin film transistor, this method comprises:
Step S301, it as shown in figures 14a, on the underlay substrate 100 for being formed with light shield layer 105 and passivation layer, is formed
Amorphous silicon membrane 130.
Step S302, as shown in fig. 14b, which is carried out at annealing away from the side of underlay substrate 100
Reason so that amorphous silicon membrane 130 deviate from underlay substrate 100 side, and at least with the position to be formed of source electrode 101 and drain electrode
The amorphous silicon 20 of the corresponding part in region between 102 positions to be formed is changed into polysilicon 10, and (Figure 14 b is thin with amorphous silicon
Film 130, which is completely reformed into away from the side amorphous silicon 20 of underlay substrate 100, to be illustrated for polysilicon 10), to form the
One sub- semiconductor layer 301, at this point, amorphous thin Film layers 130 remain as amorphous silicon layer 131 close to the side of underlay substrate 100.
It should be noted that the production of semiconductor active layer 300 can be terminated after completing step S102, i.e., it is above-mentioned non-
Crystal silicon layer 131 is equivalent to the second sub- semiconductor layer 302.In addition, for being served as a contrast in step S302 by deviating to amorphous silicon membrane 130
The side of substrate 100 is made annealing treatment to form the first sub- semiconductor layer 301, and amorphous thin Film layers 130 are close to substrate
The side of substrate 100 remains as the process of amorphous silicon layer 131, can use quasi-molecule laser annealing (Excimer Laser
Annealing, ELA) technology, realize that annealing is deep by accurately controlling focus and the laser energy of laser in annealing process
The control of degree.
Then, as shown in figure 14 c, on sub- 302 underlay substrate 100 of semiconductor layer of above-mentioned formation second formed grid 103,
Source electrode 101 and drain electrode 102.
In addition, as shown in figure 15 to preparing, source electrode 101 and drain electrode 102 are located at semiconductor active layer 300 close to substrate base
For the top gate type TFT of 100 side of plate, only slightly have difference in the production order of source electrode 101, drain electrode 102 and grid 103, it is right
Identical as the preparation method of semiconductor active layer 300 in Figure 14 c in the preparation of semiconductor active layer 300, details are not described herein again.
Certainly, after completing above-mentioned steps S102, the production of semiconductor active layer 300, the preparation of the TFT can be continued
Method can also include:
By part annealing process, amorphous silicon membrane 130 is handled, as shown in figure 16, so that amorphous silicon membrane
130 close to the side of underlay substrate 100, and the corresponding part in region between source electrode 101 and drain electrode 102 includes at least not
The amorphous silicon 20 retained by annealing, to form the second sub- semiconductor layer 302.
Specifically, in above-mentioned second sub- 302 forming process of semiconductor layer, by controlling the focus of laser and the energy of laser
Amount, and selectively annealed technique is combined to anneal the part of amorphous silicon layer 131 of the side close to underlay substrate forms the
Two sub- semiconductor layers 302.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of thin film transistor (TFT), including source electrode, drain electrode and grid, which is characterized in that the thin film transistor (TFT) further includes half
Conductor active layer, the semiconductor active layer include the first sub- semiconductor layer and the second sub- semiconductor layer, and first son is partly led
Body layer is close to the grid；
Wherein, in the described first sub- semiconductor layer, the corresponding part in region at least between the source electrode and the drain electrode
It is made of polysilicon；In the second sub- semiconductor layer, the corresponding part in region between the source electrode and the drain electrode
Including at least amorphous silicon；
The second sub- semiconductor layer is in the corresponding part in region between the source electrode and the drain electrode, the first setting
Region is made of polysilicon, remaining region is made of amorphous silicon；
Europe is provided between the source electrode and the semiconductor active layer and between the drain electrode and the semiconductor active layer
Nurse contact layer；
The thin film transistor (TFT) be top gate type thin film transistor in the case where, the first sub- semiconductor layer with described ohm
It is included at least in the contact area of contact layer: the amorphous silicon region being made of amorphous silicon；
Alternatively, the thin film transistor (TFT) be bottom gate thin film transistor in the case where, the second sub- semiconductor layer with institute
It states in the contact area of ohmic contact layer and includes at least: the amorphous silicon region being made of amorphous silicon.
2. thin film transistor (TFT) according to claim 1, which is characterized in that brilliant for bottom gate thin film in the thin film transistor (TFT)
In the case where body pipe, the first sub- semiconductor layer is made of polysilicon.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of the second sub- semiconductor layer with it is described
The ratio of the thickness of first sub- semiconductor layer is 2~4.
4. thin film transistor (TFT) according to claim 1, which is characterized in that in the described second sub- semiconductor layer, along described
Thin film transistor channel width direction, its width of the part being made of amorphous silicon are of same size with the semiconductor active layer；
And/or in the second sub- semiconductor layer part corresponding with the region between the source electrode and the drain electrode, along described
Thin film transistor channel length direction, its length of the part being made of amorphous silicon are with the thin film transistor channel lenth ratio
5%~20%.
5. a kind of array substrate, which is characterized in that including the described in any item thin film transistor (TFT)s of Claims 1-4.
6. a kind of display device, which is characterized in that including the array substrate described in claim 5.
7. a kind of preparation method of thin film transistor (TFT), comprising: source electrode, drain electrode are being formed on underlay substrate and the step of grid,
It is characterized by further comprising:
The first amorphous silicon membrane is formed on the underlay substrate；
First amorphous silicon membrane is made annealing treatment to form the first sub- semiconductor layer；Wherein, first son is partly led
In body layer, the corresponding part in region at least between the source electrode and the drain electrode is made of polysilicon, and described first
Sub- semiconductor layer is close to the grid；
The second amorphous silicon membrane is formed on the underlay substrate；
The part of second amorphous silicon membrane is made annealing treatment to form the second sub- semiconductor layer；Wherein, described second
In sub- semiconductor layer, the corresponding part in region between the source electrode and the drain electrode includes at least amorphous silicon；Described
Two sub- semiconductor layers are in the corresponding part in region between the source electrode and the drain electrode, and the first setting regions is by polycrystalline
Silicon is constituted, remaining region is made of amorphous silicon.
8. the preparation method of thin film transistor (TFT) according to claim 7, which is characterized in that partly led forming first son
After body layer and the second sub- semiconductor layer, the method also includes:
Using ion lightly doped technique to the described first sub- semiconductor layer and/or second son of the semiconductor active layer of composition
Semiconductor layer is handled.
9. the preparation method of thin film transistor (TFT) according to claim 7, which is characterized in that described to second amorphous silicon
The part of film is made annealing treatment to form the second sub- semiconductor layer and include:
The laser irradiation that laser transmitter projects go out is deviated from into the underlay substrate side to second amorphous silicon membrane is located at
Mask plate, and between the mask plate and second amorphous silicon membrane, and penetrate with the mask plate position in area
It sets at corresponding prism structure；
In the prism structure under light convergence effect, second amorphous silicon membrane is in the correspondence mask plate through area
Position is by the laser irradiation, to be made annealing treatment；
Second amorphous silicon membrane is not affected by the laser irradiation in the zone position of blocking of the correspondence mask plate, so that institute
The second sub- semiconductor layer is stated in the corresponding part in region between the source electrode and the drain electrode, the first setting regions by
Polysilicon is constituted, remaining region is made of amorphous silicon.
10. a kind of preparation method of thin film transistor (TFT), comprising: source electrode, drain electrode are being formed on underlay substrate and the step of grid,
It is characterized by further comprising:
Amorphous silicon membrane is formed on the underlay substrate；
The amorphous silicon membrane is made annealing treatment away from the side of the underlay substrate, so that the amorphous silicon membrane is carried on the back
Side from the underlay substrate, and the corresponding portions turn in region at least between the source electrode and the drain electrode is more
Crystal silicon, to form the first sub- semiconductor layer, the amorphous thin Film layers remain as amorphous silicon close to the side of the underlay substrate
Layer；By part annealing process, the amorphous silicon membrane is handled, so that the amorphous silicon membrane is close to the substrate
The side of substrate, and the corresponding part in region between the source electrode and the drain electrode includes at least and protects without annealing
The amorphous silicon stayed, to form the second sub- semiconductor layer.
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| EP4177961A1 (en) * | 2021-10-14 | 2023-05-10 | Samsung Display Co., Ltd. | Thin-film transistor substrate, manufacturing method thereof, and display apparatus employing the thin-film transistor substrate |
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| CN108735819B (en) * | 2017-04-13 | 2020-07-14 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display substrate |
| CN107039284A (en) * | 2017-04-17 | 2017-08-11 | 武汉华星光电技术有限公司 | A kind of method for making low-temperature polysilicon film transistor |
| CN109713043A (en) * | 2017-10-25 | 2019-05-03 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and its manufacturing method, array substrate, electronic device |
| CN109742024B (en) * | 2019-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Laser annealing method and array substrate |
| CN110972508B (en) * | 2019-03-04 | 2022-05-03 | 京东方科技集团股份有限公司 | Thin film transistor and method for manufacturing thin film transistor |
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| CN111276546B (en) * | 2020-02-20 | 2022-07-29 | 武汉华星光电技术有限公司 | Display panel and manufacturing method thereof |
| CN112542386B (en) * | 2020-11-03 | 2022-07-08 | 北海惠科光电技术有限公司 | Method and apparatus for manufacturing display panel and thin film transistor |
| CN112817173B (en) * | 2021-01-05 | 2023-10-17 | 深圳市华星光电半导体显示技术有限公司 | Sensing assembly, manufacturing method thereof and display panel |
| CN116195033A (en) * | 2021-09-29 | 2023-05-30 | 京东方科技集团股份有限公司 | Amorphous silicon thin film transistor, preparation method thereof and display panel |
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| KR20060032454A (en) * | 2004-10-12 | 2006-04-17 | 삼성전자주식회사 | Fabrication method of poly crystalline si tft |
| JP2008306080A (en) * | 2007-06-11 | 2008-12-18 | Hitachi Ltd | Optical sensor element, and optical sensor apparatus and image display apparatus using the same |
| KR101703511B1 (en) * | 2008-06-27 | 2017-02-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Thin film transistor |
| JP5470519B2 (en) * | 2009-07-24 | 2014-04-16 | 株式会社ブイ・テクノロジー | Thin film transistor, manufacturing method thereof, and liquid crystal display device |
| JP2012004411A (en) * | 2010-06-18 | 2012-01-05 | Sharp Corp | Method of manufacturing semiconductor device, semiconductor device, and display device |
| CN105826398A (en) * | 2016-06-15 | 2016-08-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method |
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