KR20100065739A - Fabricating method of electric device - Google Patents

Abstract

PURPOSE: A manufacturing method of an electric device is provided to suppress a metal film in forming a microcrystalline silicon by inserting a barrier layer into an active layer and using the barrier as an etch stopper in forming an ohmic contact layer. CONSTITUTION: A gate metal pattern including a gate electrode of an TFT is formed on a substrate(SUB). The barrier layer and a photo-thermal conversion layer are formed on the substrate where the gate metal pattern is formed. A laser light is projected on the photo-thermal conversion layer to remove the photo-thermal conversion layer. A barrier layer and a microcrystal silicon layer are patterned successively, and an active layer(ACT) located on the gate electrode and an etch stopper pattern(ES) located on the surface the active layer are formed. A data metal pattern, the ohmic contact are formed on the substrate in which the etch stopper pattern is formed. The etch stopper pattern protects the active layer from plasma damage in the etching process for forming the ohmic contact.

Description

Manufacturing method of electronic device {FABRICATING METHOD OF ELECTRIC DEVICE}

The present invention relates to a method of manufacturing an electronic device comprising a microcrystalline semiconductor material.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, various flat displays such as liquid crystal display devices (LCDs) and active matrix type organic light emitting diode displays (AMOLEDs) have been developed. Devices have been studied and most of them are already used as display devices in various fields. As a switching element used in a display device such as an LCD or an AMOLED, a thin film transistor (hereinafter, referred to as a TFT) is mainly used.

Amorphous silicon (a-Si) among the materials used as the semiconductor layer of the TFT is widely used due to the advantages of a simple process and low temperature, but low electron mobility in amorphous silicon (about 2). Cm 2 / Vsec or less) acts as a disturbing factor in the operation characteristics of the switching of the TFT, and also makes it difficult to integrate the TFT with the drive circuitry for controlling the TFT at high speed.

On the other hand, since poly silicon has an electron mobility of about 100 times higher than amorphous silicon at about 20 to 550 cm 2 / Vsec, it is suitable for high-speed switching in high resolution and large area display devices. This is because polysilicon is composed of several grains and has fewer defects than amorphous silicon (a-Si). Polysilicon can typically be obtained by heat treating amorphous silicon (a-Si) through an Excimer Laser Annealing processor. However, since the narrow laser beam is progressively scanned across the substrate surface through several shots, this processor is relatively slow and the polysilicon is not uniform depending on the position due to the non-uniformity of the laser shot.

Accordingly, recently, a technology for changing amorphous silicon (a-Si) into microcrystalline silicon (μc-Si) by using indirect thermal crystallization (ITC) technology has emerged. ITC technology uses infrared diode laser (800nm ~ 810nm) which is more stable than existing UV excimer laser (308nm) to irradiate light, converts the irradiated energy into heat in the photo-thermal conversion layer, and then generates the instantaneous high temperature It is a technique of forming microcrystalline silicon (μc-Si) using the heat of. A conventional TFT using microcrystalline silicon (μc-Si) may have a structure as shown in FIGS. 1 and 4.

First, as shown in FIG. 1, the microcrystalline silicon (μc-Si) TFT may be implemented in the same bottom gate structure as the amorphous silicon (a-Si) TFT. 2 and 3, the main manufacturing process of FIG. 1 is described. After completion of the gate electrode G on the substrate SUB, a gate insulating film GI and amorphous silicon (a-Si) are deposited. Subsequently, a heat-transition layer (HTL) including a metal such as molybdenum (Mo) is deposited, and then irradiated with light to the light-to-heat conversion layer (HTL) by using an infrared laser to irradiate the amorphous silicon. (a-Si) is crystallized sequentially. Subsequently, the light-to-heat conversion layer (HTL) is removed through a wet etching (WE) process to form an active layer (ACT) including microcrystalline silicon (μc-Si), and then generate on the surface of the active layer (ACT). The metal remaining film is removed by a dry etching (DE) process. Subsequently, n + amorphous silicon (a-Si) is deposited and then dry etched to form an ohmic contact layer. The source electrode S and the drain electrode D are formed on the ohmic contact layer, and the transparent electrode ITO is formed through the passivation layer PAS to contact the drain electrode D. However, the conventional TFT manufacturing method as shown in Figs. 1 to 3 has the following problems. First, in this conventional TFT manufacturing method, after the wet etching of the light-to-heat conversion layer (HTL), a residual film of metal-silicide having a predetermined thickness remains on the microcrystalline silicon (μc-Si). A dry etching process must be added to remove the film. In addition, since the microcrystalline silicon (μc-Si) at the bottom of the residual film after etching is to be left, the thickness of the microcrystalline silicon (μc-Si) may be increased unless the etching etching conditions are developed in consideration of the dry etching margin. There is a limit to thinning. Second, the conventional TFT manufacturing method is expected to deteriorate the channel portion due to plasma damage during n + amorphous silicon (a-Si) dry etching. Therefore, the thickness of the active layer (ACT) must be maintained above a certain level due to the dry etching margin. Increasing resistance may lead to deterioration of device characteristics.

Next, the microcrystalline silicon (μc-Si) TFT may be implemented in the same bottom gate structure as that of the amorphous silicon (a-Si) TFT as shown in FIG. 4. 4 is a microcrystalline silicon (μc-Si) TFT to which an etch stopper (ES) is applied, and reduces the thickness of the active layer ACT by eliminating plasma damage of the channel portion. Referring to the main manufacturing process of FIG. 4 using FIGS. 5 and 6, after completion of the gate electrode G on the substrate SUB, the gate insulating layer GI and the amorphous silicon (a-Si) are deposited. Subsequently, a heat-transition layer (HTL) including a metal such as molybdenum (Mo) is deposited, and then irradiated with light to the light-to-heat conversion layer (HTL) by using an infrared laser to irradiate the amorphous silicon. (a-Si) is crystallized sequentially. Subsequently, the light-to-heat conversion layer (HTL) is removed through wet etching (WE) to form an active layer (ACT) including microcrystalline silicon (μc-Si), and then generated on the surface of the active layer (ACT). The metal residue is removed by dry etching (DE). Subsequently, the etch stopper (ES) is deposited on the active layer (ACT) and then patterned to correspond to the channel portion forming region, and n + amorphous silicon (a-Si) is deposited on the patterned etch stopper (ES) and then dried. Etching forms an ohmic contact layer. In this case, the etch stopper (ES) serves to protect the channel portion from plasma damage during dry etching for forming the ohmic contact layer. The source electrode S and the drain electrode D are formed on the ohmic contact layer, and the transparent electrode ITO is formed through the passivation layer PAS to contact the drain electrode D. However, in the conventional TFT manufacturing method as shown in Figs. 4 to 6, after the wet etching of the light-to-heat conversion layer (HTL), a glass of metal-silicon compound (Metal-Silicide) having a predetermined thickness on the microcrystalline silicon (μc-Si) The film remains and a separate dry etching process must be added to remove this residual film. In addition, a separate mask process for patterning the etch stopper ES is required. Therefore, the conventional TFT manufacturing method as shown in FIGS. 4 to 6 has a disadvantage in that the process becomes complicated.

Accordingly, it is an object of the present invention to provide a method for manufacturing an electronic device that can prevent deterioration of a device and simplify a process in the manufacture of an electronic device including a microcrystalline silicon TFT.

In order to achieve the above object, a method of manufacturing an electronic device including a microcrystalline silicon TFT according to an embodiment of the present invention, the gate metal including the gate electrode of the TFT by depositing and patterning a gate metal layer on the substrate over the entire surface Forming a pattern; A gate insulating film, an amorphous silicon layer, a barrier layer, and a light-to-heat conversion layer are deposited on the substrate on which the gate metal pattern is formed, and the light-to-heat conversion layer is irradiated with laser light to form the amorphous silicon layer as microcrystalline silicon. After crystallization to a layer, removing the light-to-heat conversion layer; Patterning the barrier layer and the microcrystalline silicon layer sequentially using the same mask to form an active layer on the gate electrode and an etch stopper pattern on the active layer; And a data metal pattern including a source electrode and a drain electrode of the TFT by sequentially depositing an amorphous silicon layer and a data metal layer containing n + impurities on the substrate on which the etch stopper pattern is formed, and sequentially patterning the data metal pattern and the data metal pattern. And forming an ohmic contact layer to reduce ohmic resistance between the active layers; The etch stopper pattern may protect the active layer from plasma damage during an etching process for forming the ohmic contact layer.

Depositing and patterning an inorganic insulating layer on the substrate on which the data metal pattern is formed to form a protective layer exposing a portion of the drain electrode; And depositing a transparent conductive metal on the substrate on which the protective layer is formed and patterning the transparent conductive pattern to form a transparent conductive pattern in contact with the drain electrode of the TFT.

The barrier layer is characterized in that it comprises at least one or more of oxide film-based, such as SiOx, ZnO2, ITO, and SiNx.

The barrier layer is characterized in that it has a thickness of 10nm ~ 50nm.

The laser is characterized in that the infrared diode laser for generating light of 800nm ~ 810nm wavelength.

In the method of manufacturing an electronic device according to the present invention, a barrier layer is inserted between an active layer and a light-to-heat conversion layer, and the barrier layer is used as an etch stopper when forming an ohmic contact layer, thereby forming a metal residual film during crystallization of microcrystalline silicon. It suppresses production and protects the channel portion of the active layer from plasma damage when forming the ohmic contact layer. Accordingly, the manufacturing method of the electronic device according to the present invention can prevent the deterioration of the device to improve the device characteristics, a separate dry etching process for removing the metal residual film and a separate mask process for patterning the etch stopper. Removal can simplify the process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7A to 7I.

7A to 7I are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an electronic device according to an embodiment of the present invention.

The manufacturing method of the electronic device will be described sequentially.

First, referring to FIG. 7A, one selected from Al, Mo, Cr, Cu, Al alloy, Mo alloy, Cu alloy, or two or more metals or alloys on a substrate SUB made of transparent glass or plastic material The gate metal layer is deposited on the entire surface by a sputtering process. The gate metal layer is patterned through a photolithography process using a first mask and a wet etching process. As a result, a gate metal pattern including a gate line and a gate electrode G of a TFT protruding from the gate line is formed on the substrate SUB.

Referring to FIG. 7B, an inorganic insulating material such as SiO ₂ or SiNx used as the gate insulating film GI and a semiconductor material of amorphous silicon (a-Si) are used on the substrate SUB on which the gate metal pattern is formed. continuous deposition in an enhanced Chemical Vapor Deposition process. Subsequently, a barrier material and heat transfer such as Al, Mo, Cr, Cu, Al alloy, Mo alloy, Cu alloy, and the like are formed on the substrate SUB on which the inorganic insulating material and the amorphous silicon (a-Si) semiconductor material are formed. The material is deposited entirely in a sputtering process to form a barrier layer (BAR) and a light-to-heat conversion layer (HTL). Here, the barrier material must have 1) thermal stability and 2) high heat transfer efficiency. In other words, since the instantaneous temperature rises to about 1000 ° C. during crystallization, the barrier material must be free from thermal by-products generation, stress generation and denaturation, and microcrystalline silicon (μc-Si) of amorphous silicon (a-Si) is possible. In order to be able to transfer heat generated in its upper light-to-heat conversion layer (HTL) to its lower amorphous silicon (a-Si). Examples of suitable materials include oxide film series such as SiOx, ZnO2, ITO, and SiNx.

Referring to FIG. 7C, an infrared diode laser is disposed on a substrate on which an inorganic insulating material, an amorphous silicon (a-Si), a barrier layer (BAR), and a light-to-heat conversion layer (HTL) are sequentially deposited. The infrared diode laser scans infrared rays of 800 nm to 810 nm wavelength on the light-to-heat conversion layer (HTL) by a scan method. This infrared light is converted into heat in the light-to-heat conversion layer (HTL) and then applied to the semiconductor material of amorphous silicon (a-Si) through the barrier layer (BAR). Accordingly, amorphous silicon (a-Si) in the portion to which heat is applied is converted into microcrystalline silicon (μc-Si). In this case, the barrier layer (BAR) is located between the light-to-heat conversion layer (HTL) and the semiconductor material, so that the metal-silicon residual film is formed at the interface of the microcrystalline silicon (μc-Si) during the crystallization of the semiconductor material. It serves to suppress the creation. To this end, the barrier layer BAR may have a thickness of about 10 nm to about 200 nm. When the thickness of the barrier layer BAR is less than 10 nm, the force capable of suppressing residual film generation is decreased. When the thickness of the barrier layer BAR exceeds 200 nm, the heat transfer efficiency is lowered. According to the present invention, since no metal-silicon residual film is formed at the interface of the microcrystalline silicon (μc-Si), a separate dry etching process for removing the residual film is not required, and thus, a conventional process This is simplified.

Referring to FIG. 7D, the light-to-heat conversion layer (HTL) is removed through a wet etching process.

Referring to FIG. 7E, the barrier layer BAR is patterned through a photolithograph process using a second mask and a wet etching process. The microcrystalline silicon (μc-Si) layer is patterned through a dry etching process using the patterned barrier layer (BAR) as a mask. As a result, the active layer ACT positioned on the gate electrode G with the gate insulating layer GI therebetween and the etch stopper pattern ES positioned on the active layer ACT are formed on the substrate SUB. According to the present invention, since the active layer ACT and the etch stopper pattern ES are formed with the same mask, a separate mask process for the etch stopper pattern ES is not necessary. Accordingly, the number of processes is reduced compared to the conventional.

Referring to FIG. 7F, an amorphous silicon layer containing n + impurities is deposited on the substrate SUB on which the active layer ACT and the etch stopper pattern ES are formed, and then on the amorphous silicon layer containing n + impurities. A data metal layer SD selected from any one of Al, Mo, Cr, Cu, Al alloys, Mo alloys, Cu alloys, or two or more metals or alloys is deposited on the entire surface by a sputtering process.

Referring to FIG. 7G, the data metal layer SD is patterned through a photolithography process using a third mask and a wet etching process. The amorphous silicon layer containing n + impurities is patterned through a dry etching process using the patterned data metal layer SD as a mask. As a result, a data metal pattern including the source electrode S and the drain electrode D of the TFT and an ohmic contact layer n + for reducing ohmic resistance between the data metal pattern and the active layer ACT are formed on the substrate SUB. do. Here, since the etch stopper pattern ES is positioned on the active layer ACT during dry etching of n + amorphous silicon, the channel portion of the active layer ACT is not damaged by the plasma for dry etching. Accordingly, the present invention can reduce the thickness of the active layer ACT regardless of the dry etching margin, it is possible to solve the conventional problem that the device characteristics are degraded due to the increase in the thickness of the active layer (ACT).

Referring to FIG. 7H, an inorganic insulating material such as SiO ₂ or SiNx is deposited by PECVD on a substrate SUB on which a data metal pattern is formed, and then the inorganic layer is formed through a photolithography process using a fourth mask and a dry etching process. The insulating material is partially removed. As a result, a protective layer PAS is formed, which has a pass hole PH exposing a part of the drain electrode D of the TFT.

Referring to FIG. 7I, after the transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the substrate SUB on which the protective layer PAS is formed, the sputtering process is used to completely deposit a fifth mask. The transparent conductive metal is partially removed through the photolithography process and the dry etching process. As a result, a transparent conductive pattern TE connected to the drain electrode D of the TFT is formed.

8A and 8B are graphs showing device (TFT) characteristics in the related art and the present invention, respectively.

In the TFT fabricated by the method for manufacturing an electronic device according to the embodiment of the present invention, the channel portion thereof is not damaged by plasma damage, and furthermore, the degree of freedom for the thickness of the active layer is increased, so that the thickness of the active layer may be lower than that of the conventional art. . Accordingly, the TFT of the present invention shown in Fig. 8B has improved device characteristics compared with the conventional one as shown in Fig. 8A.

As described above, in the method of manufacturing an electronic device according to the present invention, the barrier layer is inserted between the active layer and the light-to-heat conversion layer, and the barrier layer is used as an etch stopper when forming the ohmic contact layer. The formation of the metal residual film during crystallization is suppressed and the channel portion of the active layer is protected from plasma damage during the formation of the ohmic contact layer. Accordingly, the manufacturing method of the electronic device according to the present invention may prevent deterioration of the device, thereby improving device characteristics, and using a separate dry etching process for removing the metal remaining film and a separate mask process for patterning the etch stopper. Removal can simplify the process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view showing an example of a conventional microcrystalline silicon TFT.

2 and 3 show the main manufacturing process for FIG.

4 shows another example of a conventional microcrystalline silicon TFT.

5 and 6 show the main manufacturing process for FIG.

7A to 7I are cross-sectional views according to a process sequence for explaining a method for manufacturing an electronic device according to an embodiment of the present invention.

8A and 8B are graphs showing device characteristics in the prior art and the present invention, respectively.

Claims (5)

In the manufacturing method of the electronic device containing a microcrystalline silicon TFT, Depositing and patterning a gate metal layer on the substrate to form a gate metal pattern including the gate electrode of the TFT; A gate insulating film, an amorphous silicon layer, a barrier layer, and a light-to-heat conversion layer are deposited on the substrate on which the gate metal pattern is formed, and the light-to-heat conversion layer is irradiated with laser light to form the amorphous silicon layer as microcrystalline silicon. After crystallization to a layer, removing the light-to-heat conversion layer; Patterning the barrier layer and the microcrystalline silicon layer sequentially using the same mask to form an active layer on the gate electrode and an etch stopper pattern on the active layer; And A data metal pattern including a source electrode and a drain electrode of the TFT by patterning the amorphous silicon layer containing the n + impurity and the data metal layer on the substrate on which the etch stopper pattern is formed and then sequentially patterning the data metal pattern; Forming an ohmic contact layer to reduce ohmic resistance between the active layers; And the etch stopper pattern protects the active layer from plasma damage during an etching process for forming the ohmic contact layer. The method of claim 1, Depositing and patterning an inorganic insulating layer on the substrate on which the data metal pattern is formed to form a protective layer exposing a portion of the drain electrode; And And depositing and patterning a transparent conductive metal on the substrate on which the protective layer is formed to form a transparent conductive pattern in contact with the drain electrode of the TFT. The method of claim 1, The barrier layer is an electronic device manufacturing method comprising at least one of an oxide film series, such as SiOx, ZnO2, ITO, and SiNx. The method of claim 1, The barrier layer has a thickness of 10nm ~ 200nm electronic device manufacturing method. The method of claim 1, The laser is an electronic device manufacturing method, characterized in that the infrared diode laser for generating light of 800nm ~ 810nm wavelength.

Images