CN104460165B - A kind of liquid crystal display and liquid crystal panel and array base palte - Google Patents
A kind of liquid crystal display and liquid crystal panel and array base palte Download PDFInfo
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- CN104460165B CN104460165B CN201410856154.0A CN201410856154A CN104460165B CN 104460165 B CN104460165 B CN 104460165B CN 201410856154 A CN201410856154 A CN 201410856154A CN 104460165 B CN104460165 B CN 104460165B
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- insulating barrier
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- base palte
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The present invention relates to a kind of liquid crystal display and liquid crystal panel and array base palte, array base palte includes multiple pixel cells.Thin film transistor (TFT) is provided with each pixel cell.Thin film transistor (TFT) includes stacking gradually glass substrate, the first insulating barrier, the second insulating barrier and the 3rd insulating barrier from bottom to up.The first low-temperature polycrystalline silicon layer that can be covered by the second insulating barrier is provided with the upper surface of the first insulating barrier.The two ends of the first low-temperature polycrystalline silicon layer are connected with the first source electrode being formed between the 3rd insulating barrier and the second insulating barrier and the first drain electrode respectively.The first grid that can be covered by the first insulating barrier is provided with the upper surface of glass substrate, while the lower surface of first grid can cover orthographic projection of first low-temperature polycrystalline silicon layer on the lower surface of first grid.Array base palte of the invention can realize shading using first grid, such that it is able to omit light shield, simplify manufacturing process, improve production efficiency.
Description
Technical field
The invention belongs to LCD Technology field, especially a kind of array base palte and including its liquid crystal panel and bag
Include its liquid crystal display.
Background technology
In LCD Technology field, the thin film transistor (TFT) of array base palte is broadly divided into low-temperature polysilicon film crystal
Pipe and amorphous silicon film transistor, because the superior performance of low-temperature polysilicon film transistor is in amorphous silicon film transistor, make
Must gradually be instead of using the array base palte of polycrystalline SiTFT and use the array base palte of amorphous silicon film transistor.
However, because the low-temperature polycrystalline silicon layer (i.e. semiconductor active layer) of low-temperature polysilicon film transistor is in backlight
Photoelectric current can be produced under illumination, the display effect of liquid crystal display is disturbed, it is therefore desirable to set in the lower section of low-temperature polycrystalline silicon layer
Light-blocking structure, for example, be capable of the light shield of shading.But, because existing low-temperature polysilicon film transistor is required for light shield, by
This can make the manufacturing process become complicated, influence production efficiency.
The content of the invention
In order to solve the above problems, it is an object of the invention to provide a kind of array base palte and the liquid crystal including the array base palte
Panel and the liquid crystal display including the array base palte, the wherein array base palte realize shading using grid, such that it is able to
Light shield is omitted, simplifies manufacturing process, improve production efficiency.
According to the first aspect of the invention, there is provided a kind of array base palte, it includes multiple pixel cells.Each pixel list
Thin film transistor (TFT) is provided with unit.Thin film transistor (TFT) includes stacking gradually from bottom to up glass substrate, the first insulating barrier, second exhausted
Edge layer and the 3rd insulating barrier.The first low temperature polycrystalline silicon that can be covered by the second insulating barrier is provided with the upper surface of the first insulating barrier
Layer.The two ends of the first low-temperature polycrystalline silicon layer respectively with the first source electrode being formed between the 3rd insulating barrier and the second insulating barrier and
One drain electrode is connected.The first grid that can be covered by the first insulating barrier is provided with the upper surface of glass substrate, while first grid
Lower surface can cover orthographic projection of first low-temperature polycrystalline silicon layer on the lower surface of first grid.
In one embodiment, the area of the lower surface of first grid is the area of the lower surface of the first low-temperature polycrystalline silicon layer
1-10 times.
In one embodiment, first grid, the first source electrode and the first drain electrode is made by metal material.
In one embodiment, array base palte also includes public electrode and pixel electrode, public electrode and the 3rd insulating barrier
Separated by the 4th insulating barrier, pixel electrode and public electrode are separated by the 5th insulating barrier, public electrode and first drain electrode phase
Connect, and pixel electrode is connected with the first source electrode.
In one embodiment, thin film transistor (TFT) is nmos pass transistor or PMOS transistor.
In one embodiment, thin film transistor (TFT) is CMOS transistor.
In one embodiment, CMOS transistor includes being arranged on the upper surface of the first insulating barrier and by the second insulating barrier
Second low-temperature polycrystalline silicon layer of covering, the two ends of the second low-temperature polycrystalline silicon layer respectively be formed in the 3rd insulating barrier and insulated with second
The second source electrode and the second drain electrode between layer are connected, and the second source electrode and the first drain electrode are connected, and the second drain electrode and the first source electrode phase
Even, the second grid that can be covered by the first insulating barrier is provided with the upper surface of glass substrate, while the lower surface of second grid
Orthographic projection of second low-temperature polycrystalline silicon layer on the lower surface of second grid can be covered.
According to the second aspect of the invention, there is provided a kind of including array base palte described according to the first aspect of the invention
Liquid crystal panel.
According to the third aspect of the invention we, there is provided a kind of including array base palte described according to the first aspect of the invention
Liquid crystal display.
Array base palte of the invention is arranged on first grid the lower section of the first low-temperature polycrystalline silicon layer, for blocking backlight
The low-temperature polycrystalline silicon layer of light irradiation first in source, it is possible thereby to effectively prevent from producing photoelectric current in low-temperature polycrystalline silicon layer, so that can
To avoid interference the display effect of liquid crystal display.Can omit in this way light shield and light shield insulating barrier, from
And manufacturing process can be simplified, improve production efficiency.
When the thin film transistor (TFT) of array base palte is CMOS transistor, first grid and second grid can respectively block backlight
The low-temperature polycrystalline silicon layer of light irradiation first and second in source, it is possible thereby to effectively prevent from being produced in the first and second low-temperature polycrystalline silicon layers
Generated photo-current, such that it is able to avoid interference the display effect of liquid crystal display.Light shield can be omitted in this way, simplify system
Make technique, improve production efficiency.
In addition, the simple structure of array base palte of the invention, with low cost, production efficiency is high, popularization convenient to carry out
Using.
Brief description of the drawings
The invention will be described in more detail below based on embodiments and refering to the accompanying drawings.Wherein：
Fig. 1 schematically shows array base palte of the invention；And
Fig. 2 schematically shows the pixel cell of array base palte of the invention.
Identical part uses identical reference in the accompanying drawings.Accompanying drawing is not drawn according to actual ratio.
Specific embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Fig. 1 shows array base palte of the invention 10.The array base palte 10 includes the pixel cell 2 of multiple matrix form distributions
(i.e. sub-pixel unit).Each pixel cell 2 is by thin film transistor (TFT) 3, pixel electrode 5, public electrode 6 (see Fig. 2) and storage
Capacitor (not shown) is constituted.The thin film transistor (TFT) 3 is low temperature polycrystalline silicon (Low Temperature Poly-Silicon, letter
Claim LTPS) thin film transistor (TFT), compared to traditional non-crystalline silicon (α-Si), LTPS has carrier mobility higher, therefore real
Resolution ratio and lower power consumption now higher, and the integrated level of device is also higher on array base palte.
As shown in Fig. 2 the thin film transistor (TFT) 3 includes stacking gradually glass substrate 7, the first insulating barrier 31, the from bottom to up
Two insulating barriers 32 and the 3rd insulating barrier 33.Public electrode 6 is arranged on the upper surface of the 3rd insulating barrier 33 by the 4th insulating barrier 34
On, and pixel electrode 5 is arranged on the upper surface of public electrode 6 by the 5th insulating barrier 35.In the upper table of the first insulating barrier 31
Face is provided with the first low-temperature polycrystalline silicon layer 304 that can be covered by the second insulating barrier 32.First low-temperature polycrystalline silicon layer 304 (is partly led
Body active layer) two ends respectively with the first source electrode 301 and first being formed between the 3rd insulating barrier 33 and the second insulating barrier 34
Drain electrode 302 is connected.Pixel electrode 5 can be connected with the first source electrode 301, and the first drain electrode 302 can be with data electrode (i.e. signal electrode
It is connected), to control pixel electrode 5 with the electric field produced by public electrode 6.Wherein, each insulating barrier belongs to this area skill
Known to art personnel, no further details to be given herein.
According to the present invention, the first grid that can be covered by the first insulating barrier 31 is provided with the upper surface of glass substrate 7
303.First grid 303 is connected for connecting gate electrode line, to control leading between the first source electrode 301 and the first drain electrode 302
Logical state.The lower surface of the first grid 303 can cover lower surface of first low-temperature polycrystalline silicon layer 304 in first grid 303
On orthographic projection.In this way, can effectively stopping the illumination of the backlight of liquid crystal display, to be mapped to the first low temperature more
On crystal silicon layer 304, thus it can be prevented that in the first low-temperature polycrystalline silicon layer 304 and produce photoelectric current, such that it is able to avoid interference liquid crystal
The display effect of display.Compared with prior art, array base palte of the invention 10 can omit light shield and light shield it is exhausted
Edge layer, such that it is able to simplify manufacturing process, improve production efficiency.Wherein, first grid 303, the first source electrode 301 and the first drain electrode
302 are made by metal material, to realize conducting function.
Under normal circumstances, first grid 303 is obtained by etching mode, and the first grid 303 that etching mode is formed is usual
All it is that lower surface area is more than upper surface area, therefore only needs to ensure that the lower surface of first grid 303 is more than or equal to first
Orthographic projection of the low-temperature polycrystalline silicon layer 304 on the lower surface of first grid 303, just can stop the light of the backlight of liquid crystal display
It is irradiated on the first low-temperature polycrystalline silicon layer 304.But, the light transmission part of pixel electrode 5 can not be blocked due to first grid 303
(belonging to known to skilled person), therefore first grid 303 has to the overall size less than thin film transistor (TFT) 3.Due to
The overall sizableness of thin film transistor (TFT) 3 is in the area of the lower surface of 10 times of the first low-temperature polycrystalline silicon layer 304.Therefore the first grid
The area of the lower surface of pole 303 should be 1-10 times of the area of the lower surface of the first low-temperature polycrystalline silicon layer 304.
Thin film transistor (TFT) 3 can be nmos pass transistor or PMOS transistor, can be again CMOS transistor.But, film is brilliant
Body pipe 3 is preferably CMOS transistor.CMOS transistor power consumption and antijamming capability are better than NMOS or PMOS transistor.NMOS English
Full name is N-Metal-Oxide-Semiconductor, and it is N-type Metal-oxide-semicondutor to look like, and possesses this structure
Transistor be referred to as nmos pass transistor, it belongs to well known to those skilled in the art.PMOS English full name are P-Metal-
Oxide-Semiconductor, it is p-type Metal-oxide-semicondutor to look like, and the transistor for possessing this structure is referred to as
PMOS transistor, it falls within well known to those skilled in the art.CMOS(Complementary Metal Oxide
Semiconductor, complementary metal oxide semiconductors (CMOS)) transistor is while possessing NMOS transistor structure and PMOS transistor
The transistor of structure.
In one embodiment, CMOS transistor includes being arranged on the upper surface of the first insulating barrier 31 and by the second insulation
Second low-temperature polycrystalline silicon layer 314 of the covering of layer 32.The two ends of the second low-temperature polycrystalline silicon layer 314 respectively be formed in the 3rd insulating barrier
The second source electrode 311 and the second drain electrode 312 between 33 and the second insulating barrier 32 are connected.Wherein, the second source electrode 311 and the first drain electrode
302 are connected, and the second drain electrode 312 is connected with the first source electrode 301.Being provided with the upper surface of glass substrate 7 can be by the first insulation
The second grids 313 of the covering of layer 31, while the lower surface of second grid 313 can cover the second low-temperature polycrystalline silicon layer 314 the
Orthographic projection on the lower surface of two grids 313.In this way, the light of the backlight of liquid crystal display can effectively be stopped
It is irradiated on the second low-temperature polycrystalline silicon layer 314, thus it can be prevented that in the second low-temperature polycrystalline silicon layer 314 and produce photoelectric current, so that
The display effect of liquid crystal display can be avoided interference.Wherein, second grid 313, the second source electrode 311 and the second drain electrode 312 are equal
It is made up of metal material, to realize conducting function.First and second low-temperature polycrystalline silicon layers 304 and 314 can be respectively N-type gold
Category-Oxidc-Semiconductor and p-type Metal-oxide-semicondutor, otherwise the first and second low-temperature polycrystalline silicon layers 304 and 314
P-type Metal-oxide-semicondutor and N-type Metal-oxide-semicondutor can be respectively.
Situation with first grid 303 is identical, and the area of the lower surface of second grid 313 should also be as being 1-10 times second low
The area of the lower surface of warm polysilicon layer 314.
In summary, array base palte of the invention 10 can be using grid (including first grid 303 and second grid
313) effectively stop that the illumination of the backlight of liquid crystal display is mapped to low-temperature polycrystalline silicon layer (including the first low-temperature polycrystalline silicon layer
304 and second low-temperature polycrystalline silicon layer 314) on, it is possible thereby to effectively prevent from producing photoelectric current in low-temperature polycrystalline silicon layer, so that can
To avoid interference the display effect of liquid crystal display.Compared with prior art, array base palte of the invention 10 eliminates light shield layer
(Light shielding layer), can reduce by one light shield；Such that it is able to simplify manufacturing process, improve production efficiency.
In addition, present invention also offers a kind of liquid crystal panel, that includes above-mentioned array base palte 10.Additionally, the present invention is also
There is provided a liquid crystal display, it also includes above-mentioned array base palte 10.
Although by reference to preferred embodiment, invention has been described, is not departing from the situation of the scope of the present invention
Under, various improvement can be carried out to it and part therein can be replaced with equivalent.Especially, as long as in the absence of structure punching
Prominent, the every technical characteristic being previously mentioned in each embodiment can combine in any way.The invention is not limited in text
Disclosed in specific embodiment, but all technical schemes including falling within the scope of the appended claims.
Claims (6)
1. a kind of array base palte, including multiple pixel cells, is provided with thin film transistor (TFT) in each described pixel cell, described thin
Film transistor includes stacking gradually glass substrate, the first insulating barrier, the second insulating barrier and the 3rd insulating barrier from bottom to up, described
The upper surface of the first insulating barrier is provided with the first low-temperature polycrystalline silicon layer that can be covered by second insulating barrier, first low temperature
The two ends of polysilicon layer drain with the first source electrode being formed between the 3rd insulating barrier and the second insulating barrier and first respectively
It is connected, the first grid that can be covered by first insulating barrier, the first grid is provided with the upper surface of the glass substrate
The lower surface of pole can cover orthographic projection of first low-temperature polycrystalline silicon layer on the lower surface of the first grid,
The thin film transistor (TFT) is CMOS transistor,
The CMOS transistor includes being arranged on what is covered on the upper surface of first insulating barrier and by second insulating barrier
Second low-temperature polycrystalline silicon layer, the two ends of second low-temperature polycrystalline silicon layer are respectively with to be formed in the 3rd insulating barrier exhausted with second
The second source electrode and the second drain electrode between edge layer are connected, and second source electrode is connected with the described first drain electrode, and second leakage
Pole is connected with first source electrode, and second for being covered by first insulating barrier is provided with the upper surface of the glass substrate
Grid, the lower surface of the second grid can cover second low-temperature polycrystalline silicon layer on the lower surface of the second grid
Orthographic projection.
2. array base palte according to claim 1, it is characterised in that the area of the lower surface of the first grid is described
1-10 times of the area of the lower surface of the first low-temperature polycrystalline silicon layer.
3. array base palte according to claim 2, it is characterised in that the first grid, the first source electrode and the first drain electrode
It is made by metal material.
4. array base palte according to claim 3, it is characterised in that also including public electrode and pixel electrode, the public affairs
Common electrode and the 3rd insulating barrier are separated by the 4th insulating barrier, and the pixel electrode and public electrode pass through the 5th insulating barrier
Separate, data electrode is connected with the described first drain electrode, and the pixel electrode is connected with first source electrode.
5. a kind of liquid crystal panel of the array base palte including any one of claim 1 to 4.
6. a kind of liquid crystal display of the array base palte including any one of claim 1 to 4.
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| CN201410856154.0A CN104460165B (en) | 2014-12-31 | 2014-12-31 | A kind of liquid crystal display and liquid crystal panel and array base palte |
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| CN201410856154.0A CN104460165B (en) | 2014-12-31 | 2014-12-31 | A kind of liquid crystal display and liquid crystal panel and array base palte |
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| CN104460165B true CN104460165B (en) | 2017-06-16 |
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Families Citing this family (3)
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| CN104867944B (en) * | 2015-05-08 | 2018-07-10 | 深圳市华星光电技术有限公司 | Array base-plate structure and preparation method thereof |
| CN107845342A (en) * | 2017-11-22 | 2018-03-27 | 殷周平 | A kind of array base palte and display device |
| CN109003943B (en) * | 2018-06-27 | 2021-01-29 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
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| US6038004A (en) * | 1996-04-30 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Active matrix liquid crystal display for projection system |
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