CN100583417C - Making method for CMOS thin film transistor - Google Patents
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- CN100583417C CN100583417C CN200710169933A CN200710169933A CN100583417C CN 100583417 C CN100583417 C CN 100583417C CN 200710169933 A CN200710169933 A CN 200710169933A CN 200710169933 A CN200710169933 A CN 200710169933A CN 100583417 C CN100583417 C CN 100583417C
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Abstract
This invention relates to a manufacturing method for semiconductor elements including: carrying out first micro-image etching to form a first photoetching substratum with at least two diferent thicknesses to define a semiconductor layer of PMOS and NMOS elements by the photoetching substratum and then defining source/drain of the PMOS element by the ashed first substratum and forming a second photoetching substratum by second micro-image etching to define the grid of the PMOS and NMOS elements from the second substratum then to define a LDD of the NMOS element from the ashed second substratum.
Description
Technical field
The present invention refers to a kind of manufacture method that is applicable to the CMOS thin film transistor (CMOS TFT) of LCD especially about a kind of manufacture method of LCD.
Background technology
Along with the arriving of digital Age and the rise of flat-panel screens, low temperature compound crystal silicon technology has become the synonym of high image quality display.Under product demands such as light, thin, low power consumption, the low temperature compound crystal silicon display product that possesses characteristics such as high-effect, high parsing gets most of the attention, and application comprises portable information product, digital camera, digital camera, mobile computer, mobile phone and the high large-scale video appliance or the like of resolving.
Because low temperature compound crystal silicon thin-film transistor can overcome the problem of mobility, and complementary (Complementary) is provided circuit engineering, also has absolute advantage on element downsizing, panel aperture opening ratio, image quality and resolution.Therefore, active liquid crystal indicator is gradually towards adopting CMOS thin film transistor (CMOS TFT), as the switch element of peripheral circuit and pixel.Yet; because in the CMOS thin film transistor; N type metal oxide semiconductor field-effect transistor can be because hot carrier effect; and the problem of grid leakage current is arranged when off status (off state); so N type metal oxide semiconductor field-effect transistor can design light dope grid (lightlydoped drain usually; LDD) zone is used for lowering grid leakage current.
Figure 1A to Fig. 1 F is the existing manufacture method schematic diagram that adopts the thin-film transistor array base-plate of CMOS thin film transistor.With design the CMOS thin film transistor of lightly doped drain being arranged is example, and the modal manufacturing technology steps of this thin-film transistor array base-plate needs the manufacturing process of eight road light shields.
At first, see also Figure 1A, one substrate 100 is provided, this substrate 100 has 210 and one P-type mos (PMOS) district 220, a N type metal oxide semiconductor (NMOS) district, wherein this nmos area 210 comprises first doped region 211, light doping section 212, first grid polar region 213 and capacitive region 214, and this PMOS district 220 comprises second doped region 221 and second grid district 222.
Continue to consult Figure 1A, on this substrate, form a resilient coating 110.Then, on this resilient coating 110, form a low temperature compound crystal silicon layer (figure does not show), carry out a lithography again with this low temperature compound crystal silicon layer of patterning (figure does not show), and form first semiconductor layer 121 and second semiconductor layer 122, wherein this first semiconductor layer 121 is arranged in this nmos area 210, and this second semiconductor layer 122 is arranged in this PMOS district 220.Then, on this substrate 100, form a dielectric layer 130 (for example silicon nitride), this dielectric layer 130 is covered on this first semiconductor layer 121, this second semiconductor layer 122 and this substrate 100 of part.
Then, see also Figure 1B, develop via single exposure, first photoresist layer 141 that forms a patterning exposes first doped region 211 of this nmos area 210 on this dielectric layer 130.Then, serve as the cover curtain with this first photoresist layer 141, carry out the heavy doping ion of N type ion (for example phosphonium ion or arsenic ion) and implant 910 (n
+-ions implantation), form the source/drain 121a of NMOS element by this.
Secondly, see also Fig. 1 C, remove this first photoresist layer 141.Then, carry out lithography one time, the metal level 150 that forms a patterning is on this dielectric layer 130, and this metal level 150 is covered in this first grid polar region 213, this capacitive region 214 and this second grid district 222.Then, serve as the cover curtain with this metal level 150, carry out the light dope of N type ion and implant (n--ions implantation) 920, form lightly doped drain (LDD) 121b by this.
Secondly, see also Fig. 1 D, carry out single exposure and develop, second photoresist layer 142 that forms a patterning is covered on this metal level 150 and this dielectric layer 130 of part, and second doped region 221 of this PMOS is exposed.Then, serve as the cover curtain with this second photoresist layer 142 and this metal level 150, carry out the heavy doping ion of P type ion (for example boron ion) and implant (P
+-ions implantation) 930, form the source/drain 122a of PMOS element by this.At last, remove this second photoresist layer 142 again, promptly finish the drive circuit that comprises CMOS thin film transistor and storage capacitors.
Secondly, see also Fig. 1 E, on this substrate 100, form a protective layer 160.Then, utilize lithography to define to run through the through hole 160a of this protective layer 160 and this dielectric layer 130, with the part source/drain 121a that appears the N type metal oxide semiconductor and the part source/drain 122a of P-type mos.Then, plated metal on this protective layer 160 with this through hole 160a in, carry out a lithography again and define source/drain polar conductor 170.In the present embodiment, this source/drain polar conductor 170 fills up this through hole 160a and is covered in the part surface of this protective layer 160.
At last, shown in Fig. 1 F, on this protective layer 160, form a flatness layer 180, utilize a lithography to define the through hole 180a that runs through this flatness layer 180 again.Then, deposit a transparent electrode layer 190, utilize once little shadow manufacturing process to make its patterning again, promptly finish the thin-film transistor array base-plate of a liquid crystal indicator.
Yet, because manufacturing process is tediously long and complicated, therefore cost costliness not only, and cause the manufacturing process defective easily, therefore how to reduce light shield road number and become the important topic that thin-film transistor array base-plate is made development.
This so, need a kind of manufacture method of CMOS thin film transistor at present badly, the manufacturing technology steps that can simplify lithography improves production capacity and the double effects that reduces manufacturing cost to reduce the manufacturing process degree of difficulty to reach.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of semiconductor element, make the required light shield road number of semiconductor element be reduced to twice, simplify manufacturing technology steps, the raising production capacity of lithography by this and reduce manufacturing cost.
The invention provides a kind of manufacture method of semiconductor element, comprise the following steps: that (A) provides a substrate, this substrate has a N type metal oxide semiconductor (NMOS) district, distinguishes with a P-type mos (PMOS), wherein this nmos area comprises one first doped region, a light doping section and a first grid polar region, and this PMOS district comprises one second doped region and a second grid district; (B) comprehensive formation semi-conductor layer on this substrate; (C) form one first photoresist layer on this semiconductor layer in this nmos area and this PMOS district, wherein the thickness of this first photoresist layer in this second grid district in this nmos area and this PMOS district is greater than the thickness of all the other these first photoresist layers; (D) remove this semiconductor layer that is not covered by this first photoresist layer; (E) reduce the thickness of this first photoresist layer, with this semiconductor layer on this second doped region that exposes this PMOS district; (F) serve as cover curtain with remaining this first photoresist layer, the heavy doping ion of carrying out P type ion is implanted and is formed one first source/drain; (G) remove remaining this first photoresist layer; (H) comprehensive formation one dielectric layer and a metal level on this substrate and this semiconductor layer in regular turn; (I) in forming one second photoresist layer on this first grid polar region of this nmos area and this light doping section with in this second grid district in this PMOS district; (J) remove this metal level that is not covered by this second photoresist layer; (K) serve as cover curtain with this second photoresist layer, the heavy doping ion of carrying out N type ion is implanted and is formed one second source/drain; (L) dwindle the width of this second photoresist layer, this metal level on this light doping section of this nmos area is come out; (M) remove this metal level that is not covered by this second photoresist layer; (N) serve as the cover curtain with remaining this second photoresist layer, carry out the light dope ion of N type ion and implant; And (O) remove this second photoresist layer, and form a first grid and a second grid.
Hold, the manufacture method of semiconductor element of the present invention can comprise the following steps: again
Form a protective layer on this dielectric layer, make it cover this first grid and this second grid;
Form a plurality of first through holes in this protective layer and this dielectric layer, described these first through holes expose this first source/drain of part and this second source/drain; And
Form one first source/drain polar conductor and one second source/drain polar conductor in described these first through holes, this first source/drain polar conductor and this second source/drain polar conductor are electrically connected to pairing this first source/drain and this second source/drain respectively.
Hold, the manufacture method of semiconductor element of the present invention also can comprise the following steps: again
Form a flatness layer on this protective layer, make it cover this first source/drain polar conductor and this second source/drain polar conductor;
Form one second through hole in this flatness layer, this second through hole exposes this second source/drain polar conductor; And
Form a transparent electrode layer on this flatness layer, wherein this transparent electrode layer is connected to this second source/drain polar conductor via this second through hole.
In the manufacture method of semiconductor element of the present invention, the material of this substrate does not limit, and is preferably a glass substrate or a quartz base plate.
In the manufacture method of semiconductor element of the present invention, alternative includes a resilient coating between this substrate and this semiconductor layer, and contains N type ion and P type ion in this resilient coating.This resilient coating diffuses in this semiconductor layer in order to the metal ion that intercepts in the glass substrate, reduces and plays the part of defect center formation and leakage current generating.Therefore, the material of this resilient coating does not limit, and is preferably individual layer silicon dioxide (SiOx) or double-deck silicon dioxide/silicon nitride (SiO
x/ SiN
x).
In the manufacture method of semiconductor element of the present invention, this semiconductor layer is a compound crystal silicon (Polysilicon) layer.The formation method of this compound crystal silicon layer does not limit in this step (B), can any existing method form compound crystal silicon; One better embodiment of this step (B) is: with chemical vapour deposition (CVD) (Chemicalvapor deposition), form an amorphous silicon (amorphous silicon) layer in this substrate surface; And, make this amorphous silicon layer become a compound crystal silicon layer with laser tempering (Laser annealing).
In the manufacture method of semiconductor element of the present invention, this first photoresist layer forms with half mode (Half-tone) light shield or grey mode light shield (Gray-tone) exposure imaging in this step (C), uses this first photoresist layer and has two or more different-thickness.
In the manufacture method of semiconductor element of the present invention, the material of this dielectric layer does not limit, and is preferably silica (SiOx) layer, silicon nitride layer (SiNx) or its combination.
In the manufacture method of semiconductor element of the present invention, the material of this metal level does not limit, the preferable group that is made up of aluminium, tungsten, chromium, molybdenum, titanium and combination thereof that is selected from.
In the manufacture method of semiconductor element of the present invention, the method that this step (E) reduces this first photoresist bed thickness does not limit, the preferable thickness that utilizes ashing (Ash) to reduce this first photoresist layer.
In the manufacture method of semiconductor element of the present invention, the heavy doping ion of P type ion implantation manufacturing process is the boron implant ion in this step (F).
In the manufacture method of semiconductor element of the present invention, the formation method of this second photoresist layer does not limit in this step (I), preferablely forms with an exposure imaging manufacturing process.
In the manufacture method of semiconductor element of the present invention, this second photoresist layer and this second doped region can be overlapped or not overlapping in this step (I), be preferably this second photoresist layer and this second doped region is overlapped, be beneficial to follow-up making overlapping (Overlap) type PMOS element.
Therefore, in the manufacture method of semiconductor element of the present invention, in step (J), after this metal level that is covered by this second photoresist layer is not removed, remaining this metal level and this second doped region can be overlapped or are not overlapping, be preferably remaining this metal level and this second doped region is overlapped, form one overlapping (Overlap) type PMOS element, to improve the carrier mobility and the output characteristic of PMOS element.
In the manufacture method of semiconductor element of the present invention, the heavy doping ion of N type ion implantation manufacturing process is to implant arsenic ion or phosphonium ion in this step (K).
In the manufacture method of semiconductor element of the present invention, the method that this step (L) is dwindled this second photoresist layer width does not limit, the preferable width that dwindles this second photoresist layer with ashing.
In the manufacture method of semiconductor element of the present invention, the light dope ion of N type ion implantation manufacturing process is to implant arsenic ion or phosphonium ion in this step (N).
The formed NMOS element of the manufacture method of semiconductor element of the present invention can be positioned at the pixel array region of this substrate, is used as the switch element of the pixel cell of a liquid crystal indicator.
Formed PMOS element of the manufacture method of semiconductor element of the present invention and NMOS element can the periphery circuit region of position one liquid crystal indicator in, be used as the logic element of the peripheral circuit of this liquid crystal indicator.
Description of drawings
Figure 1A to Fig. 1 F is the existing manufacture method generalized section that adopts the thin-film transistor array base-plate of CMOS thin film transistor;
Fig. 2 A to Fig. 2 I illustrates the manufacture method of an embodiment of a kind of semiconductor element of the present invention.
Drawing reference numeral;
10 NMOS elements
20 PMOS elements
30 storage capacitors
100,300 substrates
110,310 resilient coatings
121,321 first semiconductor layers
The source/drain of 121a, 321a NMOS element
121b, 321b lightly doped drain
122,322 second semiconductor layers
The source/drain of 122a, 322a PMOS element
130,330 dielectric layers
141,341 first photoresist layers
142,342 second photoresist layers
150,350 metal levels
160,360 protective layers
160a, 180a, 360a, 380a through hole
170,370 source/drain polar conductors
180,380 flatness layers
190,390 transparent electrode layers
210,510 N type metal oxide semiconductors (NMOS) district
211,511 first doped regions
212,512 light doping sections
213,513 first grid polar regions
214,530 capacitive region
220,520 P-type mos (PMOS) district
221,521 second doped regions
222,522 second grid districts
320 compound crystal silicon layers
323 the 3rd semiconductor layers
351 second grids
352 first grids
371 second source/drain polar conductors
372 first source/drain polar conductors
810, the heavy doping ion of 910 N type ions is implanted
820, the light dope ion of 920 N type ions is implanted
830, the heavy doping ion of 930 P type ions is implanted
Embodiment
Fig. 2 A to Fig. 2 H illustrates the manufacture method of an embodiment of a kind of semiconductor element of the present invention.Present embodiment is the manufacture method schematic diagram of the thin-film transistor array base-plate of employing CMOS thin film transistor.In the thin-film transistor array base-plate that present embodiment is made, the making of CMOS thin film transistor and storage capacitors only needs to use the twice light shield, and design has the NMOS element of lightly doped drain (LDD) type and the PMOS element of overlapping (Overlap) type, with the usefulness of effective lifting CMOS thin film transistor.
At first, see also Fig. 2 A, one substrate 300 is provided, this substrate 300 has a N type metal oxide semiconductor (NMOS) district 510, one P-type mos (PMOS) district, 520 and one capacitive region 530, wherein this nmos area 510 comprises one first doped region 511, a light doping section 512 and a first grid polar region 513, and this PMOS district 520 comprises one second doped region 521 and a second grid district 522.The substrate 300 that present embodiment adopts is a glass substrate.
Continue to consult Fig. 2 A, deposition of silica (SiO on this substrate
2) as resilient coating 310.Then, on this resilient coating 310, form an amorphous silicon (amorphous silicon) layer (not shown) with chemical vapour deposition (CVD) (Chemical vapor deposition); Make this amorphous silicon layer become a compound crystal silicon layer 320 with laser tempering (Laser annealing) again.Then, on this compound crystal silicon layer 320, form a photoresist layer (figure does not show), this photoresist layer (figure does not show) is carried out a halftone exposure thereupon and develop, form first photoresist layer 341 with two or more different-thickness.In the present embodiment, this first photoresist layer 341 is positioned on this nmos area 510, this PMOS district 520 and this capacitive region 530, and first photoresist layer, 341 thickness in the second grid district 522 in this nmos area 510 and this PMOS district 520 are greater than first photoresist layer, 341 thickness on second doped region 521 in this capacitive region 530 and this PMOS district 520.In addition, the periphery of this first photoresist layer 341 preferably slightly greater than this nmos area 510, this PMOS district 520 and this capacitive region 530, takes place with the situation of avoiding passage to mix.
Secondly, see also Fig. 2 B, with this first photoresist layer 341 is the cover curtain, utilize to do or wet etching is removed part compound crystal silicon layer 320, and form first semiconductor layer 321 that is positioned on this nmos area 510, be positioned at second semiconductor layer 322 in this PMOS district 520 and be positioned at the 3rd semiconductor layer 323 on this capacitive region 530.In the present embodiment, this compound crystal silicon layer 320 is by over etching, to meet this nmos area 510, this PMOS district 520 and this capacitive region 530.
Secondly, see also Fig. 2 C, utilize ashing (Ash) to reduce the thickness of this first photoresist layer 341, to expose the 3rd semiconductor layer 323 and to be positioned at second semiconductor layer 322 on second doped region 521 in this PMOS district 520.
Secondly, seeing also Fig. 2 D, serves as the cover curtain with remaining first photoresist layer 341, carries out the heavy doping ion of P type ion (boron ion) and implants 830.By this, in this second semiconductor layer 322, form the source/drain 322a of PMOS element.Need not Zhu Yi be, the source/drain 322a of PMOS element implants with the light dope ion of N type ion in the heavy doping ion implantation 810 of follow-up N type ion and can expose out in 820 o'clock, so the concentration of P type ion must be far above the concentration of follow-up N type ion, to avoid reversing.
Secondly, consult Fig. 2 E, remove remaining first photoresist layer 341.Then, form one deck silicon nitride (SiNx) or silica (SiO
x) or both combination be covered on this resilient coating 310 of part, this first semiconductor layer 321, this second semiconductor layer 322 and the 3rd semiconductor layer 323 as dielectric layer 330.Then, in metal level 350 of formation one patterning on this first grid polar region 513 of this nmos area 510 and this light doping section 512, in this second grid district 522 in this PMOS district 520 and on this capacitive region 530 of part and second photoresist layer 342 of a patterning.In the present embodiment, this second photoresist layer 342 forms via the single exposure development; This metal level 350 serves as the cover curtain with this second photoresist layer 342, removes it via etching and is not formed by the part that this second photoresist layer 342 covers.In addition, overlapping in order to make (Overlap) type PMOS element, the periphery of this of present embodiment second photoresist layer 342 and this metal level 350 can be slightly larger than this second grid district 522 in this PMOS district 520, just overlaps with this second doped region 521.
Continue to consult Fig. 2 E.Subsequently, serve as the cover curtain with this second photoresist layer 342 and this metal level 350, carry out the heavy doping ion of N type ion (arsenic ion) and implant 810.By this, in this first semiconductor layer 321, form the source/drain 321a of NMOS element.Here need special remind be because the source/drain 322a of PMOS element exposes out at this moment, so note in the implant concentration and the degree of depth of control N type ion.In addition, owing to this resilient coating also exposes out 310 this moments, so can contain N type ion and P type ion in this resilient coating 310 simultaneously.
Secondly, consult Fig. 2 F, utilize ashing (Ash) to dwindle the width of this second photoresist layer 342, to expose this metal level 350 on this light doping section 512 that is positioned at this nmos area 510; Second photoresist layer 342 with this reduced width is the cover curtain again, and the metal level 350 that comes out is removed.Then, serve as the cover curtain with second photoresist layer 342 of reduced width and metal level 350, carry out the light dope ion of N type ion (phosphonium ion) and implant 820.By this, in this first semiconductor layer 321, form lightly doped drain (LDD) 321b.Same, because the source/drain 322a of PMOS element exposes out at this moment, so also note the implant concentration and the degree of depth of control N type ion here.
Secondly, consult Fig. 2 G, remove this second photoresist layer 342 with formation first grid 352 and second grid 351, thereby form CMOS thin film transistor and the storage capacitors 30 that comprises NMOS element 10 and PMOS element 20.In the present embodiment, this NMOS element 10 of part is arranged in the viewing area of liquid crystal indicator, be used as the switch element of pixel cell, this PMOS element 20 of part and this NMOS element 10 are provided with the peripheral circuit of liquid crystal indicator, are used as the logic element of peripheral circuit.
Secondly, see also Fig. 2 H, on this substrate 300, form a protective layer 360.Then, utilize a lithography to define the through hole 360a that runs through this protective layer 360 and this dielectric layer 330, with the part source/drain 321a that appears the NMOS element, the part source/drain 322a and part the 3rd semiconductor layer 323 of PMOS element.Then, plated metal on this protective layer 360 with this through hole 360a in, carry out a lithography again and define the first source/drain polar conductor 372 and the second source/drain polar conductor 371.In the present embodiment, this first source/drain polar conductor 372 and this second source/drain polar conductor 371 part surface that fills up this through hole 360a and be covered in this protective layer 360.
At last, shown in Fig. 2 I, on this protective layer 360, form a flatness layer 380, utilize a lithography to define the through hole 380a that runs through this flatness layer 380 again.Then, deposit a transparent electrode layer 390, carry out a lithography again and make its patterning, and form the thin-film transistor array base-plate of a liquid crystal indicator.
By present embodiment as seen, present embodiment is made CMOS thin film transistor and is only needed the twice light shield, make thin-film transistor array base-plate and then need six road light shields, therefore, the manufacturing technology steps that can simplify lithography improves production capacity and the double effects that reduces manufacturing cost to reduce the manufacturing process degree of difficulty to reach.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that the claim scope is described certainly, but not only limits to the foregoing description.
Claims (17)
1. the manufacture method of a semiconductor element, described method comprises the following steps:
(A) provide a substrate, described substrate have a N type metal oxide semiconductor nmos area, with a P-type mos PMOS district, wherein said nmos area comprises one first doped region, a light doping section and a first grid polar region, and described PMOS district comprises one second doped region and a second grid district;
(B) comprehensive formation semi-conductor layer on described substrate;
(C) form one first photoresist layer on the described semiconductor layer in described nmos area and the described PMOS district, wherein the thickness of described first photoresist layer in the described second grid district in described nmos area and described PMOS district is greater than the thickness of all the other described first photoresist layers;
(D) remove the described semiconductor layer that is not covered by described first photoresist layer;
(E) thickness of described first photoresist layer of minimizing is with the described semiconductor layer on described second doped region that exposes described PMOS district;
(F) serve as cover curtain with remaining described first photoresist layer, the heavy doping ion of carrying out P type ion is implanted and is formed one first source/drain;
(G) remove remaining described first photoresist layer;
(H) comprehensive formation one dielectric layer and a metal level on described substrate and described semiconductor layer in regular turn;
(I) in forming one second photoresist layer on the described first grid polar region of described nmos area and the described light doping section with in the described second grid district in described PMOS district;
(J) remove the described metal level that is not covered by described second photoresist layer;
(K) serve as cover curtain with described second photoresist layer, the heavy doping ion of carrying out N type ion is implanted and is formed one second source/drain;
(L) dwindle the width of described second photoresist layer, the described metal level on the described light doping section of described nmos area is come out;
(M) remove the described metal level that is not covered by described second photoresist layer;
(N) serve as the cover curtain with remaining described second photoresist layer, carry out the light dope ion of N type ion and implant; And
(O) remove described second photoresist layer, and form a first grid and a second grid.
2. the manufacture method of semiconductor element as claimed in claim 1, described method more comprises:
Form a protective layer on described dielectric layer, make it cover described first grid and described second grid;
Form a plurality of first through holes in described protective layer and described dielectric layer, described these first through holes expose described first source/drain of part and described second source/drain; And
Form one first source/drain polar conductor and one second source/drain polar conductor in described these first through holes, described first source/drain polar conductor and the described second source/drain polar conductor are electrically connected to pairing described first source/drain and described second source/drain respectively.
3. the manufacture method of semiconductor element as claimed in claim 2, described method more comprises:
Form a flatness layer on described protective layer, make it cover described first source/drain polar conductor and the described second source/drain polar conductor;
Form one second through hole in described flatness layer, described second through hole exposes the described second source/drain polar conductor; And
Form a transparent electrode layer on described flatness layer, wherein said transparent electrode layer is connected to the described second source/drain polar conductor via described second through hole.
4. the manufacture method of semiconductor element as claimed in claim 1 includes a resilient coating between wherein said substrate and the described semiconductor layer in addition, and contains N type ion and P type ion in the described resilient coating.
5. the manufacture method of semiconductor element as claimed in claim 1, wherein said semiconductor layer is a compound crystal silicon layer.
6. form the step of described semiconductor layer in the manufacture method of semiconductor element as claimed in claim 1, wherein said step (B), comprising:
With chemical vapour deposition (CVD), form an amorphous silicon layer in described substrate surface; And
With laser tempering, make described amorphous silicon layer become a compound crystal silicon layer.
7. the manufacture method of semiconductor element as claimed in claim 1, first photoresist layer described in the wherein said step (C) are to develop with halftone exposure to form.
8. the manufacture method of semiconductor element as claimed in claim 1, the material of wherein said dielectric layer is silicon oxide layer, silicon nitride layer or its combination.
9. the manufacture method of semiconductor element as claimed in claim 1, the material of wherein said metal level is selected from the group that is made up of aluminium, tungsten, chromium, molybdenum and combination thereof.
10. the manufacture method of semiconductor element as claimed in claim 1, wherein said step (E) reduces the thickness of described first photoresist layer with ashing.
11. the heavy doping ion of P type ion implantation manufacturing process is the boron implant ion in the manufacture method of semiconductor element as claimed in claim 1, wherein said step (F).
12. the manufacture method of semiconductor element as claimed in claim 1, second photoresist layer described in the wherein said step (I) forms with an exposure imaging manufacturing process.
13. the manufacture method of semiconductor element as claimed in claim 1, second photoresist layer described in the wherein said step (I) and described second doped region are overlapped.
14. the manufacture method of semiconductor element as claimed in claim 1, in the wherein said step (J), after the described metal level that is covered by described second photoresist layer is not removed, remaining described metal level and described second doped region are overlapped, and form an overlapping type PMOS element.
15. the heavy doping ion of N type ion implantation manufacturing process is to implant arsenic ion or phosphonium ion in the manufacture method of semiconductor element as claimed in claim 1, wherein said step (K).
16. the manufacture method of semiconductor element as claimed in claim 1, wherein said step (L) are to dwindle the width of described second photoresist layer with ashing.
17. the light dope ion of N type ion implantation manufacturing process is to implant arsenic ion or phosphonium ion in the manufacture method of semiconductor element as claimed in claim 1, wherein said step (N).
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| CN200710169933A CN100583417C (en) | 2007-11-08 | 2007-11-08 | Making method for CMOS thin film transistor |
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| CN200710169933A CN100583417C (en) | 2007-11-08 | 2007-11-08 | Making method for CMOS thin film transistor |
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| CN103579115B (en) * | 2013-11-11 | 2015-11-25 | 京东方科技集团股份有限公司 | Complementary thin-film transistor and preparation method thereof, array base palte, display unit |
| CN104362127A (en) * | 2014-11-21 | 2015-02-18 | 深圳市华星光电技术有限公司 | Manufacturing method and device for thin film transistor substrate |
| CN104716092B (en) | 2015-04-02 | 2017-11-10 | 京东方科技集团股份有限公司 | The manufacture method and manufacture device of array base palte |
| CN105097699B (en) * | 2015-08-04 | 2018-02-13 | 武汉华星光电技术有限公司 | A kind of display panel preparation method |
| CN108831895B (en) * | 2018-08-28 | 2023-10-13 | 武汉华星光电技术有限公司 | Display panel and manufacturing method thereof |
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