JPH10111521A - Production of liquid crystal display panel and liquid crystal display panel as well as electronic apparatus formed by using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a process for producing a liquid crystal display device capable of confining a substrate size within a prescribed cell gap even if the substrate size increases at the time of formation of TFTs, the liquid crystal display panel as well as electronic apparatus formed by using the same. SOLUTION: A gate oxidized film 42 formed on a polysilicon layer 40 to be formed as the source and drain of the TFT 30 is formed of a thermally oxidized film 42a and a CVD oxidized film 42b. The thermally oxidized film 42a is formed by thermally oxidizing the polysilicon layer 40 at <=1050 deg.C. The film thickness is 0.015 to 0.05μm, more preferably 0.02 to 0.035μm. The CVD oxidized film to be formed thereon is vapor phase grown on at least the thermally oxidized film at <=1050 deg.C and the film thickness thereof is >=0.02μm. The CVD oxidized film may be formed over the entire surface of the first substrate 10 including the thermally oxidized film. The total film thickness of the gate oxidized film 42 is preferably 0.05 to 0.12μm when the polysilicon layer is commonly used as capacitor lines for the holding capacitors of liquid crystals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a liquid crystal display panel using a thin film transistor (TFT) as a switching element, a liquid crystal display panel, and electronic equipment such as a projector using the same.

[0002]

2. Description of the Related Art Liquid crystal display panels of this kind are widely used as light valves for projectors and the like, and there is a strong demand for improvement in manufacturing efficiency. Conventionally, a substrate on which a TFT is formed is a 5-inch silicon substrate, and after each layer is formed thereon, it is cut to form a liquid crystal display substrate of a predetermined size.

In order to increase the throughput of a liquid crystal display substrate, it is necessary to increase the number of liquid crystal substrates obtained from one substrate. The present inventor uses an 8-inch silicon substrate instead of a 5-inch silicon substrate. Considered that.

[0004]

FIG. 20 shows a silicon substrate having a diameter of 8 inches at 1000 ° C., 1050 ° C. and 115 ° C.
The figure shows the amount of warpage of the silicon substrate when each was annealed at 0 ° C. At this time, the silicon substrate was subjected to the arylation while supporting a portion near the peripheral edge of the silicon substrate in the same manner as in the normal heat treatment, so that the amount of warpage shown in FIG. 20 occurred between the center and the peripheral edge.

In the liquid crystal display panel, a first substrate on which scanning signal lines, data signal lines, and TFTs are formed and a second substrate on which a common electrode is formed are stopped at a predetermined cell gap. They are made to face each other and liquid crystal is sealed between them. At this time, the first substrate is obtained by cutting the 8-inch wafer having been subjected to the film formation process into a predetermined size. Here, as described above, if the amount of warpage of the 8-inch wafer is large, it cannot be stopped within a predetermined cell gap at the time of assembling the substrate.

Here, the highest process temperature for forming a TFT is a step of forming a gate oxide film. A conventional gate oxide film is formed by performing a thermal oxidation process, and its thermal oxidation temperature is 1150 ° C. or higher. Therefore, according to FIG. 20, the warpage of the 8-inch wafer is as large as 800 μm, and it cannot be stopped within the predetermined cell gap at all.

A technique of forming the gate oxide film into two layers of a thermal oxide film and a CVD oxide film is disclosed in Japanese Patent Laid-Open No. 60-164362.
JP-A-63-1071, JP-A-63-31647
9, JP-A-2-65274, JP-A-2-1742
No. 30, etc., when the thermal oxidation temperature is high, the same problem as that of a single thermal oxide film still remains.

In addition, a gate oxide film is formed by using a thermal oxide film and CVD.
In the case of using two layers with an oxide film, the step on the surface of the substrate subjected to the rubbing treatment becomes large, and there is a possibility that the liquid crystal cannot be aligned in this part.

Therefore, the object of the present invention is to make T
An object of the present invention is to provide a liquid crystal display panel manufacturing method and a liquid crystal display panel which can be held in a predetermined cell gap even if a substrate size at the time of forming an FT becomes large, and an electronic device using the same.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display panel capable of reducing a step on the surface of a rubbed substrate even if the gate oxide film has two layers of a thermal oxide film and a CVD oxide film. And a liquid crystal display panel and an electronic device using the same.

[0011]

According to a first aspect of the present invention, there is provided a liquid crystal display panel having a liquid crystal sealed between a first substrate on which a semiconductor thin film transistor is formed and a second substrate opposed thereto. Forming a polysilicon layer serving as a source and a drain of the semiconductor thin film transistor on the first substrate; forming a gate oxide film over the polysilicon layer; Forming a gate layer of the semiconductor thin film transistor on a film, forming a first interlayer insulating layer covering the gate oxide film and the gate layer, and forming the polysilicon on the first interlayer insulating layer. Forming a metal wiring layer in contact with a layer, forming a second interlayer insulating layer covering the first interlayer insulating layer and the metal wiring layer, and forming the second interlayer insulating layer. On the layer, and a step of forming a transparent electrode in contact with the polysilicon layer, the step of forming the gate oxide film, the polysilicon layer 10
Thermal oxidation at a temperature of 50 ° C. or less,
Forming a thermal oxide film having a thickness of 5 μm;
A step of vapor-phase growing a silicon oxide film on at least the thermal oxide film at a temperature of 50 ° C. or less to form a CVD film having a thickness of 0.02 μm or more. Panel manufacturing method.

A twelfth aspect of the present invention defines a liquid crystal display panel obtained by the method of the first aspect.

According to the first and twelfth aspects of the present invention, the process temperature of the gate oxide film forming step is 1050 ° C. or less, and as is apparent from FIG. 20, even if a large substrate such as an 8-inch wafer is used. 100 μm substrate warpage
It is possible to hold down below.

Further, since the thickness of the thermal oxide film is 0.015 μm or more, the MO film between the polysilicon layer and the thermal oxide film is
The S interface can be reliably formed. Further, since the upper limit of the thickness of the thermal oxide film is 0.05 μm, the thermal oxidation time is short, the occurrence of warpage can be reduced, and in addition, the MOS interface between the polysilicon layer and the thermal oxide film can be reduced. Roughness can be reduced, and the withstand voltage of the thermal oxide film itself can be secured.

Since the dielectric breakdown voltage cannot be compensated for by using the thermal oxide film alone because the film thickness is insufficient, the thermal oxide film whose surface is uneven due to the roughness of the MOS interface is covered with a CVD oxide film having good step coverage. I have. If the CVD oxide film has a thickness of 0.02 μm or more, the gate withstand voltage can be secured.

Each of the second and thirteenth inventions defines that the thickness of the thermal oxide film is 0.02 to 0.035 μm.

By setting the thickness of the thermal oxide film to 0.02 μm or more, the formation of the MOS interface becomes more reliable. By setting the upper limit to 0.035 μm and reducing the thermal oxidation time, the warpage of the substrate and the interface can be improved. Roughness can be further reduced.

In each of the third, fourteenth and fifteenth aspects, the polysilicon layer is used as a capacitance line for holding a liquid crystal, and a suitable total thickness of the gate oxide film at that time is defined. That is, according to claim 3, the step of forming the polysilicon layer includes a step of forming the polysilicon layer extending to a lower layer position facing the metal wiring layer via the gate oxide film, Forming the gate oxide film comprising the thermal oxide film and the CVD oxide film in a total thickness of 0.05 to 0.12 μm.
That is defined.

In this way, a storage capacitor connected in parallel to the liquid crystal can be formed by the polysilicon layer and the metal wiring layer.
When a polysilicon layer is used as a capacitance line of a storage capacitor,
The size of the capacitance depends on the total thickness of the gate oxide film, and if the total thickness is set in the above range, the capacitance suitable as the storage capacitance of the liquid crystal without excessively increasing the area of the storage capacitance line. Can be secured.

Claims 4 to 6 define preferred process conditions in the step of forming the CVD oxide film. According to a fourth aspect of the present invention, in the step of forming the CVD oxide film, the flow ratio of the gas containing oxygen to the gas containing silicon is set to 40 to 40.
It is preferably 60. The flow rate ratio may be set outside the above range, but when set in the above range, the in-plane uniformity of the thickness of the CVD oxide film becomes 5% or less.

According to a fifth aspect of the present invention, the CVD method
The temperature in the step of forming the oxide film is preferably set to 750 to 850 ° C.

This temperature may be set outside the above range as long as it is 1050 ° C. or less.
The step coverage of the D film can be secured to 0.7 or more.

Further, as set forth in claim 6, the CV
The pressure in the step of forming the D oxide film is preferably 200 Pa or less.

The pressure can be set to 300 Pa or less, but if it is set to 200 Pa or less, a step coverage of the CVD film of 0.7 or more can be secured.

According to a seventh aspect of the present invention, the CVD method
After the step of forming an oxide film, the CVD oxide film may be annealed. By doing so, the fixed charge in the CVD oxide film can be removed, and the characteristics of the TFT can be improved.

According to an eighth aspect of the present invention, before forming the polysilicon layer on the first substrate, the first layer is formed at a temperature substantially equal to a thermal oxidation temperature in the step of forming the thermal oxide film. Is preferably annealed.

This makes it possible to remove in advance the distortion generated in the first substrate in the thermal oxide film forming step, and to further reduce the amount of warpage.

According to a ninth aspect of the present invention, the step of forming the polysilicon layer includes a step of forming amorphous silicon on the first substrate and a step of forming the polysilicon layer by solid-phase growing the amorphous silicon. And a step of performing

As compared with the case where the polysilicon layer is formed by CVD, the grain size becomes large, and the polysilicon layer approaches the characteristics of single crystal silicon, so that the characteristics as a semiconductor can be improved.

According to a tenth aspect, each of the layers is formed using a substrate having a diameter or a diagonal length of 8 inches or more,
Thereafter, it is preferable that the method further includes a step of cutting the first substrate into a predetermined size.

In the present invention, even if a substrate having a size of 8 inches or more is used, the amount of warpage can be suppressed to 100 μm or less. By using a liquid crystal substrate obtained by cutting the substrate, a predetermined cell gap can be obtained. The liquid crystal display panel can be assembled by supporting.

The invention according to claim 11, wherein the step of forming the gate oxide film includes a step of thermally oxidizing the polysilicon layer to form a thermal oxide film, and the step of forming the first oxide film on which the thermal oxide film is formed.
A silicon oxide film is vapor-phase grown on the entire surface of
And a step of forming a VD film. Claim 16
A liquid crystal display panel obtained by the method according to claim 11 is defined.

By forming a CVD oxide film on the entire surface of the first substrate on which the thermal oxide film is formed, a photolithography step for patterning and etching are performed as in the case where only the thermal oxide film is covered. Steps such as steps can be omitted, and processing time can be greatly reduced. In addition, the CVD oxide film formed in a region other than the thermal oxide film reduces a step on the surface of the rubbed substrate during the rubbing process after all the films are formed on the first substrate. To contribute. If the level difference is small, generation of a region that is not subjected to the rubbing treatment can be prevented, and the liquid crystal can be properly aligned.

A seventeenth aspect defines an electronic device having the liquid crystal display panel according to any one of the twelfth to sixteenth aspects. According to this electronic device, the display characteristics can be improved by the liquid crystal display panel that can obtain the above-described effects.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross section of an active matrix type liquid crystal display panel. In FIG. 1, this liquid crystal display panel is configured by sealing a liquid crystal 14 between two transparent substrates 10 and 12. One substrate 10 is an insulating substrate made of quartz or the like. As will be described later, the quartz substrate 10 has a top-gate thin film transistor (T) as a switching element connected in series to the liquid crystal 14 of each pixel.
FT) 30 are formed in an array. This quartz substrate 10
Is also formed with a TFT constituting a liquid crystal drive circuit. The other substrate 12 is formed of, for example, a glass substrate. A transparent electrode 16 made of ITO (Indium Tin Oxide) is formed on a surface 12a of the glass substrate 12 facing the quartz substrate 10 so as to cover the facing surface 12a, and functions as a common electrode. The counter substrate 12
Does not have a chrome layer or the like for a black matrix, and this black matrix is, as described later,
It is arranged only on the quartz substrate 10 side.

Next, each layer formed on the quartz substrate 10 will be described with reference to FIGS. FIG. 2 is a perspective view of each layer formed in each pixel region on the quartz substrate 10, showing a dual-gate type TFT structure. On the quartz substrate 10, mainly the above-described TFT 30
And a light-shielding layer 20 formed between the TFT 30 and the quartz substrate 10, and an insulating layer 22 for insulating the light-shielding layer 20 from the TFT 30.

As shown in FIGS. 1 and 2, the TFT 30 has a first polysilicon layer 40 serving as a source and a drain of a transistor, and a second polysilicon layer 44 serving as a gate of the transistor. Both polysilicon layers 40, 44
Between the first polysilicon layer 40 and the S
A gate oxide film 42 of iO ₂ is provided. As shown in FIGS. 2 and 3D, a plurality of second polysilicon layers 44 are provided in parallel with a first direction (horizontal direction in the drawing) of the liquid crystal display panel, and a plurality of scanning signal lines Used as

Further, a first interlayer insulating layer 46 is provided so as to cover the gate oxide film 42 and the second polysilicon layer 44. A metal wiring layer 48 formed of, for example, aluminum (Al) that functions as a source line of the transistor is provided thereon. The metal wiring layer 48 is connected to the first polysilicon layer 40 via a first contact hole 47 formed in the first interlayer insulating layer 46. As shown in FIGS. 2 and 4B, a plurality of metal wiring layers 48 are provided in parallel with a second direction (vertical direction in the drawing) orthogonal to the first direction of the liquid crystal display panel. It is used as a plurality of data signal lines of a liquid crystal display panel.

The metal wiring layer 48 and the first interlayer insulating layer 4
6, a second interlayer insulating layer 50 is provided, on which a transparent electrode 52 made of, for example, ITO is formed at a position facing each pixel region. This transparent electrode 52 has a first
It is connected to the first polysilicon layer 40 via the second contact hole 51 formed in the second interlayer insulating layers 46 and 50, and functions as a pixel electrode.

In this liquid crystal display panel, the TFT 30 is provided on the second polysilicon layer 44 corresponding to the scanning signal line of a certain row.
Is applied within the selection period, all the TFTs in that row are turned on. At this time, a data signal is supplied to each pixel via a plurality of metal wiring layers 48 corresponding to the data signal lines of each column, and each of the turned-on T
A signal potential is applied to each transparent electrode 52 via the FT 30. In this case, a difference voltage between the common potential of the transparent electrode 16 of the counter substrate 12 and the signal potential of the transparent electrode 52 of each pixel on the quartz substrate 10 is applied to the liquid crystal 14.
In the non-selection period, the TFT 30 is turned off, and the display state is maintained until the next selection period by the voltage charged in the liquid crystal 14 in the selection period. Note that a storage capacitor described later is connected in parallel with the liquid crystal 14 in order to improve the voltage holding characteristic in the non-selection period. By repeating this operation for each row, a desired image can be displayed on the liquid crystal display panel.

Next, each layer formed on the quartz substrate 10 will be described with reference to the manufacturing steps shown in FIGS. 3 (A) to 3 (D) and 4 (A) to 4 (C).

<Annealing Step> Quartz Substrate 1 in Manufacturing Stage
0 is an 8-inch wafer shape. First, the quartz substrate 10 is heated at a temperature higher than the highest process temperature of the quartz substrate 10 (1000 ° C. in the thermal oxidation step for the gate oxide film 42 in this case), for example, 1000 ° C., with an inert gas such as N _2.
Annealing was performed in a gas atmosphere. By this pre-treatment, distortion generated in the quartz substrate 10 during a heat treatment at the highest process temperature performed later is removed in advance.

<Step of Forming Light Shielding Layer 20>
Indicates that light reflected on the surface of the quartz substrate
To prevent the light from entering. The light-shielding layer 20 can prevent photocarriers from being formed in the TFT 30, and prevent crosstalk due to leak current.

For this purpose, as shown in FIG. 1, the light-shielding layer 20 is formed over a width wider than the width of the first polysilicon layer 40, and is formed of a material having a sufficient light-shielding characteristic. You. As the light-shielding characteristics required of the light-shielding layer 20, the OD value is 3 or more, in other words, the transmittance is 1/100.
0 or less.

As the characteristics of the light-shielding layer 20, in addition to the light-shielding characteristics described above, it is necessary that the liquid-crystal display panel has heat resistance at the maximum process temperature. In this embodiment,
As will be described later, the thermal oxidation step of the gate oxide film 42 is the highest process temperature, for example, 1000 ° C. Therefore, the light-shielding layer 20 has a maximum process temperature of 100.
A metal or a metal compound is used as a material having a melting point of 0 ° C. or higher. Suitable materials of this type include tungsten silicide (WSi), molybdenum silicide (M
oSi) and the like. This type of silicide-based metal is preferable because it has good compatibility with the quartz substrate 10 and can have a thermal expansion coefficient close to that of the quartz substrate 10. This can prevent the quartz substrate 10 and the like from being cracked or broken.

As shown in FIG. 3A, the light-shielding layer 20 is formed of a region A facing the TFT 30 and a region B extending in the horizontal direction (the direction parallel to the scanning signal line). With this arrangement, the light-shielding layer 20 and the metal wiring layer 48 having a light-shielding property intersecting with the light-shielding layer 20 allow
The black matrix surrounding each pixel can be formed only on the quartz substrate 10 side. Thus, unlike the case where a black matrix is formed by a light shielding layer, for example, a chromium layer provided on the opposite substrate, the quartz substrate 10 and the opposite substrate 12
Strict alignment with is not required. Conventionally,
Although it was necessary to ensure a relatively large margin in the line width of the black matrix forming layer in consideration of the displacement between the two substrates, this is no longer necessary in the present embodiment. Therefore,
The aperture ratio of the liquid crystal display panel increases, and a bright display screen can be secured.

The light shielding film 20 is formed by sputtering or CVD.
(Chemical vapor deposition), and a photolithography process and an etching process are performed so that only the regions A and B shown in FIG. When the light-shielding layer 20 is used as a black matrix as shown in FIG. 3A, the light-shielding layer 20 needs to have a sufficient thickness to be black. Therefore, in the case of a silicide-based metal, the thickness may be 0.1 μm or more.

<Step of Forming Insulating Layer 22>
Is for insulating the light shielding layer 20 from the first polysilicon layer 40. This insulating layer 22 is formed of, for example, SiO ₂ , for example, by CVD.

<Regarding the Setting of the Potential of the Light-Shielding Layer 20 and the Film Thickness of the Insulating Layer 22> The light-shielding layer 20 has a floating potential when not connected to another wiring. In this case, if the thickness of the insulating layer 22 is small, the charge of the light-shielding layer 20 adversely affects the switching of the TFT 30 as described above. To prevent this, the thickness of the insulating layer 22 must be increased.

In this embodiment, a constant DC potential is applied to the light shielding layer 20 in order to realize a normal switching operation in the TFT 30 depending only on the gate potential without depending on the thickness of the insulating layer 22. I have.

In this embodiment, the off potential applied to the gate of the TFT 30 is constantly applied to the light shielding layer 20. The TFT 30 provided for each pixel is an N-type TFT, and, for example, -1 V is always applied to the light shielding layer as an off potential to the gate. In this case, the light shielding layer 20 is interposed via the insulating layer 22.
Even if the electric charge of the TFT 30 affects the TFT 30, the electric charge of the light shielding layer 20 does not cause the TFT 30 to be turned on by mistake. To do so, the potential applied to the light shielding layer 20 may be set to a potential lower than the threshold value of the TFT 30. The ground potential or the negative potential may be used for an N-channel TFT.

The off-potential is also applied to the light-shielding layer provided opposite to the TFT forming the liquid crystal drive circuit. In this case, when both N-type and P-type TFTs are used as the transistors used in the liquid crystal drive circuit, different off-potentials are applied to the light-shielding layers facing the N-type and P-type TFTs.

In this case, since the switching operation of the TFT 30 is not affected by the electric charge of the light shielding layer 20, the thickness of the insulating film 22 is simply determined by electrically connecting the light shielding layer 20 and the first polysilicon layer 40. Any material that can be insulated can be used. The thickness of the light-shielding layer 20 in this case may be 0.05 μm or more, and the thickness of the insulating layer 22 (0.8 μm or more) required when the light-shielding layer 20 has a floating potential.
It may be thinner. The thickness of the insulating layer 22 is 0.0
It can be selected from 5 to 1.5 μm.

In the case of FIG. 3A, the light shielding layers 22 are provided separately from each other by at least the number of the scanning signal lines, corresponding to the second polysilicon layer 44 as the scanning signal lines. In this case, a scanning signal to a corresponding scanning signal line may be supplied to each light shielding layer 22. In this case, the second polysilicon layer 44 and the light shielding layer 20, which are the scanning signal lines, both have the ON potential when the TFT 30 is to be turned on, and have the OFF potential when the TFT 30 is to be turned off.
A malfunction does not occur in the switching of the FT 30.

<About the case where the light shielding layer 20 is used as a capacitance line of a storage capacitor> In addition to the regions A and B shown in FIG. 3A, the light shielding layer 20 can be formed also in a region C shown in FIG. . This region C is a region facing the region where the first polysilicon layer 40 shown in FIG. 3B extends in the vertical direction in FIG. In this case, the light-shielding layer 20 and the first polysilicon layer 40 can form the storage capacitor C1.

The first and second polysilicon layers 40, 4
4 also constitutes the storage capacitor C2. Each of the storage capacities C
6, the liquid crystal 14 and the storage capacitors C1 and C2 are connected in parallel, respectively, as shown in FIG. Therefore, the total storage capacity in this case is C1 + C2, and the storage capacity can be increased.

Here, the storage capacitance C1 is different from that of the insulating layer 22.
The capacitance can be set to a desired value by selecting from the preferable range of the insulating layer 22 described above, which is 0.05 to 1.5 μm. The storage capacitance C1 increases as the thickness of the insulating layer 22 decreases. Therefore, when it is desired to secure a large storage capacitance C1, as described above, it is preferable to set the light shielding layer 20 to a constant DC potential and make the insulating layer 22 thin.

The total storage capacitance C1 + C2 may be set in the following width according to the density of the pixels formed on the quartz substrate 10. V with a pixel density of 640-480 dots
In the case of GA (Video Graphics Array), 20fF ~
In the case of SVGA (Super Video Graphics Array) having a pixel density of 200 fF and a pixel density of 800 to 600 dots,
20 fF to 200 fF.

<Step of Forming First Polysilicon Layer 40> After the formation of the insulating layer 22, the quartz substrate 10 is heated to about 500 ° C. while supplying monosilane (SiH ₄ ) gas at 500 cc / m 2.
at a pressure of 30 Pa and a quartz substrate 10
An amorphous silicon (a-Si) deposition film was formed thereon. By performing this process for about 2 hours,
An a-Si film having a thickness of 0.055 μm was formed.

Thereafter, annealing was performed at 640 ° C. for about 6 hours in an N ₂ atmosphere, and a polysilicon film was formed by solid phase growth. There is also a method of forming a polysilicon layer by CVD, but this results in a fine grain. In this embodiment, since the solid phase growth of grain is performed from a-Si in the form of obtuse crystals to form polysilicon, the grain size is large, the formed polysilicon layer is close to the characteristics of a single crystal, and the characteristics as a semiconductor are reduced. Have improved.

Thereafter, a first polysilicon layer 40 having a pattern shown in FIG. 3B is formed by performing a photolithography step, an etching step, and the like.

The film thickness of the first polysilicon layer 40 is reduced by a subsequent thermal oxidation step, but the final film thickness is preferably 0.02 to 0.15 μm. Below this lower limit, the resistance of the first polysilicon layer 40 becomes too large, and there is a possibility that the ON current cannot be secured. In addition,
Since this on-current flows in a predetermined thickness region on the MOS interface side, if the thickness is larger than that, the leak current increases. Therefore, it is preferable that the on-current does not exceed the upper limit of the above range.

<Step of Forming Gate Oxide Film 42> (1) Formation of Thermal Oxide Film First, the first polysilicon layer 40 was thermally oxidized for 30 minutes in an atmosphere of 1000 ° C. and 100% dry oxygen. At this time,
The first polysilicon layer 40 of 0.055 μm has a thickness of 0.04 μm.
m and a thermal oxide film (SiO ₂ ) 42a of 0.03 μm
Was formed on the first polysilicon layer 40.

FIG. 7 shows the relationship between the thermal oxidation time and the thermal oxide film thickness, and FIG. 8 shows the relationship between the thermal oxide film thickness and the warpage generated on the 8-inch quartz substrate 10. As shown in FIG. 8, the upper limit of the thermal oxidation temperature is 1050 ° C. at which the warp of the 8-inch quartz substrate 10 becomes 100 μm or less. As is clear from FIG. 8, 1100, 11 when the thermal oxidation temperature exceeded 1050 ° C.
At 50 ° C., the warpage of the quartz substrate 10 cannot be suppressed to 100 μm or less.

Even if the thermal oxidation is performed at 1050 ° C. or less, if the thermal oxidation time is long, in other words, if the thermal oxide film 42a is thick, the warpage of the quartz substrate 10 cannot be suppressed to 100 μm or less. . According to FIG. 8, when the thermal oxidation temperature is 1050 ° C. or less, the thickness of the thermal oxide film is approximately 0.1 μm or less, and the warpage of the quartz substrate 10 can be suppressed to 100 μm or less. However, due to other factors described below,
It is preferable that the thermal oxide film thickness is further thinner.

FIGS. 9A to 9F show MOS transistors after thermal oxidation.
It is a diagram schematically showing an electron micrograph of the interface,
It shows the roughness (irregularities) of the MOS interface for each thermal oxidation temperature. As can be seen from the figure, the roughness of the MOS interface decreases as the thermal oxidation temperature increases. In this sense, the higher the thermal oxidation temperature, the better, but considering the warpage of the quartz substrate 10,
The temperature must be 0 ° C. or lower.

According to the present inventors, it has been found that the above-described roughening of the MOS interface becomes more prominent as the thermal oxidation time is longer, in other words, as the thermal oxide film thickness is larger. And this M
Roughness of the OS interface causes a portion of the thermal oxide film 42a on which the film density becomes coarse, current flows intensively there, and the withstand voltage of the thermal oxide film 42a decreases.

In consideration of these points, thermal oxide film 42
The thickness of “a” is preferably 0.015 to 0.05 μm, and more preferably 0.02 to 0.035 μm. The lower limit of the thickness of the thermal oxide film 42a is determined because if it is smaller than that, it becomes difficult to form the interface itself. The upper limit is
It is determined from the viewpoint of ensuring the dielectric strength in view of the relationship between the warpage of the substrate and the temperature described above.

(2) Formation of CVD Oxide Film By forming the above-described thermal oxide film 42a, a MOS interface with relatively little roughness can be formed, but with this alone, a sufficient dielectric breakdown voltage cannot be secured. Therefore, in the present embodiment, the thermal oxide film 42a having the irregularities reflecting the roughness of the MOS interface is formed on the Si film formed by CVD having high step coverage.
It is covered with the O ₂ film 42b. This CVD oxide film 42b
Is formed on the entire surface of the quartz substrate 10 as shown in FIG. This eliminates the need for a photolithography step and an etching step for patterning. In addition, the CVD process is performed at a position other than the thermal oxide film 42a shown in FIG.
By forming the oxide film 42b, a step formed on the surface of the second interlayer insulating film 50 and the transparent electrode 52, which are the uppermost layers of the quartz substrate 10, can be reduced. For this reason, the rubbing process for the liquid crystal alignment is facilitated, and the cell gap between the substrates 10 and 12 is easily suppressed to a desired dimensional accuracy.

The CVD oxide film 42b is formed by mixing a gas containing silicon, for example, monosilane (SiH ₄ ), and a gas containing oxygen, for example, nitrogen peroxide (N ₂ O), with a flow rate ratio of 1:50 in excess of oxygen. Atmosphere, SiO by HTO method
_Two films were grown by vapor phase. In an excess silicon atmosphere, CV
It is not preferable because the D oxide film 42b has a charge. The pressure at this time was 80 Pa. The upper limit of the film formation temperature is 1050 ° C., which is the same as the thermal oxidation temperature, and preferably 600 to
1000 ° C. The upper limit is that the warpage of the quartz substrate 10 is 10
The lower limit is determined from the viewpoint of ensuring the quality of the CVD film 42b. This film formation temperature is
More preferably 700-900 ° C, still more preferably,
As shown in FIG. 10, the temperature is set to 750 to 850 ° C. in order to secure a step coverage of 0.7 or more. The pressure is preferably 300 pa or less, and as shown in FIG.
a. Although the lower limit of the pressure is not particularly limited, it was confirmed that a high step coverage was obtained at a pressure of 40 Pa as shown in FIG. As shown in FIG. 12, the flow ratio (N ₂ O / SiH ₄ ) of a gas containing oxygen, for example, nitrogen peroxide (N ₂ O) to a gas containing silicon, for example, monosilane (SiH ₄ ), is quartz. From the viewpoint of reducing the in-plane uniformity of the substrate 10 to 10% or less, 25 to
75, and in order to make the in-plane uniformity 5% or less, 40 to 6
It is good to set to 0.

The thickness of the CVD oxide film 42b is 0.02 μm.
m or more. This value is determined from the viewpoint of ensuring the gate breakdown voltage, and the step coverage improves as the film thickness increases. The thickness of the CVD oxide film 42b is
It can be determined in consideration of the total thickness of the gate oxide film 42 composed of the D oxide film 42b and the thermal oxide film 42a. The thickness of the gate oxide film 42 also affects the size of the storage capacitor C2 formed by the first and second polysilicon layers 40 and 44. As the thickness of the gate oxide film 42 is reduced,
The storage capacitance C2 can be increased. From the viewpoint of securing the storage capacitor C2, the thickness of the gate oxide film 42 is set to 0.05 to
The thickness is preferably 0.12 μm.

Therefore, in order to obtain this total film thickness, the thickness of the above-mentioned thermal oxide film 42a must be 0.015 to 0.0
Considering that the thickness is 5 μm, the thickness of the CVD oxide film 42b in the range of 0.03 to 0.1 μm is sufficient. As described above, the thickness of the thermal oxide film 42a is set to 0.02 to 0.035.
μm, the thickness of the CVD oxide film 42b is
A range of 0.05 to 0.09 μm is sufficient.

This CVD oxide film 42b is thereafter annealed. In an inert gas such as N ₂ atmosphere, 600
Annealing was performed at a temperature in the range of １０００1000 ° C., for example, 950 ° C. for 30 minutes. Thereby, the defects in the CVD oxide film 42b can be rearranged, and the fixed charge can be released.
The above temperature range is necessary to release the fixed charge.

<Step of Forming Capacitance in First Polysilicon Layer 40> Region D in FIG. 3C is masked, and impurities such as phosphorus are added to the other regions of the first polysilicon layer 40 where capacitance is to be formed. At a dose amount of, for example, 3 × 10 ¹⁴ / c
doping with m ³ , and the first polysilicon layer 40
Was reduced in resistance. The dose amount is 1.0 × 1
It is preferable to be in the range of 0 ^{14 to} 2.0 × 10 ¹⁵ / cm ³ .
The lower limit is determined from the viewpoint of securing the conductivity required for forming a capacitance in the first polysilicon layer 40, and more preferably, 3.0 × 10 ¹⁴ / cm ³ or more, whereby the resistance is sufficiently reduced. . The upper limit is determined from the viewpoint of suppressing the deterioration of the gate oxide film 42.

<Step of Forming Second Polysilicon Layer 44> Next, a second polysilicon layer is formed on the entire surface, and is doped with an impurity such as phosphorus for lowering the resistance. Thereafter, by performing a photolithography process and an etching process, FIG.
As shown in (D), a gate electrode is formed by the patterned second polysilicon layer 44. Gate electrode 4
4 crosses the polysilicon layer 40 twice in this embodiment, and has a dual gate structure. With the dual gate structure, leakage current at the time of off can be reduced. Note that a single gate that intersects the polysilicon layer 40 once may be used instead of the dual gate.

<Step of implanting impurities for forming transistor> First, in order to form an N-type transistor,
Using the second polysilicon layer 44 serving as a gate as a mask,
The source and drain regions in the region D in FIG. 3D are lightly doped with impurity phosphorus at a dose of 2 × 10 ¹³ / cm ³ . Further, a mask wider than the gate width is formed on the gate, and impurity boron is added to the source region of FIG.
A second implantation is performed at a dose of 2 × 10 ¹⁵ / cm ³ to perform high doping. Thus, the masked region becomes a lightly doped drain. The dose at the time of the second driving is preferably 1.0 × 10 ¹² to
It is good to set it to 1.0 × 10 ¹⁴ / cm ³ . Below the lower limit, the resistance increases and the on-current decreases. Exceeding the upper limit makes it easier for leakage current to flow. In this embodiment, the LDD structure has a low-concentration region and a high-concentration region in the source / drain region. However, the present invention is not limited to the LDD structure, and the source / drain region is separated from the gate electrode. An offset structure may be used. Alternatively, a self-aligned structure in which source / drain regions are formed using the gate electrode as a mask may be used. LD
With the D structure or the offset structure, a leakage current at the time of off can be reduced. Therefore, when used in combination with the above-described dual gate structure, the leakage current at the time of off is further reduced.

Similarly, an N-type transistor used as a liquid crystal driver circuit is formed on the quartz substrate 10. The P-type transistor of the liquid crystal driver is formed in the same manner, that is, boron is lightly doped at a dose of 1.0 × 10 ¹³ / cm ^{3 using} the gate electrode as a mask. Thereafter, a mask wider than the gate electrode is formed in the gate electrode, and phosphorus is implanted at a dose of 1.0 × 10 ¹⁵ / cm ³ to form an LDD structure.

<Step of Forming First Interlayer Insulating Layer 46>
A first interlayer insulating layer 46 is formed. This is equivalent to 140cc / m of TEOS (Tetra Ethyl Osol Silicate)
in, at a substrate temperature of 680 ° C. and a pressure of 50 Pa, C
It was formed to a thickness of 0.08 μm by VD. After this, 9
Annealing was performed at 50 ° C. for 20 minutes to activate impurities in the first interlayer insulating layer 46 to improve the film quality. After this,
For example, heating was performed at 500 ° C. for 1 hour using a forming gas composed of argon and hydrogen. As a result, hydrogen is contained in the first polysilicon layer 40, silicon unbonded portions are bonded, the level in the gap is reduced, and the TFT 30
The characteristics of were improved.

Further, by performing a photolithography step and an etching step, the first
A contact hole 47 was formed. As an etching step, wet etching was performed after performing dry etching, and light etching for exposing the first polysilicon layer 40 was performed.

<Step of Forming Metal Wiring Layer 48> Aluminum (Al) is sputtered and then patterned to form a metal wiring layer 48 as shown in FIG.
Was formed. At this time, the metal wiring layer 48 is connected to the first polysilicon layer 40 through the first contact hole 47.
Connected to This metal wiring layer 48 is not limited to Al,
Any material having conductivity such as r may be used.

<Step of Forming Second Interlayer Insulating Layer 50> As the second interlayer insulating layer 50, an SiO 2 containing boron and phosphorus is used.
₂ (BPSG) was formed by normal pressure CVD. As the process gas, TEOS, TEB (tetra-ethyl-borate), and TMOP (tetra-methyl-oxy-foslate) were used. Thereafter, the second position is set at the position shown in FIG.
The contact hole 51 was formed by performing the same steps as the first contact hole 47. In the case where the aspect ratio of the second contact hole 51 is large and it is difficult to control the etching stop within the range of the thickness of the first polysilicon layer 40,
For example, a polysilicon sheet may be formed.

<Step of Forming Transparent Electrode 52> On the second interlayer insulating layer 50, ITO (indium tin oxide) was sputtered and then patterned to form the transparent electrode 52 as shown in FIG. .

Although the switching element is a TFT in the above-described embodiment, the present invention can be similarly applied to a liquid crystal display panel having a switching element such as a back-to-back diode in which photo carriers are generated by reflected light.

In the above-described embodiment, the light-shielding layer 20 and the insulating layer 22 are formed under the first polysilicon layer 40, but these are not necessarily provided.

<Description of Liquid Crystal Panel> FIG. 13 shows an example of a system configuration of a substrate on which TFTs are formed in the liquid crystal panel of the above embodiment. Each pixel 190 arranged corresponding to the intersection of the gate line 102 and the signal line 103 arranged so as to cross each other includes a pixel electrode 114 made of ITO or the like and a TFT 191. TFT 191
Is for applying a voltage corresponding to a pixel signal on the signal line 103 to the pixel electrode 114. T in the same row (Y direction)
The FT 191 has its gate connected to the same gate line 102 and its drain connected to the corresponding pixel electrode 114. Also, the TFTs 191 in the same row (X direction)
Have their sources connected to the same signal line 103. In this embodiment, the transistors constituting the peripheral circuits (X and Y shift registers and sampling means) 150 and 160 are constituted by polysilicon TFTs having a polysilicon layer as an operation layer similarly to TFTs for driving pixels. Thus, the transistors constituting the peripheral circuits 150 and 160 are formed simultaneously with the pixel driving TFT by the same process.

In this embodiment, the signal lines 10 are arranged on one side (the upper side in FIG. 13) of the display area (pixel matrix) 120.
A shift register (hereinafter, referred to as an X shift register) 151 for sequentially selecting the gate line 102 is disposed on the other side of the pixel matrix. 161 are provided. A buffer 163 is provided at the next stage of the Y shift register 161 as necessary. The other end of the signal line 103 has a sampling switch (T
FT) 152, and these sampling switches 152 are connected to external terminals 174, 175, 176.
Are connected to the video lines 154, 155, and 156 for transmitting the image signals VID1 to VID3 input to the CPU and the signal line 103, and are sequentially turned on / off by sampling pulses output from the X shift register 151. ing. The X shift register 151 has a terminal 17
Clock CLX externally input through the second and the second 173
, Xn to select all the signal lines 103 one by one in order during one horizontal scanning period on the basis of 1, CLX2, and to the control terminal of the sampling switch 152. Supply. On the other hand, Y
The shift register 161 is operated in synchronization with clocks CLY1 and CLY2 externally input via the terminals 177 and 178, and sequentially drives the gate lines 102.

FIGS. 14A and 14B show a cross section and a planar layout configuration of a liquid crystal panel 130 to which the above liquid crystal panel is applied. As shown in the figure, on the front side of the liquid crystal panel substrate 110, an incident side glass substrate (a counter substrate) having a color filter layer 113 and a counter electrode 133 made of a transparent film electrode (ITO) to which a common electrode potential is applied. ) 131 are disposed at appropriate intervals, and a TN (Twisted Nema) is disposed in a gap surrounded by a sealing material 136.
tic) type liquid crystal or SH (Super Homeotropic) type liquid crystal 13
The liquid crystal panel 130 is filled with 7 or the like. In addition, above the peripheral circuits 150 and 160,
For example, it is configured to be shielded from light by a black matrix provided on the counter substrate 131 or the like. Note that a liquid crystal injection port 138 is provided in the counter substrate 131.

<Explanation of Electronic Apparatus> An electronic apparatus using the liquid crystal display panel of the above-described embodiment includes a display information output source 1000, a display information processing circuit 1002, and a display information output circuit 1000 shown in FIG.
Display driving circuit 1004, display panel 1 such as a liquid crystal panel
006, clock generation circuit 1008 and power supply circuit 101
0 is included. The display information output source 1000
It includes a memory such as an OM and a RAM, a tuning circuit for tuning and outputting a television signal, and the like, and outputs display information such as a video signal based on a clock from a clock generation circuit 1008. The display information processing circuit 1002 processes and outputs display information based on the clock from the clock generation circuit 1008. This display information processing circuit 100
2 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, or the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010
Power is supplied to each of the above circuits.

As an electronic apparatus having such a configuration, FIG.
, A personal computer (PC) and an engineering workstation (EWS) for multimedia shown in FIG. 17, a pager shown in FIG. 18, or a mobile phone, a word processor, a television, a viewfinder type video or a monitor direct view type video. Examples include a tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

The liquid crystal projector shown in FIG. 16 is a projection type projector using a transmission type liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system. In FIG. 16, in projector 1100,
The projection light emitted from the lamp unit 1102 of the white light source is provided inside the light guide 1104 by a plurality of mirrors 11.
06 and two dichroic mirrors 1108 divide the light into three primary colors of R, G, and B, and guide the liquid crystal to three liquid crystal panels 1110R, 1110G, and 1110B that display images of the respective colors. The light modulated by the respective liquid crystal panels 1110R, 1110G and 1110B is applied to the dichroic prism 1112 by 3
It is incident from the direction. Dichroic prism 1112
Then, the light of red R and blue B is bent 90 °,
Since the light of green G goes straight, images of each color are synthesized,
A color image is projected through a projection lens 1114 onto a screen or the like.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206.

The pager 1300 shown in FIG. 18 includes a liquid crystal display panel 1304, a light guide 1306 having a backlight 1306a, a circuit board 1308, and first and second shield plates 1310, 1 in a metal frame 1302.
312, two elastic conductors 1314 and 1316, and a film carrier tape 1318. Two elastic conductors 1314 and 1316 and film carrier tape 1
318 is a liquid crystal display panel 1304 and a circuit board 1308
Is to be connected.

Here, the liquid crystal display panel 1304 has liquid crystal sealed between two transparent substrates 1304a and 1304b, thereby forming at least a dot matrix type liquid crystal display panel. Fig. 1
5 or a display information processing circuit 1002 in addition to the driving circuit 1004. Circuits not mounted on the liquid crystal display panel 1304 are external circuits, and can be mounted on the circuit board 1308 in the case of FIG.

FIG. 18 shows the structure of a pager, and therefore, a circuit board 1308 is provided in addition to the liquid crystal display panel 1304.
However, what fixed the liquid crystal display panel 1304 to the metal frame 1302 as a housing can also be used as a liquid crystal display device which is one component for electronic devices. Further, in the case of a backlight type, a liquid crystal display panel 1304 and a light guide 1306 provided with a backlight 1306a can be incorporated in a metal frame 1302 to constitute a liquid crystal display device. Instead of these, as shown in FIG.
4 is a polyimide tape having a metal conductive film formed on one of two transparent substrates 1304a and 1304b.
TCP (Tap) with IC chip 1324 mounted on
e Carrier Package 1320 can be connected to be used as a liquid crystal display device, which is a component for electronic devices.

[0096]

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a liquid crystal display panel of the present invention.

FIG. 2 is a perspective view of each layer formed on a quartz substrate of the liquid crystal display panel of FIG.

FIG. 3A to FIG. 3D are process diagrams in the order of the manufacturing process of each layer formed on a quartz substrate.

FIGS. 4A to 4C are process diagrams in the order of the manufacturing process of each layer formed on the quartz substrate following FIG. 3D.

FIG. 5 is a plan view illustrating a formation pattern of the light shielding layer when the light shielding layer is used as a capacitance line of a storage capacitor connected in parallel to liquid crystal.

FIG. 6 is a circuit diagram showing an electrical connection relationship between a switching element, a liquid crystal, and a storage capacitor.

FIG. 7 is a characteristic diagram showing a relationship between a thermal oxidation time and a thermal oxide film thickness.

FIG. 8 is a characteristic diagram showing a relationship between a thermally oxidized film thickness and a warp generated on an 8-inch quartz substrate.

FIGS. 9A to 9F are characteristic diagrams schematically showing electron micrographs showing a rough state of a MOS interface at each thermal oxide film temperature.

FIG. 10 is a characteristic diagram showing a temperature dependence of a step coverage of a CVD oxide film constituting a gate oxide film.

FIG. 11 is a characteristic diagram showing a pressure-dependent characteristic of a step coverage of a CVD oxide film forming a gate oxide film.

FIG. 12 is a characteristic diagram showing the flow rate ratio dependence of the in-plane uniformity of a CVD oxide film forming a gate oxide film.

FIG. 13 is a schematic explanatory view showing a TFT and a driving circuit formed on the quartz substrate side shown in FIG.

14A is a cross-sectional view of the entire liquid crystal panel shown in FIG. 1, and FIG. 14B is a diagram showing a planar layout thereof.

FIG. 15 is a block diagram of an electronic device of the invention.

FIG. 16 is a schematic explanatory view of a projector to which the present invention is applied.

FIG. 17 is an external view of a personal computer to which the present invention is applied.

FIG. 18 is an exploded perspective view of a pager to which the present invention is applied.

FIG. 19 is a schematic explanatory view showing an example of a liquid crystal display panel provided with an external circuit.

FIG. 20 is a characteristic diagram showing the amount of warpage that occurs when an 8-inch wafer is annealed at various temperatures.

[Explanation of symbols]

 Reference Signs List 10 quartz substrate 12 glass substrate 14 liquid crystal 16 common electrode (ITO) 20 light shielding layer 22 insulating layer 30 thin film transistor 40 first polysilicon layer (source, drain) 42 gate oxide film 42a thermal oxide film 42b CVD oxide film 44 second polysilicon Layer (gate, scanning signal line) 46 First interlayer insulating layer 47 First contact hole 48 Metal wiring layer (data signal line) 50 Second interlayer insulating layer 51 Second contact hole 52 Pixel electrode (ITO)

Claims (17)

[Claims] 1. A method of manufacturing a liquid crystal display panel in which liquid crystal is sealed between a first substrate on which a semiconductor thin film transistor is formed and a second substrate facing the first substrate, the method comprising: Forming a polysilicon layer serving as a source and a drain of the semiconductor thin film transistor; forming a gate oxide film covering the polysilicon layer; forming a gate layer of the semiconductor thin film transistor on the gate oxide film. Forming, forming a first interlayer insulating layer covering the gate oxide film and the gate layer, and forming a metal wiring layer in contact with the polysilicon layer on the first interlayer insulating layer Forming a second interlayer insulating layer covering the first interlayer insulating layer and the metal wiring layer; and forming the polysilicon layer on the second interlayer insulating layer. Forming a transparent electrode to be contacted; and forming the gate oxide film by thermally oxidizing the polysilicon layer at a temperature of 1050 ° C. or less to form a film having a thickness of 0.015 to 0.05 μm. Forming a thermal oxide film having a thickness of at least 1050 ° C .; and vapor-growing a silicon oxide film on at least the thermal oxide film at a temperature of 1050 ° C. or less to form a CVD film having a thickness of 0.02 μm or more. A method for manufacturing a liquid crystal display panel, comprising: 2. The method according to claim 1, wherein the thermal oxide film has a thickness of 0.02 to 0.035 μm. 3. The method according to claim 1, wherein the step of forming the polysilicon layer includes a step of extending the polysilicon layer to a lower layer position facing the metal wiring layer via the gate oxide film. A step of forming the gate oxide film, wherein a total thickness of the gate oxide film comprising the thermal oxide film and the CVD oxide film is 0.05 to 0.12 μm; Method. 4. The liquid crystal display according to claim 1, wherein in the step of forming the CVD oxide film, a flow ratio of a gas containing oxygen to a gas containing silicon is 40 to 60. Panel manufacturing method. 5. The method according to claim 1, wherein the temperature in the step of forming the CVD oxide film is 750 to 750.
A method for producing a liquid crystal display panel, wherein the temperature is 850 ° C. 6. The method according to claim 1, wherein a pressure in the step of forming the CVD oxide film is set to 200 Pa or less. 7. The method according to claim 1, further comprising, after the step of forming the CVD oxide film, a step of annealing the CVD oxide film to remove a fixed charge in the CVD oxide film. A method for manufacturing a liquid crystal display panel, comprising: 8. The method according to claim 1, wherein before forming the polysilicon layer on the first substrate,
A method of manufacturing a liquid crystal display panel, comprising annealing the first substrate at a temperature substantially equal to a thermal oxidation temperature in the step of forming the thermal oxide film. 9. The method according to claim 1, wherein the step of forming the polysilicon layer includes: a step of forming amorphous silicon on the first substrate; and a step of solid-phase growing the amorphous silicon. A method for manufacturing a liquid crystal display panel, comprising: forming a silicon layer. 10. The method according to claim 1, wherein each of the layers is formed using a substrate having a diameter or a diagonal length of 8 inches or more, and thereafter, cut into the first substrate having a predetermined size. A method for manufacturing a liquid crystal display panel, comprising the steps of: 11. A method of manufacturing a liquid crystal display panel in which liquid crystal is sealed between a first substrate on which a semiconductor thin film transistor is formed and a second substrate facing the first substrate, the method comprising: Forming a polysilicon layer serving as a source and a drain of the semiconductor thin film transistor; forming a gate oxide film covering the polysilicon layer; forming a gate layer of the semiconductor thin film transistor on the gate oxide film. Forming, forming a first interlayer insulating layer covering the gate oxide film and the gate layer, and forming a metal wiring layer in contact with the polysilicon layer on the first interlayer insulating layer Forming a second interlayer insulating layer covering the first interlayer insulating layer and the metal wiring layer; and forming the polysilicon on the second interlayer insulating layer. Forming a transparent electrode in contact with and forming the gate oxide film; forming the thermal oxide film by thermally oxidizing the polysilicon layer; and forming the thermal oxide film. On the entire surface of the first substrate,
Forming a CVD film by vapor-growing a silicon oxide film in a vapor phase. 12. A liquid crystal display panel in which liquid crystal is sealed between a first substrate on which a semiconductor thin film transistor is formed and a second substrate facing the first substrate, wherein the first substrate is the semiconductor thin film transistor A polysilicon layer serving as a source and a drain of the semiconductor device; a gate oxide film formed to cover the polysilicon layer; a gate layer of the semiconductor thin film transistor formed on the gate oxide film; the gate oxide film and the gate A first interlayer insulating layer formed over the first interlayer insulating layer, a metal wiring layer formed on the first interlayer insulating layer and in contact with the polysilicon layer, covering the first interlayer insulating layer and the metal wiring layer; And a transparent electrode formed on the second interlayer insulating layer and in contact with the polysilicon layer. The oxide film is formed by thermally oxidizing the polysilicon layer at a temperature of 1050 ° C. or less, and a thermal oxide film having a thickness of 0.015 to 0.05 μm. A silicon oxide film is formed on the thermal oxide film by vapor phase growth.
A liquid crystal display panel comprising: a CVD film having a thickness of at least 02 μm. 13. The liquid crystal display panel according to claim 12, wherein the thickness of the thermal oxide film is 0.02 to 0.035 μm. 14. The storage capacitor according to claim 12, wherein the polysilicon layer extends to a lower layer position facing the metal wiring layer via the gate oxide film, and is connected in parallel to the liquid crystal. A liquid crystal display panel, which is also used as a line. 15. The liquid crystal display panel according to claim 14, wherein a total thickness of said gate oxide film comprising said thermal oxide film and said CVD oxide film is 0.05 to 0.12 μm. 16. A liquid crystal display panel in which liquid crystal is sealed between a first substrate on which a semiconductor thin film transistor is formed and a second substrate facing the first substrate, wherein the first substrate is the semiconductor thin film transistor A polysilicon layer serving as a source and a drain of the semiconductor device, a gate oxide film formed over the polysilicon layer, a gate layer of the semiconductor thin film transistor formed on the gate oxide film, the gate oxide film and the gate A first interlayer insulating layer formed over the layer, a metal wiring layer formed on the first interlayer insulating layer and in contact with the polysilicon layer, covering the first interlayer insulating layer and the metal wiring layer; A second interlayer insulating layer formed on the second interlayer insulating layer; and a transparent electrode formed on the second interlayer insulating layer and in contact with the polysilicon layer. The oxide film is formed by vapor-growing a silicon oxide film on the entire surface of the first substrate on which the thermal oxide film is formed and a thermal oxide film formed by thermally oxidizing the polysilicon layer. CVD
A liquid crystal display panel comprising: an oxide film. 17. An electronic apparatus comprising the liquid crystal display panel according to claim 12.