JP3830213B2 - Substrate provided with switching element, liquid crystal display panel, and electronic apparatus using the same - Google Patents

Substrate provided with switching element, liquid crystal display panel, and electronic apparatus using the same Download PDF

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JP3830213B2
JP3830213B2 JP28302596A JP28302596A JP3830213B2 JP 3830213 B2 JP3830213 B2 JP 3830213B2 JP 28302596 A JP28302596 A JP 28302596A JP 28302596 A JP28302596 A JP 28302596A JP 3830213 B2 JP3830213 B2 JP 3830213B2
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Prior art keywords
layer
light shielding
liquid crystal
substrate
shielding layer
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JPH10111520A (en
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康二 山崎
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セイコーエプソン株式会社
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal display panel having a thin film transistor (TFT) or the like as a switching element and an electronic apparatus such as a projector using the active matrix liquid crystal display panel.
[0002]
[Background]
An active matrix liquid crystal display panel using TFT as a switching element is used as, for example, a ride valve of a projector. When the light source light of the projector is transmitted through the liquid crystal display panel, it may be reflected by the substrate constituting the panel or by the optical system at the subsequent stage, and may enter the TFT. The polysilicon layer constituting the TFT has a transmittance of 20 to 30% with respect to visible light, generates photocarriers in the TFT, and leak current flows. Due to this leakage current, the TFT is turned on, and crosstalk in which a signal potential is supplied to a pixel that has been in a non-selection period occurs.
[0003]
In order to prevent this, techniques for providing a light shielding layer under the TFT are disclosed in Japanese Patent Publication No. 3-52611, Japanese Patent Application Laid-Open No. 8-171101, Japanese Patent Application Laid-Open No. 3-125123, and the like.
[0004]
[Problems to be solved by the invention]
Since this light shielding layer is formed of a metal or a metal compound, it is necessary to insulate from the TFT, and an insulating layer is provided between the light shielding layer and the TFT. Here, for example, in a top gate type TFT, a polysilicon layer serving as a source and a drain and a light shielding layer face each other through an insulating layer to form a capacitor. At this time, the light shielding layer has a floating potential, and the charge of the light shielding layer varies due to the influence of the charge of the polysilicon layer. Conversely, the TFT is also affected by the charge of the light shielding layer, and this light shielding layer may function as a gate different from the original gate. In other words, the TFT does not turn on unless a leak current flows through the TFT due to the charge of the light shielding layer or a high voltage is not applied to the gate of the TFT. This is more conspicuous as the thickness of the insulating layer that insulates the TFT from the light shielding layer is thinner. To prevent this, an insulating layer that is so thick that the charge of the light shielding layer does not affect the TFT is formed. There must be. This phenomenon is the same when a back-to-back diode is used as a switching element.
[0005]
Accordingly, an object of the present invention is to provide a liquid crystal that prevents the incidence of light on the switching element by the light shielding layer and reduces the occurrence of crosstalk, while the charge of the light shielding layer does not adversely affect the switching operation of the switching element. A display panel and an electronic device using the display panel are provided.
[0006]
Another object of the present invention is to provide a liquid crystal display panel in which a light-shielding layer is also used as a capacitor line of a storage capacitor and the storage capacitor can be increased by thinning an insulating layer, and an electronic device using the same. is there.
[0007]
[Means for Solving the Problems]
  According to an embodiment of the present invention, a liquid crystal is sealed between a pair of substrates, and a switching element that supplies an image signal to a pixel electrode based on a scanning signal on one substrate; In a liquid crystal display panel having a storage capacitor connected between the pixel electrodes,
  The switching element becomes a source and a drainFirstPolysilicon layer and gate electrodeSecond polysilicon layer to beAnd the lower layerFirstSaid polysilicon layer and upper layerSecond polysilicon layerFormed by a top-gate thin film transistor having a gate insulating film provided on
  The one substrate and the thin film transistor;FirstA light shielding layer between the polysilicon layer, the light shielding layer and theFirstProviding an insulating layer for insulating the polysilicon layer;
  SaidFirstThe drain side of the polysilicon layer is formed to be extended between two adjacent pixel electrodes, and the extended portion is used as one electrode of the storage capacitor,The second polysilicon layer is disposed opposite to one electrode of the storage capacitor to be the other electrode of the storage capacitor;
The light shielding layer extends in a direction intersecting with a data signal line connected to the source, and is formed in a lower layer of the storage capacitor so as to be wider than an electrode width of the storage capacitor, and the light shielding layer is formed of the storage capacitor. Is also used as a capacity line
  In the layer between the pixel electrode and the thin film transistor,DeData signal lines are provided.
  In another aspect of the present invention, one substrate having the above-described switching element, light shielding layer, and insulating film is defined.
In one embodiment and another embodiment of the present invention, when the insulating layer is thin, a large storage capacitor formed using the light-blocking layer can be secured, and the pixel voltage retention characteristics in the non-selection period can be improved.
[0008]
  In one embodiment of the present inventionLeaveScan signal is supplied to the light shielding layerWhen doneEven if the thickness of the insulating layer is reduced, the influence of the electric charge of the light shielding layer is constant on the switching element driven by the scanning signal, and it is possible to prevent the switching operation of the switching element from being adversely affected.
[0009]
According to a second aspect of the present invention, in the first aspect, the light shielding layer is set to a potential that turns off the switching element.
[0010]
In this way, the switching element is turned on only by the original on signal. For example, if the switching element is a TFT, the switching element can be turned on only by the on potential to the gate.
[0011]
According to a third aspect of the present invention, in the second aspect, the switching element is a thin film transistor (TFT), and the light shielding layer is set to a potential substantially equal to an off potential applied to the gate of the thin film transistor. It is characterized by.
[0012]
In this case, even if the light shielding layer may function as the second gate, the second gate potential is always an off potential, so that the TFT can be turned on only by the on potential to the original gate. .
[0013]
According to a fourth aspect of the present invention, in any one of the first to third aspects, a liquid crystal driver thin film transistor is formed on the one substrate, and the light shielding layer is also disposed in a region facing the liquid crystal driving thin film transistor. It is characterized by.
[0014]
This can also prevent malfunction of the thin film transistor for liquid crystal driver.
[0015]
According to a fifth aspect of the present invention, liquid crystal is sealed between a pair of substrates, and each pixel position is formed on one substrate by a plurality of scanning signal lines, a plurality of data signal lines, and their intersections. In a liquid crystal display panel having a switching element connected in series with the liquid crystal at
A light shielding layer and an insulating layer that insulates between the light shielding layer and the switching element are provided between the one substrate and each of the switching elements, and the light shielding layer extends in the direction of the scanning signal line. A plurality of the scanning signal lines are continuously provided, and the signal of the corresponding scanning signal line is supplied to each of the light shielding layers.
[0016]
According to the invention of claim 5, the light shielding layer is provided corresponding to the scanning signal line, and the scanning signal supplied to the scanning signal line is also supplied to the corresponding light shielding layer. Accordingly, both the scanning signal line and the light shielding layer are simultaneously at the same potential of the on potential or the off potential, and the influence of the light shielding layer can be ignored.
[0017]
According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the film thickness of the insulating layer is O.D. It is characterized by being 0.5 to 1.5 μm.
[0018]
As described above, since the charge of the light shielding layer does not adversely affect the switching operation of the switching element, the above-described thickness is sufficient for the insulating layer to be electrically insulated from the switching element and the light shielding layer. May be made thinner than before.
[0021]
The invention of claim 8 is the invention according to any one of claims 1 to 7,
The light shielding layer is arranged in a direction orthogonal to the data signal line formed on the one substrate, and the data signal line and the light shielding layer constitute a black matrix.
[0022]
In this way, since the black matrix can be arranged only on one substrate side, strict alignment with the other substrate becomes unnecessary during assembly. Further, the margin of the black matrix line width can be reduced, and the aperture ratio of the liquid crystal display panel is increased.
[0023]
According to a ninth aspect of the present invention, in any one of the first to eighth aspects, the one substrate is a quartz substrate, and the light shielding layer is a silicide-based metal.
[0024]
Silicide-based metal has a melting point sufficiently higher than the maximum process temperature when forming a switching element on one substrate, and the coefficient of thermal expansion with a quartz substrate is closer to that of other metals or metal compounds. Therefore, the generation of cracks and cracks can be reduced.
[0025]
An electronic apparatus according to a tenth aspect of the invention includes the liquid crystal display panel according to any one of the first to ninth aspects.
[0026]
According to the invention of claim 10, the crosstalk is reduced, and the switching operation can be accurately executed by the switching element depending on the signal potential of the scanning signal line, and the image quality of the display screen of the electronic device is improved. .
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0028]
FIG. 1 shows a cross section of an active matrix liquid crystal display panel. In FIG. 1, this liquid crystal display panel is configured by enclosing a liquid crystal 14 between two substrates 10 and 12 which are transparent substrates. One substrate 10 is an insulating substrate such as quartz. As will be described later, a top gate type thin film transistor (TFT) 30 as a switching element connected in series to the liquid crystal 14 of each pixel is arranged in an array on the quartz substrate 10. It is formed. On the quartz substrate 10, TFTs constituting a liquid crystal drive circuit are also formed. The other substrate 12 is formed of, for example, a glass substrate. A transparent electrode 16 made of ITO (Indium Tin Oxide) is formed on the surface 12a of the glass substrate 12 facing the quartz substrate 10 so as to cover the facing surface 12a, and functions as a common electrode. The counter substrate 12 is not formed with a chrome layer for the black matrix, and this black matrix is disposed only on the quartz substrate 10 side as described later.
[0029]
Next, each layer formed on the quartz substrate 10 will be described with reference to FIGS. FIG. 2 is a perspective view of each layer formed in each pixel region on the quartz substrate 10 and shows a dual gate TFT structure. The quartz substrate 10 mainly includes the above-described TFT 30, a light shielding layer 20 formed between the TFT 30 and the quartz substrate 10, and an insulating layer 22 that insulates the light shielding layer 20 from the TFT 30.
[0030]
As shown in FIGS. 1 and 2, the TFT 30 includes a first polysilicon layer 40 that serves as a source and a drain of a transistor, and a second polysilicon layer 44 that serves as a gate of the transistor. SiO formed between the polysilicon layers 40 and 44 to cover the first polysilicon layer 40.2A gate oxide film 42 is provided. As shown in FIGS. 2 and 3D, a plurality of second polysilicon layers 44 are provided in parallel with the first direction (lateral direction in the figure) of the liquid crystal display panel, and a plurality of scanning signal lines of the liquid crystal display panel are provided. Used as
[0031]
A first interlayer insulating layer 46 is provided to cover the gate oxide film 42 and the second polysilicon layer 44. On top of that, a metal wiring layer 48 made of, for example, aluminum (Al) that functions as a source line of the transistor is provided. The metal wiring layer 48 is connected to the first polysilicon layer 40 through a first contact hole 47 formed in the first interlayer insulating layer 46. As shown in FIGS. 2 and 4B, a plurality of the metal wiring layers 48 are provided in parallel with a second direction (vertical direction in the drawing) perpendicular to the first direction of the liquid crystal display panel. Used as a plurality of data signal lines of a liquid crystal display panel.
[0032]
A second interlayer insulating layer 50 is provided so as to cover the metal wiring layer 48 and the first interlayer insulating layer 46, and a transparent electrode 52 made of, for example, ITO is formed thereon at a position facing each pixel region. The transparent electrode 52 is connected to the first polysilicon layer 40 via the second contact hole 51 formed in the first and second interlayer insulating layers 46 and 50 and functions as a pixel electrode.
[0033]
In this liquid crystal display panel, when an ON voltage equal to or higher than the threshold value of the TFT 30 is applied to the second polysilicon layer 44 corresponding to the scanning signal line in a certain row within the selection period, all the TFTs existing in that row are turned on. At that time, a data signal is supplied to each pixel through a plurality of metal wiring layers 48 corresponding to the data signal lines in each column, and a signal potential is applied to each transparent electrode 52 through each turned-on TFT 30. The In this way, a difference voltage between the common potential of the transparent electrode 16 of the counter substrate 12 and the signal potential of the transparent electrode 52 for each pixel on the quartz substrate 10 side is applied to the liquid crystal 14. Since the TFT 30 is turned off in the non-selection period, the display state is maintained until the next selection period by the voltage charged in the liquid crystal 14 in the selection period. Note that a storage capacitor, which will be described later, is connected in parallel with the liquid crystal 14 in order to improve the voltage holding characteristic during the non-selection period. By repeating this operation for each row, a desired image can be displayed on the liquid crystal display panel.
[0034]
Next, each layer formed on the quartz substrate 10 will be described with reference to the manufacturing steps shown in FIGS. 3 (A) to (D) and FIGS. 4 (A) to (C).
[0035]
<Annealing process>
The quartz substrate 10 at the manufacturing stage has an 8-inch wafer shape. First, the quartz substrate 10 is heated to a temperature equal to or higher than the maximum process temperature of the quartz substrate 10 (this time 1000 ° C. in the thermal oxidation step for the gate oxide film 42), for example, 1000 ° C.2Annealing was performed in a gas atmosphere. By this pretreatment, distortion generated in the quartz substrate 10 during heat treatment at the maximum process temperature to be performed later is previously removed.
[0036]
<The formation process of the light shielding layer 20>
This light shielding layer 20 prevents light reflected from the surface of the quartz substrate 10 from entering the TFT 30. The light shielding layer 20 can prevent the formation of photocarriers in the TFT 30 and can prevent crosstalk due to leakage current.
[0037]
Therefore, as shown in FIG. 1, the light shielding layer 20 is formed over a width wider than that of the first polysilicon layer 40 and is made of a material having sufficient light shielding characteristics. As the required light shielding characteristics of the light shielding layer 20, the OD value is 3 or more, in other words, the transmittance is 1/1000 or less.
[0038]
As the characteristics of the light shielding layer 20, it is necessary to have heat resistance against the maximum process temperature of the liquid crystal display panel in addition to the above light shielding characteristics. In this embodiment, as will be described later, the thermal oxidation step of the gate oxide film 42 is the highest process temperature, for example, 1000 ° C. Therefore, the light shielding layer 20 uses a metal or a metal compound as a material having a melting point of 1000 ° C. or higher which is the maximum process temperature. Examples of this kind of suitable material include silicide-based metals such as tungsten silicide (WSi) and molybdenum silicide (MoSi). This type of silicide-based metal is preferable in that it has good compatibility with the quartz substrate 10 and can have a thermal expansion coefficient close to that of the quartz substrate 10. Thereby, it can prevent that a crack and a crack arise in quartz substrate 10 grade | etc.,.
[0039]
Further, as shown in FIG. 3A, the light shielding layer 20 is formed of a region A facing the TFT 30 and a region B extending in the lateral direction (direction parallel to the scanning signal line). With this arrangement, the black matrix surrounding each pixel can be formed only on the quartz substrate 10 side by the light shielding layer 20 and the metal wiring layer 48 having a light shielding property intersecting with the light shielding layer 20. Thus, unlike the case where the black matrix is configured by the light shielding layer provided on the counter substrate, for example, the chromium layer, the precise alignment between the quartz substrate 10 and the counter substrate 12 is not necessary. Conventionally, it has been necessary to secure a relatively large margin in the line width of the black matrix formation layer in consideration of the positional deviation between the two substrates, but this is not necessary in this embodiment. Therefore, the aperture ratio of the liquid crystal display panel is increased, and a bright display screen can be secured.
[0040]
The light shielding film 20 is formed by sputtering or CVD (chemical vapor deposition), and a photolithography process and an etching process are performed so that only the regions A and B shown in FIG. In addition, when using the light shielding layer 20 as a black matrix like FIG. 3 (A), it is necessary to have sufficient thickness so that the light shielding layer 20 may become black. For this reason, in the case of a silicide metal, the film thickness may be 0.1 μm or more.
[0041]
<Formation process of insulating layer 22>
The insulating layer 22 is for insulating the light shielding layer 20 from the first polysilicon layer 40. This insulating layer 22 is made of, for example, SiO.2For example, it is formed by CVD.
[0042]
<About the potential setting of the light shielding layer 20 and the film thickness of the insulating layer 22>
The light shielding layer 20 has a floating potential when not connected to other wiring. In this case, when the film thickness of the insulating layer 22 is thin, the charge of the light shielding layer 20 adversely affects the switching of the TFT 30 as described above. In order to prevent this, the insulating layer 22 must be formed thick.
[0043]
In this embodiment, a constant DC potential is applied to the light shielding layer 20 in order to realize a normal switching operation depending on only the gate potential in the TFT 30 without depending on the film thickness of the insulating layer 22.
[0044]
In this embodiment, the off potential applied to the gate of the TFT 30 is always applied to the light shielding layer 20. The TFT 30 provided for each pixel is an N-type TFT, and, for example, −1 V is constantly applied to the light shielding layer as an off potential to the gate. In this way, even if the charge of the light shielding layer 20 affects the TFT 30 via the insulating layer 22, the TFT 30 is not erroneously turned on by the charge of the light shielding layer 20. In order to do this, the potential applied to the light shielding layer 20 may be set to a potential lower than the threshold value of the TFT 30. In the case of an N-channel TFT, a ground potential or a negative potential may be used.
[0045]
The off potential is also applied to the light shielding layer provided opposite to the TFT forming the liquid crystal drive circuit. At this time, when both N-type and P-type TFTs are used as transistors used in the liquid crystal drive circuit, different off-potentials are applied to the P and N-type TFTs on the light shielding layer facing them.
[0046]
In this case, since the switching operation of the TFT 30 is not affected by the charge of the light shielding layer 20, the insulating film 22 can be simply insulated from the light shielding layer 20 and the first polysilicon layer 40. If it is. In this case, the thickness of the light shielding layer 20 may be 0.05 μm or more, and may be thinner than the thickness (0.8 μm or more) of the insulating layer 22 required when the light shielding layer 20 is at a floating potential. . The thickness of the insulating layer 22 can be selected from 0.05 to 1.5 μm.
[0047]
In the case of FIG. 3A, the light shielding layer 22 is provided separately from at least the number of scanning signal lines corresponding to the second polysilicon layer 44 that is the scanning signal line. In this case, a scanning signal to the corresponding scanning signal line may be supplied to each light shielding layer 22. Thus, the second polysilicon layer 44 and the light shielding layer 20 which are scanning signal lines are both turned on when the TFT 30 is turned on, and turned off when the TFT 30 is turned off. Disappear.
[0048]
<About the case where the light shielding layer 20 is used as a capacitor line of a storage capacitor>
In addition to the regions A and B shown in FIG. 3A, the light shielding layer 20 can be formed in the region C shown in FIG. This region C is a region opposite to the region in which the first polysilicon layer 40 shown in FIG. Accordingly, the storage capacitor C1 can be configured by the light shielding layer 20 and the first polysilicon layer 40.
[0049]
The first and second polysilicon layers 40 and 44 also constitute a storage capacitor C2. As shown in FIG. 6, the electrical connection relationship between the holding capacitors C1 and C2, the liquid crystal 14 and the TFT 30 is as shown in FIG. Accordingly, the total storage capacity in this case is C1 + C2, and the storage capacity can be increased.
[0050]
Here, the storage capacitor C1 depends on the thickness of the insulating layer 22, and is selected from 0.05 to 1.5 μm, which is a preferable range of the insulating layer 22, to be set to a desired capacitance. it can. The storage capacitor C1 increases as the insulating layer 22 is made thinner. Therefore, when it is desired to secure a large storage capacitor C1, it is preferable to set the light shielding layer 20 to a constant DC potential and make the insulating layer 22 thin as described above.
[0051]
The total storage capacitor C1 + C2 is preferably set with the following width in accordance with the density of pixels formed on the quartz substrate 10. In the case of a VGA (Video Graphics Array) with a pixel density of 640 to 480 dots, it is 20 fF to 200 fF, and in the case of a SVGA (Super Video Graphics Array) with a pixel density of 800 to 600 dots, it is also 20 fF to 200 fF. .
[0052]
<Process for Forming First Polysilicon Layer 40>
After the insulating layer 22 is formed, the monosilane (SiH) is heated while the quartz substrate 10 is heated to about 500 ° C.Four) A gas was supplied at a flow rate of 500 cc / min, and an amorphous silicon (a-Si) deposition film was formed on the quartz substrate 10 at a pressure of 30 Pa. By performing this treatment for about 2 hours, an a-Si film having a thickness of 0.055 μm was formed.
[0053]
After this, N2Annealing treatment was performed at 640 ° C. for about 6 hours in an atmosphere, and a polysilicon film was formed by solid phase growth. There is also a method of forming a polysilicon layer by CVD, but this makes the grain size fine. In this embodiment, since the grain is solid-phase grown from a-Si to form polysilicon, the grain size is large, and the formed polysilicon layer is close to the characteristics of a single crystal. It is improving.
[0054]
Thereafter, the first polysilicon layer 40 having the pattern shown in FIG. 3B is formed by performing a photolithography process, an etching process, and the like.
[0055]
The film thickness of the first polysilicon layer 40 is reduced by the subsequent thermal oxidation process, but the final film thickness is preferably 0.02 to 0.15 μm. Below this lower limit, the resistance of the first polysilicon layer 40 becomes too large, and there is a risk that the on-current cannot be secured. Since this on-current flows in a predetermined thickness region on the MOS interface side, the leakage current increases when the thickness exceeds this value, so it is preferable not to exceed the upper limit of the above range.
[0056]
<Step of Forming Gate Oxide Film 42>
(1) Formation of thermal oxide film
First, the first polysilicon layer 40 was thermally oxidized for 30 minutes in an atmosphere of 1000 ° C. and 100% dry oxygen. At this time, the 0.055 μm first polysilicon layer 40 becomes 0.04 μm, and a 0.03 μm thermal oxide film (SiO 2).2) 42a was formed on the first polysilicon layer 40.
[0057]
FIG. 7 shows the relationship between the thermal oxidation time and the thermal oxide film thickness, and FIG. 8 shows the relationship between the thermal oxide film thickness and the warp occurring in the 8-inch quartz substrate 10. As shown in FIG. 8, the thermal oxidation temperature has an upper limit of 1050 ° C. at which the warpage of the 8-inch quartz substrate 10 is 100 μm or less. As is apparent from FIG. 8, the warp of the quartz substrate 10 cannot be suppressed to 100 μm or less when the thermal oxidation temperature exceeds 1100 ° C. and 1150 ° C.
[0058]
Further, even if the thermal oxidation is performed at 1050 ° C. or less, if the thermal oxidation time is long, in other words, if the thermal oxide film 42a is thick, the warp of the quartz substrate 10 cannot be suppressed to 100 μm or less. According to FIG. 8, when the thermal oxidation temperature is 1050 ° C. or less, the thermal oxide film thickness is approximately 0.1 μm or less, and the warpage of the quartz substrate 10 can be suppressed to 100 μm or less. However, it is preferable that the thermal oxide film thickness is further thinner due to other factors described below.
[0059]
FIGS. 9A to 9F schematically show electron micrographs of the MOS interface after thermal oxidation, and show roughness (unevenness) of the MOS interface at each thermal oxidation temperature. As can be seen from the figure, the roughness of the MOS interface is smaller as the thermal oxidation temperature is higher. In this sense, the higher the thermal oxidation temperature, the better. However, in consideration of the warp of the quartz substrate 10, it is necessary to set it to 1050 ° C. or lower.
[0060]
According to the present inventors, it has been found that the above-mentioned roughness of the MOS interface becomes more prominent as the thermal oxidation time becomes longer, in other words, as the thermal oxide film thickness increases. Then, the roughening of the MOS interface causes a portion of the thermal oxide film 42a on which the film density becomes rough to cause a current to flow intensively, and the withstand voltage of the thermal oxide film 42a is lowered. .
[0061]
Considering these, the thickness of the thermal oxide film 42a is preferably 0.015 to 0.05 μm, more preferably 0.02 to 0.035 μm. The lower limit of the thickness of the thermal oxide film 42a is determined from the point that if it is thinner than that, it becomes difficult to form the interface itself. The upper limit is determined from the viewpoint of ensuring the withstand voltage in view of the relationship between the warp of the substrate and the temperature.
[0062]
(2) Formation of CVD oxide film
By forming the thermal oxide film 42a, a MOS interface with relatively little roughness can be formed. However, this alone cannot secure a sufficient withstand voltage. Therefore, in this embodiment, the uneven thermal oxide film 42a reflecting the roughness of the MOS interface is formed by SiO having a high step coverage capability.2It is covered with a film 42b. The CVD oxide film 42b is formed on the entire surface of the quartz substrate 10 as shown in FIG. This eliminates the need for a photolithography process, an etching process, and the like for patterning. In addition, a step formed on the surface of the second interlayer insulating film 50 and the transparent electrode 52 which is the uppermost layer of the quartz substrate 10 by forming the CVD oxide film 42b at a position other than the thermal oxide film 42a shown in FIG. Can be reduced. For this reason, the rubbing process for liquid crystal alignment becomes easy, and it becomes easy to suppress the cell gap between the substrates 10 and 12 within a desired dimensional accuracy.
[0063]
The CVD oxide film 42b is formed of a gas containing silicon such as monosilane (SiHFour) And oxygen-containing gas such as nitrogen peroxide (N2O), for example, in an oxygen-excess atmosphere with a flow ratio of 1:50, SiO 2 by the HTO method.2The film was vapor grown. In an excess silicon atmosphere, the CVD oxide film 42b has an electric charge, which is not preferable. The pressure at this time was 80 Pa. The upper limit of the film formation temperature is 1050 ° C., which is the same as the thermal oxidation temperature, and preferably 600 to 1000 ° C. The upper limit is for setting the warp of the quartz substrate 10 to 100 μm or less, and the lower limit is determined from the viewpoint of securing the film quality of the CVD film 42b. The film forming temperature is more preferably 700 to 900 ° C., and further preferably 750 to 850 ° C. in order to secure a step coverage of 0.7 or more as shown in FIG. The pressure is preferably 300 pa or less. As shown in FIG. 11, the pressure is set to 200 Pa or less in order to secure a step coverage of 0.7 or more. Although there is no restriction | limiting in particular about the minimum of a pressure, as shown in FIG. 11, it has confirmed that a high step coverage was obtained at the pressure of 40 Pa. Further, a gas containing silicon such as monosilane (SiHFour) Gas containing oxygen, such as nitrogen peroxide (N2O) flow rate ratio (N2O / SiHFour) Is set to 25 to 75 from the viewpoint of achieving uniformity within the quartz substrate 10 surface of 10% or less as shown in FIG. 12, and to be set to 40 to 60 for achieving in-plane uniformity of 5% or less. .
[0064]
The film thickness of the CVD oxide film 42b is preferably 0.02 μm or more. This value is obtained from the viewpoint of securing the gate breakdown voltage, and the step coverage improves as the film thickness increases. The thickness of the CVD oxide film 42b can be determined in consideration of the total film thickness of the gate oxide film 42 composed of the CVD oxide film 42b and the thermal oxide film 42a. The thickness of the gate oxide film 42 also affects the size of the storage capacitor C2 formed by the first and second polysilicon layers 40 and 44. As the thickness of the gate oxide film 42 is reduced, the storage capacitor C2 can be increased. From the viewpoint of securing the storage capacitor C2, the thickness of the gate oxide film 42 is preferably 0.05 to 0.12 μm.
[0065]
Therefore, in order to obtain this total film thickness, considering that the thickness of the thermal oxide film 42a is 0.015 to 0.05 .mu.m, the film thickness of the CVD oxide film 42b is 0.03 to 0.03 mm. A range of 1 μm is sufficient. As described above, when the thickness of the thermal oxide film 42a is 0.02 to 0.035 μm, the thickness of the CVD oxide film 42b is sufficient in the range of 0.05 to 0.09 μm.
[0066]
This CVD oxide film 42b is then annealed. Inert gas, eg N2Annealing was performed in an atmosphere at a temperature in the range of 600 to 1000 ° C., for example, 950 ° C. for 30 minutes. As a result, defects in the CVD oxide film 42b can be rearranged and the fixed charge can be released. The above temperature range is necessary to escape the fixed charge.
[0067]
<Capacitance Formation Process on First Polysilicon Layer 40>
The region D of FIG. 3C is masked, and an impurity such as phosphorus is dosed to a region where the capacitance of the first polysilicon layer 40 other than that is to be made, for example 3 × 1014/ CmThreeThe first polysilicon layer 40 in that portion was reduced in resistance. The dose amount is 1.0 × 1014~ 2.0 × 1015/ CmThreeIt is preferable that The lower limit is determined from the viewpoint of securing the conductivity necessary for forming a capacitance in the first polysilicon layer 40, and more preferably 3.0 × 10.14/ CmThreeIf it is more, the resistance is sufficiently lowered. The upper limit is required from the viewpoint of suppressing deterioration of the gate oxide film 42.
[0068]
<Step of Forming Second Polysilicon Layer 44>
Next, a second polysilicon layer is formed on the entire surface, and an impurity such as phosphorus is doped to reduce the resistance. Thereafter, a gate electrode is formed by the second polysilicon layer 44 patterned as shown in FIG. 3D by performing a photolithography process and an etching process. In this embodiment, the gate electrode 44 intersects the polysilicon layer 40 twice and has a dual gate structure. With the dual gate structure, leakage current at the time of off can be reduced. Instead of the dual gate, a single gate that intersects the polysilicon layer 40 once may be used.
[0069]
<Implantation process of impurities for transistor formation>
First, in order to form an N-type transistor, impurity phosphorus is added to the source and drain regions in the region D in FIG. 3D using the second polysilicon layer 44 serving as a gate as a mask.13/ CmThreeLight dope with a dose of Further, a mask wider than the gate width is formed over the gate, and impurity boron is added to the source region in FIG.15/ CmThreeThe second implantation is carried out at a dose of 5% and high doping is performed. Thereby, the masked region becomes a light-doped drain. The dose amount during the second implantation is preferably 1.0 × 1012~ 1.0 × 1014/ CmThreeAnd good. Below the lower limit, the resistance increases and the on-current decreases. When the upper limit is exceeded, leakage current easily flows. In this embodiment, an LDD structure having a low concentration region and a high concentration region in the source / drain region is used. However, the present invention is not limited to the LDD structure, and the source / drain region is separated from the gate electrode. An offset structure may be used. Alternatively, a self-aligned structure in which source / drain regions are formed using a gate electrode as a mask may be used. By using the LDD structure or the offset structure, the leakage current at the time of off can be reduced. Therefore, by using together with the above-described dual gate structure, the leakage current at the time of OFF is further reduced.
[0070]
Similarly, an N-type transistor used as a liquid crystal driver circuit is also formed on the quartz substrate 10. The P-type transistor of the liquid crystal driver is similarly formed, that is, boron is 1.0 × 10 6 using the gate electrode as a mask.13/ CmThreeLight dope with a dose of Thereafter, a mask wider than the gate electrode is formed by starvation of the gate electrode, and phosphorus is added at 1.0 × 10 6.15/ CmThreeThe LDD structure is formed by implanting at a dose of.
[0071]
<Process for Forming First Interlayer Insulating Layer 46>
Next, a first interlayer insulating layer 46 is formed. This was formed with a film thickness of 0.08 μm by CVD under the conditions of 140 cc / min, substrate temperature of 680 ° C., and pressure of 50 Pa for TEOS (tetraethyl osol silicate). Thereafter, annealing was performed at 950 ° C. for 20 minutes to activate the impurities in the first interlayer insulating layer 46 to improve the film quality. Then, for example, it heated at 500 degreeC for 1 hour using the forming gas which consists of argon and hydrogen. As a result, hydrogen was contained in the first polysilicon layer 40 and the silicon unbonded portion was bonded to reduce the level in the gap, thereby improving the characteristics of the TFT 30.
[0072]
Further, a first contact hole 47 was formed at the position shown in FIG. 4A by performing a photolithography process and an etching process. As an etching step, wet etching was performed after dry etching, and light etching for exposing the first polysilicon layer 40 was performed.
[0073]
<Formation process of metal wiring layer 48>
By sputtering aluminum (Al) and then performing patterning, a metal wiring layer 48 was formed as shown in FIG. At this time, the metal wiring layer 48 is connected to the first polysilicon layer 40 through the first contact hole 47. The metal wiring layer 48 is not limited to Al but may be any material having conductivity such as Cr.
[0074]
<The formation process of the 2nd interlayer insulation layer 50>
The second interlayer insulating layer 50 is made of SiO containing boron and phosphorus.2(BPSG) was formed by atmospheric pressure CVD. As process gases, TEOS, TEB (tetraethyl borate), and TMOP (tetramethyloxyphosphate) were used. Thereafter, the second contact hole 51 was formed at the position shown in FIG. 4C by performing the same process as the first contact hole 47. When the aspect ratio of the second contact hole 51 is large and it is difficult to control the etching stop within the thickness range of the first polysilicon layer 40, for example, polysilicon is formed under the first polysilicon layer 40. A sheet or the like may be formed in advance.
[0075]
<Process for forming transparent electrode 52>
On the second interlayer insulating layer 50, ITO (indium tin oxide) was sputtered and then patterned to form a transparent electrode 52 as shown in FIG.
[0076]
In the above-described embodiments, the switching element is a TFT, but the present invention can be similarly applied to a liquid crystal display panel using a back-to-back diode in which photocarriers are generated by reflected light.
[0077]
<Description of LCD panel>
FIG. 13 shows a system configuration example of a substrate on which TFTs are formed in the liquid crystal panel of the above embodiment. Each pixel 190 arranged corresponding to the intersection of the gate line 102 and the signal line 103 arranged so as to cross each other is composed of a pixel electrode 114 made of ITO or the like and a TFT 191. The TFT 191 applies a voltage corresponding to the pixel signal on the signal line 103 to the pixel electrode 114. The TFTs 191 in the same row (Y direction) have their gates connected to the same gate line 102 and their drains connected to corresponding pixel electrodes 114. The sources of the TFTs 191 in the same column (X direction) are connected to the same signal line 103. In this embodiment, the transistors constituting the peripheral circuits (X and Y shift registers and sampling means) 150 and 160 are constituted by polysilicon TFTs having a polysilicon layer as an operation layer, similar to TFTs for driving pixels. The transistors forming the peripheral circuits 150 and 160 are simultaneously formed by the same process together with the pixel driving TFT.
[0078]
In this embodiment, a shift register (hereinafter referred to as an X shift register) 151 for sequentially selecting the signal lines 103 is arranged on one side (upper side in FIG. 13) of the display area (pixel matrix) 120, and the other of the pixel matrix. On one side, a shift register (hereinafter referred to as a Y shift register) 161 for sequentially selecting the gate lines 102 is provided. Further, a buffer 163 is provided in the next stage of the Y shift register 161 as necessary. A sampling switch (TFT) 152 is provided at the other end of the signal line 103, and these sampling switches 152 transmit the image signals VID1 to VID3 input to the external terminals 174, 175, and 176. The video lines 154, 155, and 156 are connected to the signal line 103, and are sequentially turned on / off by a sampling pulse output from the X shift register 151. The X shift register 151 selects all the signal lines 103 one by one in order during one horizontal scanning period based on clocks CLX1 and CLX2 input from the outside via terminals 172 and 173. , X2, X3,... Xn are supplied to the control terminal of the sampling switch 152. On the other hand, the Y shift register 161 is operated in synchronization with clocks CLY1 and CLY2 input from the outside via terminals 177 and 178, and sequentially drives the gate lines 102.
[0079]
14A and 14B show a cross section and a planar layout configuration of a liquid crystal panel 130 to which the liquid crystal panel is applied. As shown in the figure, on the surface side of the liquid crystal panel substrate 110, an incident side glass substrate (counter substrate) having a counter electrode 133 made of a transparent film electrode (ITO) to which a common electrode potential is applied and a color filter layer 113 is provided. ) 131 is disposed at an appropriate interval, and a TN (Twisted Nematic) type liquid crystal or SH (Super Homeotropic) type liquid crystal 137 is filled in a gap sealed around with a sealing material 136. It is comprised as 130. Further, the peripheral circuits 150 and 160 are configured to be shielded from light by, for example, black matrix or the like provided on the counter substrate 131. Note that the counter substrate 131 is provided with a liquid crystal injection port 138.
[0080]
<Description of electronic equipment>
An electronic device configured using the liquid crystal display panel of the above-described embodiment includes a display information output source 1000, a display information processing circuit 1002, a display drive circuit 1004, a display panel 1006 such as a liquid crystal panel, and a clock generation circuit shown in FIG. 1008 and the power supply circuit 1010 are comprised. The display information output source 1000 is configured to include a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs a television signal, and outputs display information such as a video signal based on the clock from the clock generation circuit 1008. To do. The display information processing circuit 1002 processes display information based on the clock from the clock generation circuit 1008 and outputs it. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 to display. The power supply circuit 1010 supplies power to each of the circuits described above.
[0081]
As an electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 16, a personal computer (PC) and an engineering workstation (EWS) corresponding to multimedia shown in FIG. 17, a pager shown in FIG. 18, a mobile phone, a word processor, Examples include a television, a viewfinder type or a monitor direct view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.
[0082]
The liquid crystal projector shown in FIG. 16 is a projection type projector using a transmissive liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system. In FIG. 16, in the projector 1100, the projection light emitted from the lamp unit 1102 of the white light source is divided into the three primary colors R, G, and B by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside the light guide 1104. Are guided to the three liquid crystal panels 1110R, 1110G, and 1110B that display images of the respective colors. The light modulated by the respective liquid crystal panels 1110R, 1110G, and 1110B is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, the red R and blue B lights are bent by 90 °, and the green G light travels straight, so that images of the respective colors are synthesized, and a color image is projected onto a screen or the like through the projection lens 1114.
[0083]
A personal computer 1200 illustrated in FIG. 17 includes a main body 1204 including a keyboard 1202 and a liquid crystal display screen 1206.
[0084]
A pager 1300 shown in FIG. 18 includes a liquid crystal display panel 1304, a light guide 1306 having a backlight 1306a, a circuit board 1308, first and second shield plates 1310 and 1312, and two elastic conductors in a metal frame 1302. It has a body 1314, 1316 and a film carrier tape 1318. The two elastic conductors 1314 and 1316 and the film carrier tape 1318 connect the liquid crystal display panel 1304 and the circuit board 1308.
[0085]
Here, the liquid crystal display panel 1304 is obtained by enclosing liquid crystal between two transparent substrates 1304a and 1304b, and at least a dot matrix type liquid crystal display panel is configured. A driving circuit 1004 shown in FIG. 15 or a display information processing circuit 1002 can be formed on one transparent substrate. Circuits that are not mounted on the liquid crystal display panel 1304 are external circuits, and can be mounted on the circuit board 1308 in the case of FIG.
[0086]
FIG. 18 shows the structure of the pager, so that a circuit board 1308 is required in addition to the liquid crystal display panel 1304. A structure in which the liquid crystal display panel 1304 is fixed to a metal frame 1302 as a housing is used for an electronic device. It can also be used as a liquid crystal display device as a component. Further, in the case of the backlight type, a liquid crystal display device can be configured by incorporating a liquid crystal display panel 1304 and a light guide 1306 provided with a backlight 1306a in a metal frame 1302. Instead, as shown in FIG. 19, a TCP in which an IC chip 1324 is mounted on a polyimide tape 1322 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting a liquid crystal display panel 1304. (Tape Carrier Package) 1320 can be connected to be used as a liquid crystal display device which is one component for electronic equipment.
[0087]
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view of a liquid crystal display panel of the present invention.
2 is a perspective view of each layer formed on a quartz substrate of the liquid crystal display panel of FIG. 1. FIG.
FIGS. 3A to 3D are process diagrams in the order of the manufacturing process of each layer formed on a quartz substrate. FIGS.
4 (A) to 4 (C) are process diagrams in the order of the manufacturing process of each layer formed on the quartz substrate following FIG. 3 (D).
FIG. 5 is a plan view showing a formation pattern of the light shielding layer when the light shielding layer is used as a capacitor line of a storage capacitor connected in parallel to the liquid crystal.
FIG. 6 is a circuit diagram showing an electrical connection relationship among a switching element, a liquid crystal, and a storage capacitor.
FIG. 7 is a characteristic diagram showing the relationship between thermal oxidation time and thermal oxide film thickness.
FIG. 8 is a characteristic diagram showing a relationship between a thermal oxide film thickness and a warp occurring in an 8-inch quartz substrate.
FIG. 9A to FIG. 9F are characteristic diagrams schematically showing electron micrographs showing the rough state of the MOS interface for each thermal oxide film temperature.
FIG. 10 is a characteristic diagram showing temperature dependence characteristics of step coverage of a CVD oxide film constituting a gate oxide film.
FIG. 11 is a characteristic diagram showing pressure-dependent characteristics of step coverage of a CVD oxide film constituting a gate oxide film.
FIG. 12 is a characteristic diagram showing a flow ratio dependence characteristic of uniformity in a substrate surface of a CVD oxide film constituting a gate oxide film.
13 is a schematic explanatory view showing a TFT and a drive circuit formed on the quartz substrate side shown in FIG. 1. FIG.
14A is a cross-sectional view of the entire liquid crystal panel shown in FIG. 1, and FIG. 14B is a diagram showing a planar layout thereof.
FIG. 15 is a block diagram of an electronic apparatus according to the invention.
FIG. 16 is a schematic explanatory diagram of a projector to which the present invention is applied.
FIG. 17 is an external view of a personal computer to which the present invention is applied.
FIG. 18 is an exploded perspective view of a pager to which the present invention is applied.
FIG. 19 is a schematic explanatory diagram illustrating an example of a liquid crystal display panel including an external circuit.
[Explanation of symbols]
10 Quartz substrate
12 Glass substrate
14 Liquid crystal
16 Common electrode (ITO)
20 Shading layer
22 Insulating layer
30 Thin film transistor
40 First polysilicon layer (source, drain)
42 Gate oxide film
42a Thermal oxide film
42b CVD oxide film
44 Second polysilicon layer (gate, scanning signal line)
46 First interlayer insulating layer
47 First contact hole
48 Metal wiring layer (data signal line)
50 Second interlayer insulating layer
51 Second contact hole
52 Pixel electrode (ITO)

Claims (9)

  1. A liquid crystal is sealed between a pair of substrates, and a switching element that supplies an image signal to a pixel electrode based on a scanning signal is connected between the switching element and the pixel electrode on one substrate. In a liquid crystal display panel having a storage capacitor,
    The switching element has a source, a first polysilicon layer serving as a drain, and a second polysilicon layer serving as a gate electrode, provided on a lower layer of the first polysilicon layer and the upper layer of the second polysilicon layers gate Formed by a top-gate thin film transistor having an insulating film,
    A light shielding layer and an insulating layer that insulates the light shielding layer and the first polysilicon layer are provided between the one substrate and the first polysilicon layer of the thin film transistor,
    The drain side of the first polysilicon layer is extended between two adjacent pixel electrodes, the extension is used as one electrode of the storage capacitor, and the second polysilicon layer is used as one of the storage capacitors. The other electrode of the storage capacitor is disposed to face the electrode of
    The light shielding layer extends in a direction intersecting with a data signal line for supplying the image signal to the source of the thin film transistor, and is formed in a lower layer of the storage capacitor to be wider than an electrode width of the storage capacitor; and The light shielding layer is also used as a capacity line of the storage capacitor,
    Wherein in a layer between the pixel electrode and the thin film transistor, liquid crystal display panel, wherein a pre-provided Kide data signal line.
  2. In claim 1,
    A liquid crystal display panel, wherein a scanning signal is supplied to the light shielding layer.
  3. In claim 1 or 2,
    A liquid crystal display panel, wherein a thin film transistor for liquid crystal driver is formed on the one substrate, and the light shielding layer is also disposed in a region facing the thin film transistor for liquid crystal driver.
  4. In any one of Claims 1 thru | or 3,
    A liquid crystal display panel, wherein the insulating layer has a thickness of 0.05 to 1.5 μm.
  5. In any one of Claims 1 thru | or 4 ,
    A plurality of the light shielding layers are arranged in a direction orthogonal to the plurality of light shielding data signal lines formed on the one substrate, and the data signal lines and the light shielding layers constitute a black matrix. LCD panel to be used.
  6. In claim 5 ,
    A liquid crystal display panel, wherein a light shielding layer is not formed on the other substrate of the pair of substrates facing the one substrate.
  7. In any one of Claims 1 thru | or 6 .
    The liquid crystal display panel according to claim 1, wherein the one substrate is a quartz substrate, and the light shielding layer is a silicide metal.
  8. An electronic apparatus comprising the liquid crystal display panel according to any one of claims 1 to 7.
  9. In a substrate having a switching element that supplies an image signal to a pixel electrode based on a scanning signal, and a storage capacitor connected between the switching element and the pixel electrode,
    The switching element has a source, a first polysilicon layer serving as a drain, and a second polysilicon layer serving as a gate electrode, provided on a lower layer of the first polysilicon layer and the upper layer of the second polysilicon layers gate Formed by a top-gate thin film transistor having an insulating film,
    A light shielding layer and an insulating layer that insulates the light shielding layer and the first polysilicon layer are provided between the one substrate and the first polysilicon layer of the thin film transistor,
    The drain side of the first polysilicon layer is extended between two adjacent pixel electrodes, the extension is used as one electrode of the storage capacitor, and the second polysilicon layer is used as one of the storage capacitors. The other electrode of the storage capacitor is disposed to face the electrode of
    The light shielding layer extends in a direction intersecting with a data signal line connected to the source, and is formed in a lower layer of the storage capacitor so as to be wider than an electrode width of the storage capacitor, and the light shielding layer is formed of the storage capacitor. Is also used as a capacity line
    A substrate having a switching element, wherein said in a layer between the pixel electrode and the thin film transistor, the pre-provided Kide data signal line.
JP28302596A 1996-10-04 1996-10-04 Substrate provided with switching element, liquid crystal display panel, and electronic apparatus using the same Expired - Fee Related JP3830213B2 (en)

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JP28302596A JP3830213B2 (en) 1996-10-04 1996-10-04 Substrate provided with switching element, liquid crystal display panel, and electronic apparatus using the same

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US8158980B2 (en) 2001-04-19 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
TW468269B (en) * 1999-01-28 2001-12-11 Semiconductor Energy Lab Serial-to-parallel conversion circuit, and semiconductor display device employing the same
TW478014B (en) 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
JP4341062B2 (en) 2003-02-12 2009-10-07 日本電気株式会社 Thin film transistor and manufacturing method thereof
JP2005197618A (en) 2004-01-09 2005-07-21 Nec Corp Thin film transistor, formation method and display device thereof, and electronic equipment
JP5458367B2 (en) 2007-07-09 2014-04-02 Nltテクノロジー株式会社 Thin film transistor and manufacturing method thereof
WO2010089831A1 (en) 2009-02-05 2010-08-12 シャープ株式会社 Semiconductor device and method for producing the same
CN102646595A (en) * 2011-11-11 2012-08-22 京东方科技集团股份有限公司 Thin film transistor, manufacturing method and display device thereof

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