CN205789970U - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- CN205789970U CN205789970U CN201620391571.7U CN201620391571U CN205789970U CN 205789970 U CN205789970 U CN 205789970U CN 201620391571 U CN201620391571 U CN 201620391571U CN 205789970 U CN205789970 U CN 205789970U
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Abstract
A kind of thin-film transistor array base-plate, it is characterised in that including: substrate；It is positioned at the active layer on described substrate, grid, source electrode and drain electrode, described active layer is made up of channel region, source area and drain region, described source electrode and described drain electrode are positioned at described active layer and deviate from the side of substrate, described source area, drain region respectively with described source electrode and described drain contact；It is positioned at described active layer and deviates from the photoresistance of described substrate side, for stopping that light deviates from substrate side from described active layer and is irradiated to described channel region, described photoresistance is lighttight positivity photoresistance or negativity photoresistance, and described channel region falls at described photoresistance in the drop shadow spread of described substrate in the projection of described substrate.Utilize photoresistance to block the light irradiated to active layer channel region, effectively prevent channel region from causing leakage current because the irradiation of ambient produces photo-generated carrier.
Description
Technical field
This utility model relates to Display Technique field, especially relates to a kind of thin-film transistor array base-plate and display surface thereof
Plate and display device.
Background technology
Along with the development of Display Technique, the demand of display device is continuously increased by user, TFT-LCD (Thin Film
Transistor-Liquid Crystal Display, TFT liquid crystal display) at mobile phone, liquid crystal display
The product such as device, panel computer is widely used.
But, due to TFT structure not complete shading in actual production, it is in pass for be exposed under illumination condition
The TFT structure of disconnected state, light note causes the channel region of thin film transistor (TFT) to absorb outside light energy and cause transition, formation
Electron-hole pair causes leakage current to increase under source and drain electric field action, thus affects the steady operation of TFT.
Low temperature polycrystalline silicon (Low temperature poly-silicon, LTPS) thin film transistor (TFT) battle array such as Fig. 1 a, 1b
The sectional view of row substrate, array base palte includes glass substrate 1, light shield layer 2, cushion 3, gate insulator 4, active layer 5, grid
61, source electrode 62, drain electrode 63, interlayer insulating film 7, planarization layer 8, pixel electrode 81, public electrode 82, passivation layer 9, wherein, have
Active layer includes channel region 51, source area 52, drain region 53, and channel region 51 also includes main channel region 511 and transition region 512, transition
District 512 is between main channel region 511 and drain region 53 or between main channel region 511 and source area 52.Light shield layer can by from
The light barrier of backlight, is allowed to be irradiated to the channel region of active layer.Active layer 5 is also had certain by source electrode 62, drain electrode 63
Block, part can be blocked by external irradiation to source area 52, the light of drain region 53.But it is middle with drain electrode 63 to be in source electrode 62
Do not have can be with the structure of shading or film layer in channel region 51 (especially transition region 512) top.When ambient is through top
Pixel electrode 81, public electrode 82, planarization layer 7, passivation layer 9 enter channel region 51, or from the lateral or light of lower section
When superrefraction reflected illumination is to channel region 51 so that the quasiconductor of channel region produces electron-hole pair, thus produces electric leakage
Stream, when thin film transistor (TFT) is in OFF state, leakage current causes the voltage drop of the display unit of current loss sum on conducting wire, leads
Cause display bad.
Such as the sectional view of non-crystalline silicon (Amorphous silicon, the a-Si) thin-film transistor array base-plate of Fig. 2 a, 2b,
Array base palte includes substrate 20, grid 21, gate insulator 22, active layer 23, source electrode 24, drain electrode 25, passivation layer 26, source electrode 24
With the active layer 23 of 25 covering parts that drain, transparent etching barrier layer 27 is positioned at active layer and deviates from the surface of substrate 20 side,
And its area is less than active layer.But there is no light-shielding structure or film layer above the active layer of remainder.When ambient is through having
Passivation layer above active layer enters channel region, or from the light of lateral or lower section through superrefraction reflected illumination to channel region
Time so that the quasiconductor of channel region produces electron-hole pair, thus produces leakage current, causes the loss of electric current and voltage, causes
Show bad.
Utility model content
The problem resulting in leakage current in view of the above above active layer without light shield layer, this utility model provides
A kind of thin-film transistor array base-plate, including: substrate；It is positioned at the active layer on described substrate, grid, source electrode and drain electrode, described
Active layer is made up of channel region, source area and drain region, and described source electrode and described drain electrode are positioned at described active layer and deviate from substrate
Side, described source area, drain region respectively with described source electrode and described drain contact；It is positioned at described active layer and deviates from described substrate
The photoresistance of side, is used for stopping that light deviates from substrate side from described active layer and is irradiated to described channel region, described photoresistance is
Lighttight positivity photoresistance or negativity photoresistance, and described channel region falls at described photoresistance at described substrate in the projection of described substrate
Drop shadow spread in.
This utility model also provides for:
A kind of display floater includes above-described thin-film transistor array base-plate；
A kind of display device, including above-described display floater.
Active layer is low-temperature polysilicon silicon semiconductor or amorphous silicon semiconductor.Photoresistance is positivity photoresistance or negativity photoresistance, has
The effect of shading, photoresistance at least blocks the light irradiated to active layer channel region, effectively prevents channel region because of the photograph of ambient
Penetrate generation photo-generated carrier, thus produce leakage current.Further, photoresistance is organic insulator, will not with close metal level, partly lead
Producing parasitic capacitance between body layer, also will not be short-circuited phenomenon, affects little on the electric property of device.It addition, the system of photoresistance
Make technique can share the mask plate of other film layers, simplify processing technology.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model or technical scheme of the prior art, below will be to embodiment or existing
In technology description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this reality
By some novel embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, also may be used
To obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 a is the sectional view of low-temperature polysilicon film transistor array base palte in prior art；
Fig. 1 b is the top view of low-temperature polysilicon film transistor array base palte in prior art；
Fig. 2 a is the sectional view of amorphous silicon film transistor array base palte in prior art；
Fig. 2 b is the top view of amorphous silicon film transistor array base palte in prior art；
The sectional view of the low-temperature polysilicon film transistor array base palte that Fig. 3 a provides for this utility model；
The top view of the low-temperature polysilicon film transistor array base palte that Fig. 3 b provides for this utility model；
Photoresistance correspondence light shield layer in the low-temperature polysilicon film transistor array base palte that Fig. 4 a provides for this utility model
Sectional view；
Photoresistance correspondence light shield layer in the low-temperature polysilicon film transistor array base palte that Fig. 4 b provides for this utility model
Top view；
Photoresistance correspondence active layer in the low-temperature polysilicon film transistor array base palte that Fig. 5 a provides for this utility model
Sectional view；
Photoresistance correspondence active layer in the low-temperature polysilicon film transistor array base palte that Fig. 5 b provides for this utility model
Top view；
Fig. 6 makes the vertical view of the array base palte of photoresistance for the mask plate (Mask4) using grid that this utility model provides
Figure；
The cross section structure figure of the amorphous silicon film transistor array base palte that Fig. 7 a provides for this utility model；
The top view of the amorphous silicon film transistor array base palte that Fig. 7 b provides for this utility model；
In the amorphous silicon film transistor array base palte that Fig. 8 provides for this utility model, photoresistance substitutes cutting of etching barrier layer
Face figure；
Cut corresponding with active layer of photoresistance in the amorphous silicon film transistor array base palte that Fig. 9 a provides for this utility model
Face figure；
Bow corresponding with active layer of photoresistance in the amorphous silicon film transistor array base palte that Fig. 9 b provides for this utility model
View；
The cross section that in the amorphous silicon film transistor array base palte that Figure 10 a provides for this utility model, photoresistance is corresponding with grid
Figure；
The vertical view that in the amorphous silicon film transistor array base palte that Figure 10 b provides for this utility model, photoresistance is corresponding with grid
Figure.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole
Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under making creative work premise
The every other embodiment obtained, broadly falls into the scope of this utility model protection.
Elaborate a lot of detail in the following description so that fully understanding this utility model, but this practicality is new
Type can also use other to be different from alternate manner described here to implement, and those skilled in the art can be without prejudice to this reality
Doing similar popularization in the case of novel intension, therefore this utility model is not limited by following public specific embodiment.
In the thin-film transistor array base-plate that the embodiment of the present invention provides, grid is positioned at active layer and deviates from the one of described substrate
Side, thin-film transistor array base-plate also includes: being positioned at active layer and deviate from the gate insulator of substrate side, gate insulator covers
Active layer, grid is positioned at gate insulator and deviates from substrate side；Channel region also includes transition region, and transition region is positioned at channel region and source
Between polar region, or, transition region is between channel region and drain region；It is positioned at gate insulator and deviates from the layer insulation of substrate side
Layer, interlayer insulating film covers grid；Photoresistance is positioned at interlayer insulating film and deviates from the surface of substrate side.
Optionally, thin-film transistor array base-plate also includes lower light shield layer, lower light shield layer between substrate and active layer,
Channel region falls at lower light shield layer in the drop shadow spread of described substrate in the projection of substrate, photoresistance described substrate projection with under
Light shield layer overlaps in the projection of substrate.
Optionally, channel region overlaps in the projection of substrate with photoresistance in the projection of substrate.
The cross section structure figure of the low-temperature polysilicon film transistor array base palte that Fig. 3 a, 3b provide for this utility model with bow
View.
Low-temperature polysilicon film transistor array base palte includes substrate 31, the light shield layer 32 that is sequentially located on substrate, buffering
Layer 33, active layer 35 (including channel region 351, source area 352, drain region 353), gate insulator 34, grid 361, interlayer are exhausted
Edge layer 37, photoresistance 300, planarization layer 38, public electrode 382, pixel electrode 381, passivation layer 39.Cushion 33 covers light shield layer
32, gate insulator 34 is coated with active layer 35.Source electrode 362, drain electrode 363 are positioned at interlayer insulating film 37 surface, and are divided by via
Do not electrically connect with source area 352, drain region 353.Active layer includes channel region 351, source area 352, drain region 353, channel region
Being positioned at active layer 35 and the overlapping region of grid 361, channel region 351 also includes main channel region 3511 and transition region 3512, transition
District 3512 is between main channel region 3511 and drain region 353 or between main channel region 3511 and source area 352.Active layer is at base
The projection of plate 31 falls at light shield layer 32 in the drop shadow spread of substrate 31, and grid 361 is at projection and the main channel region 351 of substrate 31
Projection at substrate 31 overlaps.
Light barrier from backlight can be allowed to be irradiated to the channel region 351 of active layer by light shield layer 32.Source electrode
362, drain electrode 363 also has certain blocking to active layer 35, can block part by external irradiation to source area 352, drain region 353
Light.
In whole active layer 35, the transition region 3512 in channel region 351 is most susceptible to the effect of light, produces electricity
Son-hole pair, thus produce leakage current, light irradiates the leakage current caused the most mainly the photo-generate electron-hole of transition region
To cause.
Photoresistance 300 is positioned at interlayer insulating film 37 surface, its at projection and the channel region 351 of substrate 31 in the projection of substrate 31
Overlapping, photoresistance 300 just can hide main channel region 3511 and transition region 3512, blocks and is irradiated to tap drain from extraneous light
Road district 3511 and transition region 3512.Described photoresistance is lighttight positivity photoresistance or negativity photoresistance.
Positivity photoresistance is a kind of ultraviolet light-sensitive surface layer, after coating positivity photoresistance, uses one to have pattern and hollow out
Mask plate (Mask) carries out constituency ultra-vioket radiation to positivity photoresistance.Mask plate has the position of figure and has the positivity photoresistance of lower section
Blocking effect, void region ultraviolet light can pass through and be irradiated on positivity photoresistance, and positivity photoresistance is being irradiated by ultraviolet light
After chemical reaction can occur.In developing process subsequently, the positivity photoresistance irradiated by ultraviolet light can remove by developed liquid, is hidden
The positivity photoresistance that do not irradiated by ultraviolet light of gear then will not be removed, thus the most irradiated positivity photoresistance stays, formed with
The pattern that reticle pattern is identical.
Negativity photoresistance is contrary with positivity photoresistance, and negativity photoresistance can occur chemical reaction after being irradiated by ultraviolet light.With
After developing process in, the negativity photoresistance being blocked can remove by developed liquid, and the negativity photoresistance irradiated by ultraviolet light then can be protected
Stay.
In thin film transistor (TFT) manufacturing process, can use one mask plate (Mask1) that active area 35 is doped.At this
In road technique, channel region 351 is blocked, and other regions of active layer are doped.Positivity is used with the etching technics of all film layers
As a example by the situation of photoresistance, in the processing step making photoresistance 300, after forming interlayer insulating film and source-drain electrode, it is coated with one
Layer photoresistance, uses Mask1 that active layer 35 is carried out constituency ultra-vioket radiation, and the region corresponding with channel region 351 can be retained when,
The developed liquid of photoresistance in the region beyond channel region removes.Thus prepare the photoresistance 300 corresponding with channel region 351.In system
Make in the technique of photoresistance 300, with active area doping process step share together with mask plate (Mask1), technique also saves
One mask plate, is greatly saved cost of manufacture.Meanwhile, photoresistance 300 and channel region 351 one_to_one corresponding, can enter channel region 351
Row effectively blocks, and is greatly reduced ambient and is irradiated to channel region 351 and causes leakage current.Further, photoresistance is organic insulator,
Will not and close metal level, semiconductor layer between produce parasitic capacitance, also will not be short-circuited phenomenon, the electrical property to device
Can affect little.
It is emphasized that in other embodiments of the present utility model, photoresistance can also use negativity photoresistance.Premise is,
The etching technics of all film layers all uses negativity photoresistance.Now, when active area 35 is doped, the Mask that channel region is corresponding
Position is hollow out, and after constituency ultraviolet lighting and development, the region corresponding with channel region 351 in photoresistance can be retained when,
The developed liquid of photoresistance in the region beyond channel region removes, thus forms the photoresistance corresponding with channel region 351 on whole substrate
Layer.
It addition, in order to prevent from the extraneous oblique channel region 351 being incident upon active layer 35 of light, it is also possible to increase together
Mask, does more the scope of photoresistance, to block its remaining part do not blocked by source electrode 362, drain electrode 363 on active layer 351
Point.Such as, when photoresistance carrying out Weak ultraviolet constituency and irradiating, the photoresistance pattern of gained can be than irradiation limit, normal ultraviolet light constituency
The big 2-3um of edge.Now, it is big in the drop shadow spread of substrate 31 that photoresistance 300 compares channel region 351 in the drop shadow spread of substrate 31, energy
Enough shield portions are from the extraneous oblique light being incident upon channel region 351.The size of photoresistance is not done with the upper limit by this utility model
Fixed, as long as channel region 351 can be blocked, the most all in protection domain of the present utility model.
The another kind of embodiment party of the low-temperature polysilicon film transistor array base palte that Fig. 4 a, Fig. 4 b provide for this utility model
Formula, is with the embodiment difference shown in Fig. 2, Fig. 3, photoresist layer 300 is corresponding with light shield layer 32, and i.e. photoresist layer 300 is at base
The projection of plate 31 overlaps in the projection of substrate 31 with described light shield layer 32, and in this case, the processing technology of photoresist layer 300 can
With the mask plate (Mask2) of shared making light shield layer 32, technique saves one mask plate, reduces cost of manufacture.
Another embodiment party of the low-temperature polysilicon film transistor array base palte that Fig. 5 a, Fig. 5 b provide for this utility model
Formula, is with the embodiment difference shown in Fig. 2, Fig. 3, photoresist layer 300 is corresponding with whole active layer 35, i.e. photoresist layer 300
Projection at substrate 31 overlaps in the projection of substrate 31 with described active layer 35.In this embodiment, photoresist layer 300 is to whole
Active layer 35 defines and blocks, and can effectively prevent ambient to be irradiated to active layer, the most thorough to the preventing effectiveness of leakage current.
In this case, the processing technology of photoresist layer 300 can share the mask plate (Mask3) making active layer, saves in technique
Save one mask plate, reduce cost of manufacture.
Fig. 6 show the top view of the array base palte of mask plate (Mask4) the making photoresistance 300 using grid 361.Use
The technique that Weak ultraviolet constituency is irradiated, the width of prepared photoresistance 300 is compared with the big 2-3um of the width of gate line 361, and photoresistance blocks
Live transition region 3512 and major part channel region.
The embodiment of the present invention also provides for another thin-film transistor array base-plate, this thin-film transistor array base-plate active
Layer is positioned at grid and deviates from the side of substrate, and thin-film transistor array base-plate also includes: be positioned on substrate and cover the grid of grid
Insulating barrier, active layer is positioned at gate insulator and deviates from substrate side；Source area and drain region are covered with drain electrode by source electrode respectively.
Optionally, the photoresistance of thin-film transistor array base-plate is covered in the surface of channel region, and photoresistance is in the projection of substrate
Overlap in the projection of substrate with channel region.
Optionally, the photoresistance of thin-film transistor array base-plate is positioned at channel region, source electrode, drain electrode deviate from the table of substrate side
Face, and photoresistance overlaps in the projection of substrate with grid in the projection of substrate.
Optionally, thin-film transistor array base-plate also includes passivation layer, and passivation layer is coated with active layer, source electrode and drain electrode, light
Resistance is positioned at passivation layer and deviates from substrate side.
The cross section structure figure of the amorphous silicon film transistor array base palte that Fig. 7 a, Fig. 7 b provide for this utility model and vertical view
Figure.Amorphous silicon film transistor array base palte includes substrate 40, the grid 41, the gate insulator 42 that are sequentially located on substrate, has
Active layer 43, photoresistance 400, passivation layer 46.Source electrode 44, drain electrode 45 are positioned on gate insulator 42, and source electrode 44 and drain electrode 45 cover
The active layer 43 of part, the part not covered by source electrode 44 and drain electrode 45 in active layer is channel region 431.Photoresistance 400 covers
Channel region 431.Gate insulator 42 covers grid 41, and passivation layer is coated with active layer 43 and photoresistance 400.
Channel region 351 is easily subject to the effect of light and produces electron-hole pair, thus produces leakage current, and light irradiates
The leakage current caused the most mainly has the photo-generate electron-hole of transition region to causing.
Photoresistance 400 covers channel region 431, it is possible to blocks and is irradiated to channel region 431, outside being greatly reduced from extraneous light
Boundary's light is irradiated to channel region 431 and causes leakage current.Further, photoresistance is organic insulator, will not with close metal level, half
Producing parasitic capacitance between conductor layer, also will not be short-circuited phenomenon, affects little on the electric property of device.
In the amorphous silicon film transistor array base palte that Fig. 8 provides for this utility model, photoresistance 400 substitutes etching barrier layer
Cross section structure figure.In actual process, often make one layer of etching barrier layer (such as Fig. 2 a).In the present embodiment, photoresistance is used
400 replace etching barrier layer, can play etch stopper effect, effectively raceway groove can be carried out shading again, be greatly reduced leakage
The generation of electric current.The processing technology of photoresistance 400 can share the mask plate (Mask5) of etching barrier layer, and technique is saved together
Mask, reduces cost.
In the amorphous silicon film transistor array base palte that Fig. 9 a provides for this utility model, photoresistance 400 is corresponding with active layer 43
Cross section structure figure.Photoresistance 400 and active layer in the amorphous silicon film transistor array base palte that Fig. 9 b provides for this utility model
The top view of 43 correspondences.In the present embodiment, photoresistance 400 at projection and the active layer 43 of substrate 40 at the projection weight of substrate 40
Closing, whole active layer can be blocked by photoresistance effectively, is greatly reduced the generation of leakage current.The processing technology of photoresistance 400
The mask plate (Mask6) of active layer can be shared, technique is saved one Mask, reduce cost.
In the amorphous silicon film transistor array base palte that Figure 10 a provides for this utility model, photoresistance 400 is corresponding with grid 41
Cross section structure figure.Photoresistance 400 and grid 41 in the amorphous silicon film transistor array base palte that Figure 10 b provides for this utility model
Corresponding top view.In the present embodiment, photoresistance 400 overlaps in the projection of substrate 40 with grid 41 in the projection of substrate 40,
Whole active layer can be blocked by photoresistance effectively, is greatly reduced the generation of leakage current.The processing technology of photoresistance 400 is permissible
The mask plate (Mask7) of common grid 41, technique is saved one Mask, reduces cost.
In this specification, various piece uses the mode gone forward one by one to describe, and what each some importance illustrated is and other parts
Difference, between various piece, identical similar portion sees mutually.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses this practicality new
Type.Multiple amendment to these embodiments will be apparent from for those skilled in the art, is determined herein
The General Principle of justice can realize in the case of without departing from spirit or scope of the present utility model in other embodiments.Cause
This, this utility model is not intended to be limited to embodiment illustrated herein, and is to fit to and principles disclosed herein and new
The widest scope that grain husk feature is consistent.
Claims (10)
1. a thin-film transistor array base-plate, it is characterised in that including:
Substrate；
Being positioned at the active layer on described substrate, grid, source electrode and drain electrode, described active layer is by channel region, source area and drain region
Composition, described source electrode and described drain electrode be positioned at described active layer and deviate from the side of substrate, and described source area, drain region are respectively and institute
State source electrode and described drain contact；
It is positioned at described active layer and deviates from the photoresistance of described substrate side, be used for stopping that light deviates from substrate side from described active layer
Being irradiated on described channel region, described photoresistance is lighttight positivity photoresistance or negativity photoresistance, and described channel region is at described base
The projection of plate falls at described photoresistance in the drop shadow spread of described substrate.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that described active layer is positioned at the described grid back of the body
From the side of described substrate, described thin-film transistor array base-plate also includes:
Being positioned on described substrate and cover the gate insulator of described grid, described active layer is positioned at described gate insulator to deviate from
Described substrate side；
Described source area and described drain region are covered with described drain electrode by described source electrode respectively.
3. thin-film transistor array base-plate as claimed in claim 2, it is characterised in that described photoresistance is covered in described channel region
Surface, and described photoresistance overlaps in the projection of described substrate with described channel region in the projection of described substrate.
4. thin-film transistor array base-plate as claimed in claim 2, it is characterised in that described photoresistance be positioned at described channel region,
Source electrode, drain electrode deviate from the surface of described substrate side, and described photoresistance in the projection of described substrate with described grid at described base
The projection of plate overlaps.
5. thin-film transistor array base-plate as claimed in claim 2, it is characterised in that described thin-film transistor array base-plate is also
Including passivation layer, described passivation layer covers described active layer, source electrode and drain electrode, and described photoresistance is positioned at described passivation layer and deviates from substrate
Side.
6. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that described grid is positioned at the described active layer back of the body
From the side of described substrate, described thin-film transistor array base-plate also includes:
Being positioned at described active layer and deviate from the gate insulator of described substrate side, described gate insulator covers described active layer,
Described grid is positioned at described gate insulator and deviates from described substrate side；
Described channel region also includes transition region, described transition region between described channel region and described source area, or, described mistake
Cross district to be positioned between described channel region and described drain region；
Being positioned at described gate insulator and deviate from the interlayer insulating film of substrate side, described interlayer insulating film covers described grid；
Described photoresistance is positioned at described interlayer insulating film and deviates from the surface of described substrate side.
7. thin-film transistor array base-plate as claimed in claim 6, it is characterised in that described thin-film transistor array base-plate is also
Including lower light shield layer, described lower light shield layer is between described substrate and described active layer, and described channel region is at described substrate
Projection falls at described lower light shield layer in the drop shadow spread of described substrate, and described photoresistance is in projection and the described lower screening of described substrate
Photosphere overlaps in the projection of described substrate.
8. thin-film transistor array base-plate as claimed in claim 6, it is characterised in that described channel region is in the throwing of described substrate
Shadow overlaps in the projection of described substrate with described photoresistance.
9. a display floater, it is characterised in that include the thin-film transistor array base-plate described in any one of claim 1-8.
10. a display device, it is characterised in that include the display floater described in claim 9.
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| CN107817636B (en) * | 2017-10-31 | 2020-09-29 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
| CN107817636A (en) * | 2017-10-31 | 2018-03-20 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
| WO2020024292A1 (en) * | 2018-08-03 | 2020-02-06 | 深圳市柔宇科技有限公司 | Array substrate and display device |
| CN112639600A (en) * | 2018-08-03 | 2021-04-09 | 深圳市柔宇科技股份有限公司 | Array substrate and display device |
| WO2020073547A1 (en) * | 2018-10-11 | 2020-04-16 | 深圳市华星光电技术有限公司 | Thin film transistor and manufacturing method therefor |
| CN109378345A (en) * | 2018-10-11 | 2019-02-22 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and its manufacturing method |
| CN110400811A (en) * | 2019-08-30 | 2019-11-01 | 合肥鑫晟光电科技有限公司 | Array substrate and display device |
| US11264411B2 (en) | 2019-08-30 | 2022-03-01 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate and display device including light shielding layers |
| CN111402739A (en) * | 2020-03-31 | 2020-07-10 | 云谷（固安）科技有限公司 | Display module and preparation method thereof |
| CN112542470A (en) * | 2020-12-04 | 2021-03-23 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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