CN112639600A - Array substrate and display device - Google Patents
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- CN112639600A CN112639600A CN201880094119.6A CN201880094119A CN112639600A CN 112639600 A CN112639600 A CN 112639600A CN 201880094119 A CN201880094119 A CN 201880094119A CN 112639600 A CN112639600 A CN 112639600A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
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Abstract
The invention discloses an array substrate (10), which comprises a substrate (11), a thin film transistor (13) and a first light blocking layer (15), wherein the thin film transistor (13) and the first light blocking layer (15) are arranged on the substrate (11), the first light blocking layer (15) is positioned on one side, away from the substrate (11), of the thin film transistor (13), and the orthographic projection of an oxide active layer (133) of the thin film transistor (13) on the substrate (11) is positioned in the orthographic projection of the first light blocking layer (15) on the substrate (11). The invention also provides a display device.
Description
The invention relates to the technical field of display, in particular to an array substrate and a display device.
Currently, flat panel displays have taken the lead of the display market and are moving towards large size, high resolution. In order to meet the requirements of large size and high resolution, the mobility of a Thin Film Transistor (TFT) in a display needs to be improved to improve the display effect, but the mobility of an amorphous silicon (a-Si) TFT in the prior art is low, which has become a constraint factor for improving the display effect, and the oxide TFT has a wider application prospect due to its higher mobility than the a-Si TFT.
However, the oxide TFT has poor light stability, and when the oxide TFT is irradiated by external light, the oxide TFT is likely to cause an increase in leakage current of the oxide active layer, which reduces the reliability of the oxide TFT and affects the display quality.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention disclose an array substrate and a display device with improved reliability.
An array substrate comprises a substrate, a thin film transistor and a first light blocking layer, wherein the thin film transistor and the first light blocking layer are arranged on the substrate, the first light blocking layer is located on one side, away from the substrate, of the thin film transistor, and the orthographic projection of an oxide active layer of the thin film transistor on the substrate is located in the orthographic projection of the first light blocking layer on the substrate.
Further, the array substrate further comprises a second light-blocking layer, and the second light-blocking layer is arranged between the substrate and the oxide active layer.
Further, the array substrate further comprises a first passivation layer, and the first passivation layer is arranged between the substrate and the second light blocking layer.
Further, the array substrate further comprises a second passivation layer located between the oxide active layer and the second light blocking layer.
The thin film transistor further comprises a grid electrode and a grid electrode insulating layer, the grid electrode is arranged on the substrate, the second light blocking layer is arranged on the grid electrode and covers the grid electrode, and the grid electrode insulating layer is arranged between the oxide active layer and the second light blocking layer.
Further, the orthographic projection of the second light-blocking layer on the substrate is positioned in the orthographic projection of the first light-blocking layer on the substrate, and the orthographic projection area of the second light-blocking layer on the substrate is smaller than that of the first light-blocking layer on the substrate.
Furthermore, the thin film transistor further comprises a gate electrode and a gate insulating layer, the gate electrode is arranged on the substrate, the gate insulating layer is arranged between the oxide active layer and the gate electrode, and the second light blocking layer is arranged on the gate insulating layer.
Further, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the gate, the first gate insulating layer, the second light blocking layer, and the second gate insulating layer are sequentially stacked on the substrate.
Further, the thin film transistor further comprises a gate electrode and a gate insulating layer, the array substrate further comprises a passivation layer, the second light blocking layer, the passivation layer, the oxide active layer, the gate insulating layer and the gate electrode are sequentially stacked on the substrate, and the second light blocking layer is adjacent to the substrate.
Further, the second light-blocking layer is made of a passivation layer material doped with a light-absorbing material.
Further, the second light-blocking layer includes a light-shielding layer and a light-absorbing layer which are stacked.
Further, the first light-blocking layer comprises a light-shielding layer and a light-absorbing layer which are arranged in a stacked mode.
Furthermore, the array substrate further comprises a third passivation layer, the third passivation layer covers the thin film transistor, and the first light blocking layer is arranged on one side, far away from the substrate, of the third passivation layer.
Further, the array substrate further comprises a fourth passivation layer, and the fourth passivation layer covers one side, far away from the oxide active layer, of the first light-blocking layer.
Further, the first light blocking layer is formed by doping a light absorbing material with a passivation layer material.
A display device comprises the array substrate.
According to the array substrate and the display device provided by the invention, the first light blocking layer is arranged on the side, away from the substrate, of the oxide active layer, and the orthographic projection of the oxide active layer on the substrate is positioned in the orthographic projection of the first light blocking layer on the substrate, so that the damage of light to the oxide active layer caused by irradiation can be effectively avoided, and the reliability of the array substrate is improved. In addition, the array substrate is provided with the second light blocking layer on one side of the oxide active layer adjacent to the substrate, so that the oxide active layer is protected doubly, and the reliability of the array substrate is further improved.
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a cross-sectional view of an array substrate according to a first embodiment of the present invention.
Fig. 1a is a cross-sectional view of an array substrate according to an embodiment of the invention.
Fig. 2 is a cross-sectional view of an array substrate according to a second embodiment of the present invention.
Fig. 3 is a cross-sectional view of the array substrate shown in fig. 2 and a color filter substrate disposed on the array substrate.
Fig. 4 is a cross-sectional view of an array substrate according to a third embodiment of the present invention.
Fig. 5 is a cross-sectional view of an array substrate according to a fourth embodiment of the present invention.
Fig. 6 is a cross-sectional view of an array substrate according to a fifth embodiment of the present invention.
Fig. 7 is a cross-sectional view of an array substrate according to a sixth embodiment of the present invention.
Fig. 8 is a cross-sectional view of an array substrate according to a seventh embodiment of the present invention.
Fig. 9 is a cross-sectional view of an array substrate according to an eighth embodiment of the present invention.
Fig. 10 is a top view of a display device provided by the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a first embodiment of the invention provides an array substrate 10. The array substrate 10 includes a substrate 11, a thin film transistor 13 and a first light blocking layer 15, wherein the thin film transistor 13 is disposed on the substrate 11. The first light-blocking layer 15 is located on a side of the thin film transistor 13 away from the substrate 10, and is used for preventing damage caused by light irradiating the oxide active layer 133 of the thin film transistor 13. An orthogonal projection of the oxide active layer 133 on the substrate 11 is located within an orthogonal projection of the first light blocking layer 15 on the substrate 11.
In other words, the orthographic projection of the oxide active layer 133 on the substrate 11 is overlapped with the orthographic projection of the first light-blocking layer 15 on the substrate 11, and the orthographic projection area of the oxide active layer 133 on the substrate 11 is smaller than or equal to the orthographic projection area of the first light-blocking layer 15 on the substrate 11, so that the oxide active layer 133 is effectively prevented from being damaged by light irradiating the oxide active layer 133, and the reliability of the array substrate 10 is improved. The light is side leakage light of other processes (such as exposure and development), or exposure reflected light, or ambient light, or emergent light of a backlight source, and the like.
In this embodiment, the thin film transistor 13 has a bottom gate structure. The thin film transistor 13 includes a gate electrode 131, a gate insulating layer 135, a source electrode 137, and a drain electrode 139. The array substrate 10 further includes a second light blocking layer 17 and a passivation layer 19. The gate electrode 131 is attached to the substrate 11. The second light-blocking layer 17 covers a side of the gate electrode 131 away from the substrate 11, and is used to prevent damage to the oxide active layer 133 due to gate reflection light and the like. The gate insulating layer 135 is disposed between the oxide active layer 133 and the second light blocking layer 17. The source electrode 137 and the drain electrode 139 are spaced apart from one side of the oxide active layer 133 away from the substrate 11. The passivation layer 19 is disposed on the source and drain electrodes 137 and 139 and the oxide active layer 133. The first light-blocking layer 15 is provided on the passivation layer 19. The orthographic projection of the second light-blocking layer 17 on the substrate 11 is positioned in the orthographic projection of the first light-blocking layer 15 on the substrate 11, and the orthographic projection area of the second light-blocking layer 17 on the substrate 11, the orthographic projection area of the first light-blocking layer 15 on the substrate 11 and the orthographic projection area of the grid 131 on the substrate 11 are approximately the same. The array substrate 10 can be realized by chemical vapor deposition, physical vapor deposition, exposure, development, etching, and other process steps.
The first light-blocking layer 15 and the second light-blocking layer 17 are respectively located at two sides of the oxide active layer 133, so that the oxide active layer 133 is protected doubly, damage to the oxide active layer 133 caused by lateral light, backlight, ambient light, gate reflected light and the like can be effectively avoided, and the reliability of the array substrate 10 is improved. In addition, since the orthographic projection of the oxide active layer 133 on the substrate 11 is located in the orthographic projection of the first light-blocking layer 15 on the substrate 11, the damage of the oxide active layer 133 not covered by the source electrode 137 and the drain electrode 139 due to the irradiation of light can be avoided.
In this embodiment, the first light blocking layer 15 is made of a light absorbing material capable of absorbing energy of incident light, and reducing damage of the oxide active layer 133 by the incident light entering into the array substrate 10. The light absorption material comprises one or a combination of more than one of a carbon black composition, organic macromolecules with a cavity structure, a carbon nanotube mixture, a resin compound and the like, preferably, the light absorption effect of the light absorption material reaches more than 99% so as to absorb most of energy of incident light entering the array substrate 10 and avoid damage of light to the oxide active layer 133. The second light-blocking layer 17 is made of an insulating opaque material to avoid affecting the performance of the gate 131.
The composition of the carbon black comprises the following components: 5 to 20 percent of photosensitive resin, 0.1 to 5 percent of photoinitiator, 10 to 50 percent of carbon black dispersion solution, 30 to 50 percent of solvent and 0.1 to 1 percent of additive. Wherein, the composition containing the carbon black can also contain a monomer to polymerize small molecules and macromolecules; solvents and additives include a variety of organic solvents and additives that render the surface of the composition comprising carbon black flat, for example: the organic solvent may be one or more selected from ethylene glycol methyl ether, ethylene glycol ethyl ether, propylene glycol methyl ether acetate, propylene glycol ethyl ether acetate, tetrahydrofuran, cyclohexanone, ethyl cellosolve acetate, butyl cellosolve acetate, 1-methoxy-2-propyl acetate, diethylene glycol dimethyl ether, ethylbenzene, xylene, methanol, and isopropyl ketone. The additive comprises one or more than two of defoaming agent, wetting agent and flatting agent.
In one embodiment, the carbon black in the carbon black composition has a particle size greater than or equal to 20 angstroms and less than or equal to 1000 angstroms. Preferably, the carbon black in the composition has a particle size of greater than or equal to 20 angstroms and less than or equal to 500 angstroms.
In one embodiment, the first light-blocking layer 15 is made of a light-blocking material that does not transmit light, such as a metal material.
It is understood that the material of the first light-blocking layer 15 and the second light-blocking layer 17 is not limited, and may be any material that can prevent a portion of incident light from entering the array substrate 10 and irradiating the oxide active layer 133, for example, the side of the first light-blocking layer 15 away from the substrate 11 is coated with a reflective material as a reflective surface.
In one embodiment, the light blocking effect of the first light blocking layer 15 is adjusted by adjusting the vertical distance between the first light blocking layer 15 and the oxide active layer 133; the light blocking effect of the second light blocking layer 17 is adjusted by adjusting the vertical distance between the second light blocking layer 17 and the oxide active layer 133.
In one embodiment, referring to fig. 1a, the first light blocking layer 15 includes a light shielding layer 151 and a light absorbing layer 153 stacked together, the second light blocking layers 17 include a light shielding layer 171 and a light absorbing layer 173 stacked together, the light shielding layers 151 and 171 are made of a light-impermeable material, and the light absorbing layers 153 and 173 are made of a light absorbing material. The light-shielding layer 151 of the first light-blocking layer 15 is provided on the side of the first light-blocking layer 15 away from the substrate 10, and the light-shielding layer 171 of the second light-blocking layer 17 is provided on the side of the second light-blocking layer 17 away from the substrate 10. It is to be understood that the light-shielding layer 151 of the first light-blocking layer 15 may be provided on a side of the first light-blocking layer 15 adjacent to the substrate 10; the light-shielding layer 171 of the second light-blocking layer 17 may be disposed on a side of the second light-blocking layer 17 adjacent to the substrate 10, the first light-blocking layer 15 includes at least one of the light-shielding layer 151 and the light-absorbing layer 153, and the second light-blocking layer 17 includes at least one of the light-shielding layer 171 and the light-absorbing layer 173.
Referring to fig. 2, a second embodiment of the invention provides an array substrate 20. The array substrate 20 has substantially the same structure as the array substrate 10 provided in the first embodiment, except that the area of the second light-blocking layer 27 projected onto the substrate 21 is smaller than the area of the first light-blocking layer 25 projected onto the substrate 21.
Referring to fig. 3, taking the light emitting source 203 of the color filter substrate 201 located above the array substrate 20 as an example, how to determine the boundary position of the first light blocking layer 25 will be briefly described, where the color filter substrate 201 is disposed adjacent to the first light blocking layer 25. The color filter substrate 201 includes a plurality of light emitting sources 203.
The side of the gate 231 adjacent to the substrate 21 includes a first end 2311 and a second end 2313 opposite to each other. The side of the oxide active layer 233 adjacent to the substrate 21 includes a first end point 2331 and a second end point 2333 disposed opposite to each other. The first light blocking layer 25 includes a first boundary 251 and a second boundary 253 opposite to each other on a side adjacent to the oxide active layer 233. The first end 2311 of the gate electrode 231 and the first end 2331 of the oxide active layer 233 correspond to the first boundary 251 of the first light-blocking layer 25. The second end 2313 of the gate electrode 231 and the second end 2333 of the oxide active layer 233 correspond to the second boundary 253 of the first light-blocking layer 25.
Each of the light-emitting sources 203 includes a first border 2031 and a second border 2033 disposed opposite to each other. Two light sources 203 of the plurality of light sources 203 are selected, wherein the two light sources 203 are a first light source 2035 and a second light source 2037.
The first light emitted from the first border 2031 by the first light source 2035 can be irradiated to the first end 2311 of the gate electrode 231, and the second light emitted from the second border 2033 by the first light source 2035 can be irradiated to the first end 2331 of the oxide active layer 233. In this embodiment, the first light-emitting source 2035 is a light-emitting source 203 having the largest distance from the first boundary 2031 to the first end 2331 of the oxide active layer 233, among the light-emitting sources 203 that can affect the first end 2311 of the gate electrode 231 of the thin film transistor 23 and the first end 2331 of the oxide active layer 233, so as to further reduce the probability of the oxide active layer 233 being irradiated with light. The intersection of the first light ray and the second light ray is the position of the first boundary 251.
The third light emitted from the first boundary 2033 by the second light emitting source 2037 can be irradiated to the second end 2313 of the gate electrode 231, and the fourth light emitted from the second boundary 2033 by the second light emitting source 2037 can be irradiated to the second end 2333 of the oxide active layer 233. In this embodiment, the second light-emitting source 2037 is the light-emitting source 203 having the largest distance from the second boundary 2033 to the second end 2333 of the oxide active layer 233, among the light-emitting sources 203 affecting the second end 2313 of the gate electrode 231 of the thin film transistor 23 and the second end 2333 of the oxide active layer 233, so as to further reduce the probability of the oxide active layer 233 being irradiated with light. The intersection of the third light ray and the fourth light ray is the position of the second boundary 253.
It is understood that the length, width and distance of the first light-blocking layer 25 from the oxide active layer 233 are adjusted as needed.
Referring to fig. 4, a third embodiment of the invention provides an array substrate 40. The array substrate 40 has substantially the same structure as the array substrate 10 provided in the first embodiment, except that the gate insulating layer 435 includes a first gate insulating layer 4351 and a second gate insulating layer 4353, the gate 431, the first gate insulating layer 4351, the second light blocking layer 47, the second gate insulating layer 4353, the oxide active layer 433, and the source 437 are sequentially stacked on the substrate 41, and the gate 431 is disposed adjacent to the substrate 41.
Since the second light-blocking layer 47 is disposed between the first gate insulating layer 4351 and the second gate insulating layer 4353, in the present embodiment, the second light-blocking layer 47 is made of an opaque metal material. In an embodiment, the second light-blocking layer 47 is made of a material including a light-absorbing material. It is understood that the second light-blocking layer 47 is entirely covered with the gate insulating layer 435, i.e., each side of the second light-blocking layer 47 is covered with the gate insulating layer 435.
Referring to fig. 5, a fourth embodiment of the invention provides an array substrate 50. The array substrate 50 has substantially the same structure as the array substrate 10 provided in the first embodiment. The array substrate 50 includes a substrate 51, a thin film transistor 53, a first light-blocking layer 55, a second light-blocking layer 57, and a passivation layer 58, except that in this embodiment, the thin film transistor 53 has a top gate structure, and the first light-blocking layer 55 and the second light-blocking layer 57 are disposed.
The first light-blocking layer 55 and the second light-blocking layer 57 are both provided on the passivation layer 58. Specifically, the passivation layer 58 includes a first passivation layer 581, a second passivation layer 583, a third passivation layer 585 and a fourth passivation layer 587. A first passivation layer 581, a second light-blocking layer 57, a second passivation layer 583, a thin film transistor 53, a third passivation layer 585, a first light-blocking layer 55, and a fourth passivation layer 587 are sequentially stacked on the substrate 51. The first passivation layer 581 is disposed adjacent to the substrate 51. The oxide active layer 533 of the thin film transistor 53 is located between the first light-blocking layer 55 and the second light-blocking layer 57. The first light blocking layer 55 is positioned between the third passivation layer 585 and the fourth passivation layer 587, and the second light blocking layer 57 is positioned between the first passivation layer 581 and the second passivation layer 583.
The thin film transistor 53 further includes a gate electrode 531, a gate insulating layer 535, a source electrode 537, and a drain electrode 539, wherein the oxide active layer 533, the gate insulating layer 535, and the gate electrode 531 are sequentially stacked on one side of the second passivation layer 583 away from the first passivation layer 581, the oxide active layer 533 is disposed adjacent to the second passivation layer 583, the source electrode 537, the gate insulating layer 535, and the drain electrode 539 are disposed on the oxide active layer 533 at intervals, the gate insulating layer 535 is disposed between the source electrode 537 and the drain electrode 539, and the third passivation layer 585 covers the gate electrode 531, the source electrode 537, the drain electrode 539, and the oxide active layer.
The first light blocking layer 55 is formed on the side of the oxide active layer 533 away from the substrate 51 to prevent the oxide active layer 533 from being damaged by light irradiation at portions not covered by the gate insulating layer 535, the source electrode 537, and the drain electrode 539. The second light blocking layer 57 is formed on the side of the oxide active layer 533 adjacent to the substrate 51 to prevent the oxide active layer 533 from being affected by backlight, reflected light, and the like.
In this embodiment mode, the second light-blocking layer 57 is made of a material including a light-absorbing material. When the array substrate 50 is prepared, the light absorbing material is coated on the first passivation layer 583, and the light absorbing material is subjected to exposure, development and post-baking processes to form the second light blocking layer 57, which can prevent side light leakage, a backlight source and the like from damaging the oxide active layer 533.
Referring to fig. 6, a fifth embodiment of the invention provides an array substrate 60. The array substrate 60 has substantially the same structure as the array substrate 50 provided in the fourth embodiment, except for the arrangement of the first light-blocking layer 65 and the second light-blocking layer 67.
The passivation layer 68 includes a first passivation layer 681 and a second passivation layer 683. The second light-blocking layer 67, the first passivation layer 681, the thin film transistor 63, the second passivation layer 683, and the first light-blocking layer 65 are sequentially disposed on the substrate 61, and the second light-blocking layer 67 is attached to the substrate 61.
The second light-blocking layer 67 is arranged at the bottom of the first passivation layer 681 below the oxide active layer 633, and the first light-blocking layer 65 is arranged at the top of the second passivation layer 683 above the oxide active layer 633, so that the difficulty of the manufacturing process is reduced, and the manufacturing process is simplified.
Referring to fig. 7, a sixth embodiment of the invention provides an array substrate 70. The array substrate 70 has substantially the same structure as the array substrate 60 provided in the fifth embodiment, except that the second light-blocking layer 77 is located between the oxide active layer 733 and the substrate 71, the first side of the second light-blocking layer 77 is attached to the oxide active layer 733, the second side of the second light-blocking layer 77 is attached to the substrate 71, and the second light-blocking layer 77 is formed by doping a light-absorbing material in a passivation layer material, so that the second light-blocking layer 77 has both functions of a passivation layer and a light-blocking function. In this embodiment, the passivation layer material includes at least one of silicon oxide and silicon nitride.
The first light blocking layer 75 is disposed over the oxide active layer 733, and the light absorbing material is doped in the passivation layer under the oxide active layer 733 to form the second light blocking layer 77, thereby achieving shielding of light.
Referring to fig. 8, a seventh embodiment of the invention provides an array substrate 80. The array substrate 80 has substantially the same structure as the array substrate 60 provided in the fifth embodiment, except that the first light-blocking layer 85 covers the thin film transistor 83, and the first light-blocking layer 85 is formed by doping a light-absorbing material into a passivation layer material, so as to have both functions of a passivation layer and light blocking. In this embodiment, the passivation layer material includes at least one of silicon oxide and silicon nitride.
The first light blocking layer 85 is formed by doping a light absorbing material in the passivation layer on the oxide active layer 833, and the second light blocking layer 87 is arranged outside the first passivation layer 883 below the oxide active layer 833 to shield light and improve the performance and reliability of the array substrate 80.
Referring to fig. 9, an array substrate 90 according to an eighth embodiment of the present invention is provided. The array substrate 90 has substantially the same structure as the array substrate 60 provided in the fifth embodiment, except that the first light-blocking layer 95 of the array substrate 90 covers the thin film transistor 93, the second light-blocking layer 97 of the array substrate 90 is disposed between the oxide active layer 933 of the thin film transistor 93 and the substrate 91, and both the second light-blocking layer 97 and the first light-blocking layer 97 are formed by doping a light-absorbing material in a passivation layer material, so as to have both functions of a passivation layer and a light-blocking layer.
Referring to fig. 10, the present invention further provides a display device 100 including the array substrate according to any of the above embodiments. Display panel, electronic paper, Organic Light-Emitting Diode (OLED) panel, mobile phone, tablet computer, tv, display, notebook computer, digital photo frame, navigator and other products or components with display function.
According to the array substrate and the display device provided by the invention, the first light blocking layer is arranged on the side, away from the substrate, of the oxide active layer, so that the damage of light to the oxide active layer caused by irradiation can be effectively avoided, and the reliability of the array substrate is improved. In addition, the array substrate is provided with the second light blocking layer on one side of the oxide active layer adjacent to the substrate, so that the oxide active layer is protected doubly, and the reliability of the array substrate is further improved.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (16)
- The array substrate is characterized by comprising a substrate, a thin film transistor and a first light blocking layer, wherein the thin film transistor and the first light blocking layer are arranged on the substrate, the first light blocking layer is positioned on one side, away from the substrate, of the thin film transistor, and the orthographic projection of an oxide active layer of the thin film transistor on the substrate is positioned in the orthographic projection of the first light blocking layer on the substrate.
- The array substrate of claim 1, further comprising a second light blocking layer disposed between the substrate and the oxide active layer.
- The array substrate of claim 2, further comprising a first passivation layer disposed between the substrate and the second light blocking layer.
- The array substrate of claim 3, further comprising a second passivation layer between the oxide active layer and the second light blocking layer.
- The array substrate of claim 2, wherein the thin film transistor further comprises a gate electrode disposed on the substrate, and a gate insulating layer disposed between the oxide active layer and the second light blocking layer, wherein the second light blocking layer is disposed on the gate electrode and covers the gate electrode.
- The array substrate of claim 5, wherein an orthographic projection of the second light-blocking layer on the substrate is within an orthographic projection of the first light-blocking layer on the substrate, and an orthographic area of the second light-blocking layer on the substrate is smaller than an orthographic area of the first light-blocking layer on the substrate.
- The array substrate of claim 2, wherein the thin film transistor further comprises a gate electrode and a gate insulating layer, the gate electrode is disposed on the substrate, the gate insulating layer is disposed between the oxide active layer and the gate electrode, and the second light blocking layer is disposed on the gate insulating layer.
- The array substrate of claim 7, wherein the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, and the gate, the first gate insulating layer, the second light blocking layer, and the second gate insulating layer are sequentially stacked on the substrate.
- The array substrate of claim 2, wherein the thin film transistor further comprises a gate electrode and a gate insulating layer, the array substrate further comprises a passivation layer, the second light blocking layer, the passivation layer, the oxide active layer, the gate insulating layer and the gate electrode are sequentially stacked on the substrate, and the second light blocking layer is disposed adjacent to the substrate.
- The array substrate of claim 2, wherein the second light blocking layer is made of a passivation layer material doped with a light absorbing material.
- The array substrate of claim 2, wherein the second light blocking layer comprises a light blocking layer and a light absorbing layer stacked.
- The array substrate of claim 1, wherein the first light blocking layer comprises a light blocking layer and a light absorbing layer stacked.
- The array substrate of claim 1, further comprising a third passivation layer covering the thin film transistor, wherein the first light blocking layer is disposed on a side of the third passivation layer away from the substrate.
- The array substrate of claim 13, further comprising a fourth passivation layer covering a side of the first light blocking layer away from the oxide active layer.
- The array substrate of claim 1, wherein the first light blocking layer is formed by doping a light absorbing material with a passivation layer material.
- A display device comprising the array substrate according to any one of claims 1 to 15.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/098669 WO2020024292A1 (en) | 2018-08-03 | 2018-08-03 | Array substrate and display device |
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| CN112639600A true CN112639600A (en) | 2021-04-09 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579356A (en) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | Oxide TFT, manufacturing method of oxide TFT, display panel and display device |
| CN104934449A (en) * | 2015-07-16 | 2015-09-23 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof, and display apparatus |
| CN105097831A (en) * | 2015-06-23 | 2015-11-25 | 京东方科技集团股份有限公司 | Low temperature poly-silicon back plate, fabrication method thereof and light-emitting device |
| CN205789970U (en) * | 2016-05-03 | 2016-12-07 | 厦门天马微电子有限公司 | A kind of array base palte, display floater and display device |
| CN106601754A (en) * | 2016-12-06 | 2017-04-26 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and preparation method thereof, and display device |
| CN106597770A (en) * | 2016-12-28 | 2017-04-26 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method and display apparatus |
| CN106684103A (en) * | 2017-02-28 | 2017-05-17 | 厦门天马微电子有限公司 | Array substrate, display panel and display apparatus |
| CN107302032A (en) * | 2017-06-19 | 2017-10-27 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display panel |
-
2018
- 2018-08-03 WO PCT/CN2018/098669 patent/WO2020024292A1/en active Application Filing
- 2018-08-03 CN CN201880094119.6A patent/CN112639600A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579356A (en) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | Oxide TFT, manufacturing method of oxide TFT, display panel and display device |
| CN105097831A (en) * | 2015-06-23 | 2015-11-25 | 京东方科技集团股份有限公司 | Low temperature poly-silicon back plate, fabrication method thereof and light-emitting device |
| CN104934449A (en) * | 2015-07-16 | 2015-09-23 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof, and display apparatus |
| CN205789970U (en) * | 2016-05-03 | 2016-12-07 | 厦门天马微电子有限公司 | A kind of array base palte, display floater and display device |
| CN106601754A (en) * | 2016-12-06 | 2017-04-26 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and preparation method thereof, and display device |
| CN106597770A (en) * | 2016-12-28 | 2017-04-26 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method and display apparatus |
| CN106684103A (en) * | 2017-02-28 | 2017-05-17 | 厦门天马微电子有限公司 | Array substrate, display panel and display apparatus |
| CN107302032A (en) * | 2017-06-19 | 2017-10-27 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display panel |
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