CN107393933B - Manufacturing method of array substrate, array substrate and display panel - Google Patents
Manufacturing method of array substrate, array substrate and display panel Download PDFInfo
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- CN107393933B CN107393933B CN201710640506.2A CN201710640506A CN107393933B CN 107393933 B CN107393933 B CN 107393933B CN 201710640506 A CN201710640506 A CN 201710640506A CN 107393933 B CN107393933 B CN 107393933B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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Abstract
The invention discloses a manufacturing method of an array substrate, the array substrate and a display panel, and belongs to the technical field of display. The method comprises the following steps: forming an active layer on a base substrate; sequentially forming a first gate insulation pattern and a gate pattern on the active layer; sequentially forming an interlayer insulating layer and a source/drain electrode pattern on the gate electrode pattern; the upper surface of the first gate insulation pattern is provided with a convex structure, the lower surface of the gate pattern is provided with a groove structure matched with the convex structure in shape, and the orthographic projection of the gate pattern on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate. According to the invention, the orthographic projection of the grid electrode pattern on the substrate is covered on the orthographic projection of the first grid insulation pattern on the substrate, so that the on-state current of the TFT is effectively improved. The invention is used in the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate, the array substrate and a display panel.
Background
The oxide semiconductor material is considered to be one of semiconductor active materials most suitable for driving a Thin-film transistor (TFT) of an Organic light-emitting diode (Organic L light-emitting diode, abbreviated as O L ED) due to its advantages of high carrier mobility, low preparation temperature, good electrical uniformity, low cost and the like, and the TFT made of an oxide semiconductor is referred to as an oxide TFT, and is widely applied to an O L ED display panel at present.
For example, referring to fig. 1-1, fig. 1-1 is a schematic structural diagram of an array substrate provided in the prior art, the array substrate may include a substrate 01, a shielding layer 02, a buffer layer 03, an active layer 04, a gate insulation pattern 05, a gate pattern 06, an interlayer insulation layer 07, and a source/Drain pattern 08, the active layer 04 may be divided into a gate control region 041, a lightly Doped Drain (english: L ighty Doped Drain) region 042, and a conductor region 043, wherein a region of the active layer 04, which is positively projected on the active layer 04 by the gate pattern 06, is the gate control region 041, a region of the active layer 04, which is not covered by a conductor region 633, and a region of the active layer 04, which is positively projected on the active layer 04 by the gate insulation pattern 05, is the conductor region 043, and a region of the active layer 04 between the gate control region 042 and the Drain region 042.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
as shown in fig. 1, due to the influence of the manufacturing process, the forward projection areas of the gate insulating pattern 05 and the gate pattern 06 on the active layer 04 are sequentially decreased, resulting in an increase in the width d01 of the L DD region 042, and thus a larger parasitic resistance, which in turn results in a smaller on-state current of the TFT.
Disclosure of Invention
In order to solve the problem that the on-state current of the TFT in the prior art is small, embodiments of the present invention provide a manufacturing method of an array substrate, and a display panel. The technical scheme is as follows:
in a first aspect, a method for manufacturing an array substrate is provided, the method including:
forming an active layer on a base substrate;
sequentially forming a first gate insulation pattern and a gate pattern on the active layer;
sequentially forming an interlayer insulating layer and a source/drain electrode pattern on the grid electrode pattern;
and the orthographic projection of the grid electrode pattern on the substrate covers the orthographic projection of the first grid insulation pattern on the substrate.
Optionally, the sequentially forming a first gate insulation pattern and a gate pattern on the active layer includes:
forming a gate insulating film on the active layer;
performing a composition process on the gate insulating layer film once to form a second gate insulating pattern;
forming a gate thin film on the second gate insulating pattern;
performing a one-time composition process on the gate thin film and the second gate insulation pattern to form the gate pattern and the first gate insulation pattern;
wherein, the orthographic projection of the second gate insulation pattern on the substrate base plate covers the orthographic projection of the active layer on the substrate base plate, and the orthographic projection of the active layer on the substrate base plate covers the orthographic projection of the first gate insulation pattern on the substrate base plate.
Optionally, the performing a patterning process on the gate insulating film to form a second gate insulating pattern includes:
coating a first photoresist on the gate insulating layer film;
carrying out first exposure treatment and first development treatment on the first photoresist through a grid mask plate to form a first photoresist pattern;
performing first etching treatment on the gate insulating layer film to form a second gate insulating pattern with the first photoresist pattern;
and stripping the first photoresist pattern to obtain the second gate insulation pattern.
Optionally, the performing a patterning process on the gate thin film and the second gate insulation pattern to form the gate pattern and the first gate insulation pattern includes:
coating a second photoresist on the grid film;
carrying out second exposure treatment and second development treatment on the second photoresist through the grid mask plate to form a second photoresist pattern;
performing second etching treatment on the gate thin film and the second gate insulation pattern to form a gate pattern with the second photoresist pattern and the first gate insulation pattern;
stripping the second photoresist pattern to obtain the gate pattern and the first gate insulation pattern;
the first photoresist and the second photoresist are both positive photoresists, and the exposure intensity of the first exposure treatment is greater than that of the second exposure treatment so that the width of the first photoresist pattern is smaller than that of the second photoresist pattern;
or, the first photoresist and the second photoresist are both negative photoresists, and the exposure intensity of the first exposure treatment is smaller than that of the second exposure treatment, so that the width of the first photoresist pattern is smaller than that of the second photoresist pattern.
Optionally, the second etching treatment includes: the etching treatment is carried out for two times,
the second etching treatment is performed on the gate thin film and the second gate insulation pattern to form a gate pattern with the second photoresist pattern and the first gate insulation pattern, and the method includes:
carrying out primary etching treatment on the grid film to form a grid pattern with the second photoresist pattern;
and carrying out primary etching treatment on the second gate insulation pattern to form the first gate insulation pattern.
Optionally, before forming the active layer on the substrate base plate, the method further includes:
and sequentially forming a shielding layer and a buffer layer on the substrate base plate.
In a second aspect, an array substrate is provided, including:
a substrate base plate;
an active layer, a first gate insulation pattern, a gate pattern, an interlayer insulation layer and a source drain pattern are sequentially arranged on the substrate;
the upper surface of the first gate insulation pattern is provided with a protruding structure, the lower surface of the gate pattern is provided with a groove structure matched with the protruding structure in shape, and the orthographic projection of the gate pattern on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate.
Optionally, the array substrate further includes:
and the shielding layer and the buffer layer are sequentially arranged on the substrate base plate.
Optionally, the active layer is made of indium gallium zinc oxide.
In a third aspect, a display panel is provided, including: the array substrate of any of the second aspect.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
according to the manufacturing method of the array substrate, the array substrate and the display panel provided by the embodiment of the invention, the first gate insulation pattern and the gate electrode pattern are sequentially formed on the active layer, the projection structure is formed on the upper surface of the first gate insulation, and the groove structure matched with the projection structure in shape is formed on the lower surface of the gate electrode pattern, so that the orthographic projection of the gate electrode pattern on the substrate can cover the orthographic projection of the first gate insulation pattern on the substrate, the L DD area in the active layer is effectively eliminated, the parasitic resistance is effectively reduced, the on-state current of the TFT is effectively improved, meanwhile, the probability of breakage of the source and drain electrode pattern can be effectively reduced, and the light stability of the TFT can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1-1 is a schematic structural diagram of an array substrate provided in the prior art;
FIGS. 1-2 are schematic diagrams of a prior art method for forming a gate pattern with a photoresist pattern;
fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 3-1 is a flow chart of another method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 3-2 is a schematic diagram of forming a barrier layer and a buffer layer on a substrate according to an embodiment of the present invention;
fig. 3-3 is a schematic diagram of forming an active layer on a buffer layer according to an embodiment of the present invention;
fig. 3-4a are flow charts of a method for sequentially forming a first gate insulating pattern and a gate electrode pattern on an active layer according to an embodiment of the present invention;
fig. 3-4b are schematic views illustrating a gate insulating film formed on an active layer according to an embodiment of the present invention;
fig. 3-4c are flow charts of a method for forming a second gate insulation pattern according to an embodiment of the present invention;
FIGS. 3-4d are schematic diagrams illustrating the formation of a first photoresist pattern according to an embodiment of the present invention;
FIGS. 3-4e are schematic diagrams illustrating a second gate insulation pattern formed with a first photoresist pattern according to an embodiment of the present invention;
fig. 3 to 4f are schematic views illustrating a gate thin film formed on the second gate insulating pattern according to an embodiment of the present invention;
fig. 3-4g are flow charts of a method for forming a gate pattern and a first gate insulation pattern according to an embodiment of the present invention;
FIGS. 3-4h are schematic diagrams illustrating the formation of a second photoresist pattern according to an embodiment of the present invention;
FIGS. 3-4i are flow charts of a method for forming a gate pattern and a first gate insulation pattern with a second photoresist pattern according to an embodiment of the present invention;
FIGS. 3-4j are diagrams illustrating forming a gate pattern with a second photoresist pattern according to an embodiment of the present invention;
fig. 3-4k are exemplary diagrams for forming a first gate insulating pattern according to an embodiment of the present invention;
fig. 3 to 5 are schematic diagrams illustrating an interlayer insulating layer and a source/drain pattern sequentially formed on a gate pattern according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1-2, fig. 1-2 is a schematic diagram of forming a gate pattern with a photoresist pattern provided in the prior art, in order to reduce the probability of fracture of a source/drain pattern, it is necessary to ensure that slopes on two sides of a gate insulating pattern 05 are gentle and slopes on two sides of a gate pattern 06 are gentle, so that a photoresist pattern a formed after exposure and development processing of a photoresist on a gate film needs to have a certain radian, and after etching processing of the gate film, slopes on two sides of the obtained gate pattern 06 are gentle, and the slopes on two sides of the gate insulating pattern 05 can also be gentle by using the same manufacturing principle, so that forward projection areas of the gate insulating pattern 05 and the gate pattern 06 on an active layer 04 are sequentially reduced, and finally an on-state current of a TFT is small.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing an array substrate, as shown in fig. 2, where fig. 2 is a flowchart of the method for manufacturing an array substrate according to the embodiment of the present invention, and the method for manufacturing an array substrate may include:
And 203, sequentially forming an interlayer insulating layer and a source/drain electrode pattern on the gate electrode pattern.
The upper surface of the first gate insulation pattern is provided with a convex structure, the lower surface of the gate pattern is provided with a groove structure matched with the convex structure in shape, and the orthographic projection of the gate pattern on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate.
In summary, in the manufacturing method of the array substrate provided by the embodiment of the invention, the first gate insulation pattern and the gate electrode pattern are sequentially formed on the active layer, and because the raised structure is formed on the upper surface of the first gate insulation pattern and the groove structure matched with the raised structure in shape is formed on the lower surface of the gate electrode pattern, the orthographic projection of the gate electrode pattern on the substrate can cover the orthographic projection of the first gate insulation pattern on the substrate, so that the L DD area in the active layer is effectively eliminated, the parasitic resistance is effectively reduced, and the on-state current of the TFT is effectively improved.
Referring to fig. 3-1, fig. 3-1 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention, where the method for manufacturing an array substrate includes:
In practical application, the active layer in the array substrate provided by the embodiment of the invention is located at a lower layer, and the active layer is easily irradiated by an external light source from below the substrate, so that the threshold voltage of the TFT is very seriously drifted, and therefore, the shielding layer arranged below the active layer can effectively shield the active layer, thereby avoiding the irradiation of the external light source, avoiding the serious drift of the threshold voltage of the TFT, and further effectively improving the light stability of the TFT.
For example, referring to fig. 3-2, fig. 3-2 is a schematic diagram of forming a barrier layer and a buffer layer on a substrate according to an embodiment of the present invention, in which a barrier layer film is formed on a substrate 11 by any one of a plurality of methods, such as deposition, coating, sputtering, and the like, and then a barrier layer 12 is formed on the barrier layer film by a one-step patterning process, where the one-step patterning process may include: coating, exposing, developing, etching and stripping photoresist; the buffer layer 13 is formed on the base substrate 11 on which the barrier layer 12 is formed by any of various methods such as deposition, coating, sputtering, and the like.
Optionally, the active layer may be Indium Gallium Zinc Oxide (IGZO), Indium Tin Oxide (ITO), Indium-doped Zinc Oxide (IZO), or the like.
For example, referring to fig. 3-3, fig. 3-3 is a schematic diagram illustrating an active layer formed on a buffer layer according to an embodiment of the present invention. An active layer thin film is formed on the base substrate 11 on which the buffer layer 13 is formed by any of various means such as deposition, coating, sputtering, etc., and then an active layer 14 is formed on the active layer thin film through a one-time patterning process, which may include: photoresist coating, exposure, development, etching and photoresist stripping.
For example, referring to fig. 3 to 4a, fig. 3 to 4a are flowcharts of a method for sequentially forming a first gate insulating pattern and a gate electrode pattern on an active layer according to an embodiment of the present invention, where the method may include:
Optionally, the gate insulating film may be made of silicon dioxide, silicon nitride, or a high-k material.
For example, referring to fig. 3 to 4b, fig. 3 to 4b are schematic diagrams illustrating a gate insulating film formed on an active layer according to an embodiment of the present invention, wherein the gate insulating film 151 is formed on the substrate 11 on which the active layer 13 is formed by any one of a plurality of methods, such as deposition, coating, sputtering, and the like.
And step 3032, performing a composition process on the gate insulating layer film once to form a second gate insulating pattern.
For example, referring to fig. 3 to 4c, fig. 3 to 4c are flowcharts of a method for forming a second gate insulating pattern according to an embodiment of the present invention, where the method may include:
step a1, coating a first photoresist on the gate insulating film.
Alternatively, the first photoresist may be a positive photoresist.
Step a2, performing a first exposure process and a first development process on the first photoresist through the gate mask to form a first photoresist pattern.
For example, referring to fig. 3 to 4d, fig. 3 to 4d are schematic diagrams illustrating a first photoresist pattern formed according to an embodiment of the present invention, a first exposure process and a first development process are performed on a substrate 11 on which the first photoresist is formed through a gate mask to form a first photoresist pattern a 1.
Step a3, a first etching process is performed on the gate insulating film to form a second gate insulating pattern with a first photoresist pattern.
For example, referring to fig. 3 to 4e, fig. 3 to 4e are schematic diagrams illustrating a process of forming a second gate insulating pattern with a first photoresist pattern according to an embodiment of the present invention, wherein a first etching process is performed on a gate insulating film on a substrate 11 on which a first photoresist pattern a1 is formed to form a second gate insulating pattern 152 with a first photoresist pattern a 1. In the embodiment of the present invention, when performing the first etching process on the gate insulating film, the gate insulating film on the substrate 11, which is not covered by the first photoresist pattern a1, may be partially etched, so that a certain thickness of the gate insulating material still remains on the substrate 11, that is, the thickness d1 of the gate insulating material etched during the first etching process is smaller than the thickness d2 of the gate insulating film before the second gate insulating pattern 152 is etched (i.e., the gate insulating film).
And a4, stripping the first photoresist pattern to obtain a second gate insulation pattern.
In the embodiment of the invention, the orthographic projection of the second gate insulation pattern on the substrate base plate covers the orthographic projection of the active layer on the substrate base plate.
Alternatively, the gate film may be formed of a metal material, for example, the gate film is made of molybdenum (abbreviated as Mo), copper (abbreviated as Cu), aluminum (abbreviated as Al), or an alloy material.
For example, referring to fig. 3 to 4f, fig. 3 to 4f are schematic diagrams illustrating the formation of a gate thin film on the second gate insulating pattern according to an embodiment of the present invention, and the gate thin film 161 is formed on the substrate 11 on which the second gate insulating pattern 152 is formed by any one of a plurality of methods, such as deposition, coating, and sputtering.
And step 3034, performing a one-time composition process on the gate film and the second gate insulation pattern to form a gate pattern and a first gate insulation pattern.
For example, referring to fig. 3 to 4g, fig. 3 to 4g are flowcharts of a method for forming a gate pattern and a first gate insulation pattern according to an embodiment of the present invention, where the method may include:
step b1, coating a second photoresist on the gate film.
Alternatively, the second photoresist may be a positive photoresist.
And b2, performing a second exposure process and a second development process on the second photoresist through the grid mask to form a second photoresist pattern.
For example, referring to fig. 3 to 4h, fig. 3 to 4h are schematic diagrams illustrating a second photoresist pattern formation according to an embodiment of the present invention, a second exposure process and a second development process are performed on the second photoresist on the substrate 11 with the second photoresist formed thereon through a gate mask to form a second photoresist pattern a 2.
And b3, performing a second etching process on the gate film and the second gate insulation pattern to form a gate pattern and a first gate insulation pattern with a second photoresist pattern.
In an embodiment of the present invention, the second etching process may include: and (5) carrying out etching treatment twice. For example, referring to fig. 3 to 4i, fig. 3 to 4i are flowcharts of a method for forming a gate pattern and a first gate insulation pattern with a second photoresist pattern according to an embodiment of the present invention, where the method may include:
and b31, carrying out primary etching treatment on the gate film to form a gate pattern with a second photoresist pattern.
Referring to fig. 3 to 4j, fig. 3 to 4j are exemplary diagrams illustrating a method for forming a gate pattern with a second photoresist pattern according to an embodiment of the present invention, wherein a gate film is etched on a substrate 11 having the second photoresist pattern a2 formed thereon to form a gate pattern 16 with a second photoresist pattern a 2. In the embodiment of the present invention, when the gate film is subjected to the etching process once, the gate film on the substrate 11, which is not covered by the second photoresist pattern a2, may be completely etched to form the gate pattern 16 with the second photoresist pattern a 2.
And b32, carrying out primary etching treatment on the second gate insulation pattern to form a first gate insulation pattern.
Referring to fig. 3 to 4k, fig. 3 to 4k are diagrams illustrating a first gate insulating pattern formed according to an embodiment of the present invention, wherein a second gate insulating pattern is etched once on a substrate 11 on which a gate pattern 16 with a second photoresist pattern B2 is formed, so as to form a first gate insulating pattern 15. In the embodiment of the present invention, when the second gate insulating pattern is subjected to the etching process once, the second gate insulating pattern on the substrate 11, which is not covered by the second gate electrode pattern 16, may be completely etched to form the first gate insulating pattern 15.
And b4, stripping the second photoresist pattern to obtain a gate pattern and a first gate insulation pattern.
In the embodiment of the invention, the orthographic projection of the active layer on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate.
It should be noted that, because the thickness of the gate insulating layer material etched in step b32 is small, there is no slope on both sides of the first gate insulating pattern after etching, so that the orthographic projection of the gate electrode pattern 16 on the substrate 11 can cover the orthographic projection of the first gate insulating pattern 15 on the substrate 11.
In practical applications, the width d3 of the first photoresist pattern a1 formed in the step a2 is smaller than the width d4 of the second photoresist pattern a2 formed in the step b2, so that the upper surface of the first gate insulating pattern 15 obtained after the step 303 is formed with a protrusion structure, and the lower surface of the gate pattern 16 is formed with a groove structure matching the protrusion structure in shape. Since the first photoresist and the second photoresist are both positive photoresists, it is necessary to ensure that the exposure intensity of the first exposure process in step a2 needs to be greater than the exposure intensity of the second exposure process in step b 2.
It should be noted that, in the embodiment of the present invention, it is schematically illustrated that both the first photoresist and the second photoresist are positive photoresists, in practical applications, both the first photoresist and the second photoresist may also be negative photoresists, and at this time, the exposure intensity of the first exposure process in step a2 needs to be smaller than the exposure intensity of the second exposure process in step b2, so that the width of the first photoresist pattern is smaller than the width of the second photoresist pattern.
And 304, sequentially forming an interlayer insulating layer and a source/drain electrode pattern on the grid electrode pattern.
Optionally, the interlayer insulating layer may be made of silicon dioxide, silicon nitride, or a high-k material, and the drain pattern may be made of a metal material, for example, the source and drain pattern may be made of Mo, Cu, Al, or an alloy material.
For example, referring to fig. 3 to 5, fig. 3 to 5 are schematic diagrams illustrating that an interlayer insulating layer and a source/drain pattern are sequentially formed on a gate pattern, an interlayer insulating layer film is formed on a substrate 11 on which a gate pattern 16 is formed by any one of a plurality of deposition, coating, sputtering, and the like, and then an interlayer insulating layer 17 is formed on the interlayer insulating layer film by a one-step composition process, where the one-step composition process may include: coating, exposing, developing, etching and stripping photoresist; forming a source/drain thin film on the substrate 11 formed with the interlayer insulating layer 17 by any one of a plurality of methods such as deposition, coating, sputtering, and the like, and then forming a source/drain pattern 18 on the source/drain thin film by a one-step composition process, which may include: photoresist coating, exposure, development, etching and photoresist stripping.
In practical applications, after the steps of the foregoing embodiments, an array substrate may be manufactured, for example, referring to fig. 4, fig. 4 is a schematic structural diagram of the array substrate provided in an embodiment of the present invention, because a protruding structure is formed on an upper surface of the first gate insulating pattern 15, a groove structure matching the protruding structure in shape is formed on a lower surface of the gate pattern 16, and a distance from two ends of the gate pattern 16 to the active layer 14 is relatively small, a control capability of the gate pattern 16 on the gate control region 141 in the active layer 14 is effectively improved, and an on-state current of the TFT is further improved.
In the prior art, as shown in fig. 1-1, when the array substrate is disposed in an O L ED display panel, light L emitted from a light emitting layer in the O L ED display panel may pass through a side surface of a gate insulating layer 05 to a gate control region 041 in an active layer 04, and then a threshold voltage of a TFT may be shifted seriously, which may result in low light stability of the TFT.
In the embodiment of the invention, referring to fig. 4, when the array substrate is disposed in an O L ED display panel, since a protrusion structure is formed on the upper surface of the first gate insulating pattern 15, a groove structure matching the protrusion structure in shape is formed on the lower surface of the gate pattern 16, and the gate pattern 16 is opaque, light L emitted from the light-emitting layer in the OE L D display panel is shielded by the side surface of the gate pattern 16, so that light L can be effectively prevented from being incident on the gate control region 141 in the active layer 14, thereby preventing the threshold voltage of the TFT from being severely drifted, and further effectively improving the light stability of the TFT.
In summary, in the manufacturing method of the array substrate provided by the embodiment of the invention, the first gate insulation pattern and the gate electrode pattern are sequentially formed on the active layer, and the projection structure is formed on the upper surface of the first gate insulation pattern, and the groove structure matched with the projection structure in shape is formed on the lower surface of the gate electrode pattern, so that the orthographic projection of the gate electrode pattern on the substrate can cover the orthographic projection of the first gate insulation pattern on the substrate, thereby effectively eliminating the L DD region in the active layer, further effectively reducing the parasitic resistance, and effectively improving the on-state current of the TFT.
An embodiment of the present invention further provides an array substrate, where the structure of the array substrate may refer to fig. 4, and the array substrate may include:
a substrate 11.
An active layer 14, a first gate insulating pattern 15, a gate pattern 16, an interlayer insulating layer 17, and a source/drain pattern 18 are sequentially disposed on the substrate 11.
Wherein, the upper surface of the first gate insulation pattern 15 is provided with a convex structure, the lower surface of the gate pattern 16 is provided with a concave structure matched with the convex structure, and the orthographic projection of the gate pattern 15 on the substrate 11 covers the orthographic projection of the first gate insulation pattern 16 on the substrate 11.
Optionally, as shown in fig. 4, the array substrate may further include: a barrier layer 12 and a buffer layer 13 are provided in this order on the base substrate 11.
Optionally, the material of the active layer is IGZO, ITO, IZO, or the like.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific manufacturing process of the array substrate and the specific principle of the array substrate described above may refer to the corresponding process in the foregoing method embodiments, and details are not repeated herein.
In summary, according to the array substrate provided by the embodiment of the invention, the first gate insulation pattern and the gate electrode pattern are sequentially arranged on the active layer, and the projection structure is arranged on the upper surface of the first gate insulation pattern, and the groove structure matched with the projection structure in shape is arranged on the lower surface of the gate electrode pattern, so that the orthographic projection of the gate electrode pattern on the substrate can cover the orthographic projection of the first gate insulation pattern on the substrate, and the L DD area in the active layer is effectively eliminated, thereby effectively reducing the parasitic resistance, and effectively improving the on-state current of the TFT.
The display device can be any product or component with a display function, such as a liquid crystal panel, an O L ED display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A method for manufacturing an array substrate, the method comprising:
forming an active layer on a base substrate;
sequentially forming a first gate insulation pattern and a gate pattern on the active layer;
sequentially forming an interlayer insulating layer and a source/drain electrode pattern on the grid electrode pattern;
a convex structure is formed on the upper surface of the first gate insulation pattern, a groove structure matched with the convex structure in shape is formed on the lower surface of the gate pattern, and the orthographic projection of the gate pattern on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate;
the sequentially forming a first gate insulation pattern and a gate pattern on the active layer includes:
forming a gate insulating film on the active layer;
coating a first photoresist on the gate insulating layer film;
carrying out first exposure treatment and first development treatment on the first photoresist through a grid mask plate to form a first photoresist pattern;
performing first etching treatment on the gate insulating layer film to form a second gate insulating pattern with the first photoresist pattern;
stripping the first photoresist pattern to obtain a second gate insulation pattern;
forming a gate thin film on the second gate insulating pattern;
coating a second photoresist on the grid film;
carrying out second exposure treatment and second development treatment on the second photoresist through the grid mask plate to form a second photoresist pattern;
performing second etching treatment on the gate thin film and the second gate insulation pattern to form a gate pattern with the second photoresist pattern and the first gate insulation pattern;
stripping the second photoresist pattern to obtain the gate pattern and the first gate insulation pattern;
the first photoresist and the second photoresist are both positive photoresists, and the exposure intensity of the first exposure treatment is greater than that of the second exposure treatment so that the width of the first photoresist pattern is smaller than that of the second photoresist pattern;
or, the first photoresist and the second photoresist are both negative photoresists, and the exposure intensity of the first exposure treatment is smaller than that of the second exposure treatment, so that the width of the first photoresist pattern is smaller than that of the second photoresist pattern;
wherein, the orthographic projection of the second gate insulation pattern on the substrate base plate covers the orthographic projection of the active layer on the substrate base plate, and the orthographic projection of the active layer on the substrate base plate covers the orthographic projection of the first gate insulation pattern on the substrate base plate.
2. The method of claim 1, wherein the second etch process comprises: the etching treatment is carried out for two times,
the second etching treatment is performed on the gate thin film and the second gate insulation pattern to form a gate pattern with the second photoresist pattern and the first gate insulation pattern, and the method includes:
carrying out primary etching treatment on the grid film to form a grid pattern with the second photoresist pattern;
and carrying out primary etching treatment on the second gate insulation pattern to form the first gate insulation pattern.
3. The method of claim 1 or 2, wherein prior to forming the active layer on the base substrate, the method further comprises:
and sequentially forming a shielding layer and a buffer layer on the substrate base plate.
4. An array substrate prepared by the method of manufacturing an array substrate according to any one of claims 1 to 3, the array substrate comprising:
a substrate base plate;
an active layer, a first gate insulation pattern, a gate pattern, an interlayer insulation layer and a source drain pattern are sequentially arranged on the substrate;
the upper surface of the first gate insulation pattern is provided with a protruding structure, the lower surface of the gate pattern is provided with a groove structure matched with the protruding structure in shape, and the orthographic projection of the gate pattern on the substrate covers the orthographic projection of the first gate insulation pattern on the substrate.
5. The array substrate of claim 4, further comprising:
and the shielding layer and the buffer layer are sequentially arranged on the substrate base plate.
6. The array substrate of claim 4,
the active layer is made of indium gallium zinc oxide.
7. A display panel, comprising: an array substrate as claimed in any one of claims 4 to 6.
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| KR100192593B1 (en) * | 1996-02-21 | 1999-07-01 | 윤종용 | Fabrication method of polysilicon thin film transistor |
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