CN103219341B - A kind of array base palte and preparation method, display device - Google Patents
A kind of array base palte and preparation method, display device Download PDFInfo
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- CN103219341B CN103219341B CN201310116026.8A CN201310116026A CN103219341B CN 103219341 B CN103219341 B CN 103219341B CN 201310116026 A CN201310116026 A CN 201310116026A CN 103219341 B CN103219341 B CN 103219341B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 86
- 239000010409 thin film Substances 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 90
- 230000008569 process Effects 0.000 claims description 57
- 238000000059 patterning Methods 0.000 claims description 36
- 230000005611 electricity Effects 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 108
- 239000010408 film Substances 0.000 description 53
- 238000009413 insulation Methods 0.000 description 17
- 238000002161 passivation Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 9
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- 230000000694 effects Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000012780 transparent material Substances 0.000 description 6
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- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Embodiments provide a kind of array base palte and preparation method, display device, relate to Display Technique field, aperture opening ratio the thin film transistor (TFT) delay phenomenon avoiding transparent conductive material resistance to cause relatively greatly can be improved, thus meet the demand of high PPI product；This array base palte includes: thin film transistor (TFT), and described thin film transistor (TFT) includes gate electrode, source electrode and drain electrode and active layer；Further comprising the metallic conduction district being arranged at above or below described gate electrode, described metallic conduction district is for reducing the time delay that described thin film transistor (TFT) is opened；Wherein, the material of described gate electrode, described source electrode and described drain electrode is transparent conductive material.Manufacture for display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method,
Display device.
Background technology
At present, as it is shown in figure 1, array base palte includes the grid metal level of gate electrode 20, includes
The source and drain metal level of source electrode and drain electrode and pixel electrode 30；Due to forming array base
Grid metal level and the source and drain metal level of plate are opaque, cause aperture opening ratio to a certain degree reducing
?.
ADS (Advanced-Super Dimension Switch, senior super dimension field switch technology)
Display Technique has high-resolution, high permeability, low-power consumption, wide viewing angle, high opening due to it
The advantages such as rate are widely used, i.e. as it is shown in figure 1, form public electrode on array base palte
90。
But, along with market is to high PPI (Pixels per inch, the pixel that per inch is had
Number) exploitation of product, use the aperture opening ratio of the product that prior art produces to be difficult to meet demand,
Therefore, how to improve aperture opening ratio and become a new research direction.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method, display device, can carry
High aperture the thin film transistor (TFT) avoiding transparent conductive material resistance to cause relatively greatly postpone existing
As, thus meet the demand of high PPI product.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
On the one hand, it is provided that a kind of array base palte, including thin film transistor (TFT), described film crystal
Pipe includes gate electrode, source electrode and drain electrode and active layer；Further comprise and be arranged at
Metallic conduction district above or below described gate electrode, described metallic conduction district is used for reducing described
The time delay that thin film transistor (TFT) is opened；Wherein, described gate electrode, described source electrode and described
The material of drain electrode is transparent conductive material.
On the one hand, it is provided that a kind of display device, including above-mentioned array base palte.
On the other hand, it is provided that the preparation method of a kind of array base palte, including: on substrate formed
Thin film transistor (TFT), pixel electrode, described thin film transistor (TFT) includes gate electrode, source electrode and electric leakage
Pole and active layer；Further comprise: formed above or below described gate electrode and be used for
Reduce the metallic conduction district of described thin film transistor (TFT) trunon delay time；
Described gate electrode, source electrode and the drain electrode of being formed on substrate includes: formed on substrate
The described gate electrode of electrically conducting transparent material, described source electrode and described drain electrode.
Embodiments provide a kind of array base palte and preparation method, display device, this battle array
Row substrate includes being arranged on thin film transistor (TFT) on substrate, described thin film transistor (TFT) include gate electrode,
Source electrode and drain electrode and active layer；Further comprise: be arranged on described gate electrode
The metallic conduction district of side or lower section, described metallic conduction district is used for reducing described thin film transistor (TFT) and opens
The time delay opened；Wherein, described gate electrode, described source electrode and the material of described drain electrode
For transparent conductive material；So, by the gate electrode of original opaque metal material, described source electricity
Pole and described drain electrode replace with transparent conductive material (such as ITO), and be additionally provided with for
Reduce the described metallic conduction district of the time delay that described thin film transistor (TFT) is opened, can improve out
Mouth rate also avoids the thin film transistor (TFT) delay phenomenon that transparent conductive material resistance causes relatively greatly,
Thus meet the demand of high PPI product.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below by right
In embodiment or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that,
Accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art
From the point of view of, on the premise of not paying creative work, it is also possible to obtain the attached of other according to these accompanying drawings
Figure.
The schematic top plan view of a kind of array base palte that Fig. 1 provides for prior art；
The structural representation of a kind of bottom gate type array base palte that Fig. 2 provides for the embodiment of the present invention；
The structural representation of the another kind of bottom gate type array base palte that Fig. 3 provides for the embodiment of the present invention
Figure；
The structural representation of a kind of top gate type array base palte that Fig. 4 provides for the embodiment of the present invention；
The structural representation of the another kind of top gate type array base palte that Fig. 5 provides for the embodiment of the present invention
Figure；
The schematic top plan view of the array base palte that Fig. 6 provides for the embodiment of the present invention；
The preparation method of a kind of bottom gate type array base palte that Fig. 7 provides for the embodiment of the present invention one
Schematic flow sheet；
The one that Fig. 8～Figure 13 provides for the embodiment of the present invention one prepares bottom gate type array base palte
Process schematic；
The preparation method of a kind of bottom gate type array base palte that Figure 14 provides for the embodiment of the present invention two
Schematic flow sheet；
The one that Figure 15～Figure 19 provides for the embodiment of the present invention two prepares bottom gate type array base palte
Process schematic；
The preparation method of a kind of top gate type array base palte that Figure 20 provides for the embodiment of the present invention three
Schematic flow sheet；
The one that Figure 21～Figure 25 provides for the embodiment of the present invention three prepares top gate type array base palte
Process schematic.
Reference:
01-array base palte；10-substrate；20-gate electrode；30-pixel electrode；40-metallic conduction
District；50-gate insulation layer, 501-via；60-active layer；701-source electrode, 702-drain electrode；
80-passivation layer；90-public electrode.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is entered
Row clearly and completely describes, it is clear that described embodiment is only a part of embodiment of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
Have and make the every other embodiment obtained under creative work premise, broadly fall into present invention protection
Scope.
Embodiments provide a kind of array base palte 01, as shown in Figures 2 to 6, institute
State array base palte 01 to include: arrange thin film transistor (TFT) on the substrate 10, described thin film transistor (TFT)
Including gate electrode 20, source electrode 701 and drain electrode 702 and active layer 60；Further
Also include: be arranged at the metallic conduction district 40 above or below described gate electrode 20, described gold
Belong to conduction region be used for reducing described thin film transistor (TFT) such as TFT (Thin Film Transistor,
TFT) time delay of opening；Wherein, described gate electrode 20, described
The material of source electrode 701 and described drain electrode 702 is transparent conductive material.
Described transparent conductive material is preferably ITO (Indium Tin in embodiments of the present invention
Oxides, indium tin oxide) or IZO (Indium Zinc Oxide, indium-zinc oxide).
The material in described metallic conduction district 40 can be Al (aluminium), Mo (molybdenum) etc..
It should be noted that first, owing to transparent conductive material is the most now widely used
The resistance of ITO is relatively big, when the material of gate electrode 20 is ITO, in thin film transistor (TFT) position
Have the phenomenon that applied signal voltage postpones, therefore, for the embodiment of the present invention arranges metal
The purpose of conduction region 40 be reduce thin film transistor (TFT) open time delay, as it what
Situation is positioned at above gate electrode 20, and what situation is positioned at below gate electrode 20, can reduce thoroughly
The thin film transistor (TFT) delay phenomenon that bright conductive material resistance causes relatively greatly is as the criterion, i.e. can make thin
Film transistor reaches to open and close normally effect.
Second, in the embodiment of the present invention, indication is arranged at above or below described gate electrode 20
Metallic conduction district 40, refer to, the adjacent described gate electrode 20 in described metallic conduction district 40, and
It is positioned above or lower section.
By the schematic top plan view of Fig. 6 it can be seen that the array base palte that provides of the embodiment of the present invention only
At metallic conduction district 40 opaque, compared to existing technology, its opening has had the biggest proposing
High.
Embodiments providing a kind of array base palte 01, this array base palte includes being arranged on
Thin film transistor (TFT) on substrate 10, described thin film transistor (TFT) includes gate electrode 20, source electrode 701
With drain electrode 702 and active layer 60；Further comprise: be arranged at described gate electrode
Metallic conduction district 40 above or below in the of 20, described metallic conduction district is used for reducing described film
The time delay that transistor is opened；Wherein, described gate electrode 20, described source electrode 701 and
The material of described drain electrode 702 is transparent conductive material；So, by original opaque metal material
The gate electrode 20 of matter, described source electrode 701 and described drain electrode 702 replace with electrically conducting transparent
Material (such as ITO), and be additionally provided with for reducing the delay that described thin film transistor (TFT) is opened
The described metallic conduction district 40 of time, can improve aperture opening ratio and avoid transparent conductive material
The thin film transistor (TFT) delay phenomenon that resistance is relatively big and causes, thus meet the need of high PPI product
Ask.
The array base palte that the embodiment of the present invention provides can be ADS, inner plane change type
(In-Plane Switching is called for short IPS), Organic Electricity laser display (Organic
Electroluminesence Display, is called for short the life of the liquid crystal indicator of the types such as OLED type
Produce.Wherein, its core technology characteristic of ADS is described as: by gap electrode limit in same plane
The electric field that electric field produced by edge and gap electrode layer and plate electrode interlayer produce is formed many
Dimension electric field, makes in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can
Enough produce rotation, thus improve liquid crystal operating efficiency and increase light transmission efficiency.Senior super dimension
Field switch technology can improve TFT liquid crystal display (Thin Film
Transistor-Liquid Crystal Display, is called for short TFT-LCD) picture quality of product,
There is high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, nothing
The advantages such as water of compaction ripple (push Mura).OLED has self luminous characteristic, and its tool
There is visible angle big, save significantly on the advantages such as electric energy.
Therefore, for ADS type, as Fig. 2 is to shown in 6, and described array base palte also includes:
Public electrode 90.
Optionally, for bottom gate type array base palte, with reference to as shown in Figures 2 and 3, described gold
Belong to conduction region 40 to be arranged at above described gate electrode 20, and described metallic conduction district 40 and institute
State active layer 60 corresponding.
Optionally, for top gate type array base palte, with reference to as shown in Figure 4 and Figure 5, described gold
Belong to conduction region 40 to be arranged at below described gate electrode 20, and described metallic conduction district 40 and institute
State active layer 60 corresponding.
Here, described metallic conduction district 40 is corresponding with described active layer 60, specifically refers to, edge
The direction of vertical described array base palte looks over, described metallic conduction district 40 and described active layer
60 is overlapping, and overlap can be described metallic conduction district 40 and described active layer 60 1 here
The big area of area is little, and what i.e. area was less be positioned at area is bigger, it is also possible to be described
Metallic conduction district 40 is equal with described active layer 60 size, can realize maximum open rate
And the thin film transistor (TFT) unlatching delay phenomenon avoiding transparent conductive material resistance to cause relatively greatly is
Standard, i.e. meets maximum open rate and makes thin film transistor (TFT) reach normally to open and close effect i.e.
Can.
Due to, the resistivity of general ITO is about 0.55, and the resistivity of Al or Mo is about 0.12,
After gate material is such as changed into ITO, the material of corresponding grid line is also ITO so that
Resistivity on grid line is relatively big, causes grid line can postpone, after opening, the speed that between source and drain, raceway groove is opened
Degree, thus cause affecting display effect；When above gate electrode 20 and with described active layer 60
Corresponding position arranges described metallic conduction district 40, during its material for example, Al or Mo, and Ke Yiju
Resistivity on the grid line of reduction corresponding position, portion, thus reduce prolonging of described thin film transistor (TFT) unlatching
Time late.
Further, it is contemplated that in the preparation process of actual array base palte, if in order to further
Increase aperture opening ratio, the size of described active layer 60 can meet normal tft open
In the case of closing effect, that may do is the least, therefore, and the area of described active layer 60
Depending on need to be according to actual conditions.
For the area in described metallic conduction district 40, then depending on needing the area according to active layer 60,
The time delay opened for the described thin film transistor (TFT) of maximized reduction, in this step, excellent
Choosing, as shown in Figures 2 to 5, the area in described metallic conduction district 40 with active layer 60 is set
It is set to equal.
Optionally, owing to the material of gate electrode 20 is electrically conducting transparent material, when this electrically conducting transparent
When material (is such as ITO) as the material of pixel electrode 30, described gate electrode 20
Can be formed by a patterning processes with described pixel electrode 30, i.e. described gate electrode 20 He
Described pixel electrode 30 is positioned at same layer；So can reduce patterning processes herein, cost-effective.
Additionally, due to the material of described source electrode 701 and described drain electrode 702 is electrically conducting transparent
Material, when this electrically conducting transparent material (is such as ITO) as the material of pixel electrode 30
Time, described source electrode 701, drain electrode 702 and described pixel electrode 30 also can be by once
Patterning processes is formed, i.e. described source electrode 701, drain electrode 702 and described pixel electrode 30
It is positioned at same layer；The most also patterning processes can be reduced herein, cost-effective.
Embodiments providing a kind of array base palte 01, this array base palte includes being arranged on
Pixel electrode 30, public electrode 90, gate electrode 20, source electrode 701 and electric leakage on substrate
Pole 702, active layer 60 and metallic conduction district 40, described metallic conduction district 40 is with described
Active layer 60 is corresponding, and is bottom gate type or top gate type according to array base palte and is led by described metal
Electricity district 40 is arranged on above or below described gate electrode 20, described gate electrode 20, described source
The material of electrode 701 and described drain electrode 702 is transparent conductive material；Thus it is possible, on the one hand,
The array base palte provided due to the embodiment of the present invention uses ADS technology, can increase aperture opening ratio；
On the other hand, by the gate electrode 20 of original opaque metal material, described source electrode 701 and
Described drain electrode 702 replaces with transparent conductive material (such as ITO), and is additionally provided with and institute
State the described metallic conduction district 40 of active layer 60 correspondence, aperture opening ratio can be improved further and keep away
Exempt from the thin film transistor (TFT) delay phenomenon that transparent conductive material resistance causes relatively greatly, thus met
The demand of high PPI product.
Embodiments provide a kind of display device, including to the color membrane substrates after box and battle array
Row substrate, wherein, described array base palte can be the array base palte 01 of any of the above-described kind.Institute
Stating display device can be liquid crystal display, LCD TV, digital camera, mobile phone, flat board electricity
Brains etc. have product or the parts of any display function.
Embodiments providing the preparation method of a kind of array base palte, the method includes:
Forming thin film transistor (TFT), pixel electrode 30 on substrate, described thin film transistor (TFT) includes gate electrode
20, source electrode 701 and drain electrode 702 and active layer 60；Method described further is also wrapped
Include: formed above or below described gate electrode 20 and be used for reducing the unlatching of described thin film transistor (TFT)
The metallic conduction district 40 of time delay.
Wherein said gate electrode 20, source electrode 701 and the drain electrode 702 of being formed on substrate wraps
Include: on substrate, form the described gate electrode 20 of electrically conducting transparent material, described source electrode 701
With described drain electrode 702.
Embodiments providing the preparation method of a kind of array base palte, the method includes:
Forming thin film transistor (TFT), pixel electrode 30 on substrate, described thin film transistor (TFT) includes gate electrode
20, source electrode 701 and drain electrode 702 and active layer 60；Method described further is also wrapped
Include: formed above or below described gate electrode 20 and be used for reducing the unlatching of described thin film transistor (TFT)
The metallic conduction district 40 of time delay, described gate electrode 20, described source electrode 701 and described
The material of drain electrode 702 is transparent conductive material；So, by original opaque metal material
Gate electrode 20, described source electrode 701 and described drain electrode 702 replace with transparent conductive material
(such as ITO), and be additionally provided with for reducing the time delay that described thin film transistor (TFT) is opened
Described metallic conduction district 40, aperture opening ratio can be improved and avoid transparent conductive material resistance
The thin film transistor (TFT) delay phenomenon caused relatively greatly, thus meet the demand of high PPI product.
Preferably, described method also includes: form public electrode 90 on substrate.So,
Aperture opening ratio can be increased further.
For bottom gate type array base palte, optionally, its preparation method specifically may include that
Step 1, make transparent conductive film on the substrate 10, at a patterning processes
Reason forms described gate electrode 20 and described pixel electrode 30.
Herein, this transparent conductive film can be such as ITO, say, that described gate electrode
20 are also made up of ITO.As such, it is possible to by a patterning processes, i.e. use and i.e. include
Gate electrode 20 pattern includes that again the mask plate of pixel electrode 30 pattern is exposed technique, thus
Certain area at substrate concurrently forms gate electrode 20 and described pixel electrode 30.
So, described gate electrode 20 and described pixel electrode 30 are processed by a patterning processes
Formed, the number of times of patterning processes can be reduced, cost-effective.
Additionally, refer only to gate electrode 20 here, but in actual fabrication process, forming grid
While electrode 20, also can form the grid line electrically connected with gate electrode 20 and grid line lead-in wire etc.,
It is not detailed at this.
Step 2, on the substrate completing abovementioned steps, on described gate electrode 20 formed institute
State metallic conduction district 40, have described in described metallic conduction district 40 is to be formed with following step 4
Active layer 60 is corresponding.
Here the forming position according to active layer 60 is needed to determine the formation position in metallic conduction district 40
Put, i.e. need first to determine which region that active layer 60 is positioned at substrate, further according to active layer 60
Position, determines the forming position in metallic conduction district 40.
The material in metallic conduction district 40 can be Al.The area in described metallic conduction district 40 is big
Little need to be according to the size of described active layer 60 depending on, for the area of described active layer 60
With the area in described metallic conduction district 40 with can be on the basis of improving aperture opening ratio, it is to avoid transparent
The thin film transistor (TFT) delay phenomenon that conductive material resistance causes relatively greatly is as the criterion, and film can be made brilliant
Body pipe reaches to open and close normally effect.
Step 3, on the substrate completing abovementioned steps, form described gate insulation layer 50.
Step 4, on the substrate completing abovementioned steps, form described active layer 60.
Step 5, on the substrate completing abovementioned steps, form source electrode 701 and drain electrode 702.
Can also include further:
Step 6, on the substrate completing abovementioned steps, form described passivation layer 80 and described
Public electrode 90.
Embodiment one, embodiments provides the preparation side of a kind of bottom gate type array base palte
Method, as it is shown in fig. 7, comprises following steps:
S101, make transparent conductive film on the substrate 10, processed by a patterning processes
Form gate electrode 20 as shown in Figure 8 and pixel electrode 30.
Concrete, it is possible to use chemical vapor deposition method deposits a layer thickness on whole substrate and existsArriveBetween transparent conductive film layer, wherein conventional transparent conductive film can
Think ITO or IZO film；Then on described transparent conductive film, coat a layer photoetching glue,
And utilization i.e. includes that gate electrode 20 pattern includes that again the mask plate of pixel electrode 30 pattern is to formation
The substrate having photoresist is exposed, and after developing, etching, the certain area at substrate forms institute
State gate electrode 20 and described pixel electrode 30.Certainly, also formation electrically connects with gate electrode 20
Grid line and grid line lead-in wire.
S102, on the substrate completing step S101, make conductive metal film, by one
Secondary patterning processes processes the metallic conduction district 40 formed on described gate electrode 20 as shown in Figure 9, institute
The described active layer 60 stating metallic conduction district 40 to be formed with following step S104 is corresponding.
Concrete, it is possible to use chemical vapor deposition method deposit thickness on substrate is to be aboutArriveAl material film, then on described Al material film coat photoetching
Glue, and utilize common mask plate that substrate is exposed, develop, etch formation and be positioned at described
Metallic conduction district 40 above gate electrode 20.
Here, in the preparation process of actual array base palte, if in order to further increase opening
Rate, the size of described active layer 60 can meet normal tft opening and closing effect
In the case of, that may do is the least, and therefore, the area of described active layer 60 need to be according to reality
Depending on situation.
For the area in described metallic conduction district 40, then depending on needing the area according to active layer 60,
The time delay opened for the described thin film transistor (TFT) of maximized reduction, thus avoid film brilliant
Body pipe delay phenomenon, in this step, it is preferred that described metallic conduction district 40 and active layer 60
Area equation.
S103, on the substrate completing step S102, make insulation film, by a structure
Figure PROCESS FOR TREATMENT forms gate insulation layer 50 as shown in Figure 10, and described gate insulation layer 50 includes
Via 501.
Concrete, it is possible to use chemical vapor deposition method successive sedimentation thickness on substrate isExtremelyInsulation film, the material of insulation film is typically silicon nitride, it is possible to
To use silica and silicon oxynitride etc., on described insulation film, then coat photoresist, and
Utilize common mask plate that substrate is exposed, develop, etch the formation grid with via 501
Insulating barrier 50.
S104, on the substrate completing step S103, make active layer film, by once
Patterning processes process forms active layer 60 as shown in figure 11.
Concrete, it is possible to use chemical vapor deposition method deposit thickness on substrate is
ExtremelyMetal oxide semiconductor films, then at metal oxide semiconductor films
One layer of photoresist of upper coating light, and utilize common mask plate substrate to be exposed, develop, carve
Erosion is formed and is positioned at the active layer 60 above described gate electrode 20.
S105, on the substrate completing step S104, make transparent conductive film, by one
Secondary patterning processes process forms source electrode 701 as shown in figure 12 and drain electrode 702, described
Drain electrode 702 is electrically connected with described pixel electrode 30 by described via 501.
Certainly, here forming described source electrode 701 and drain electrode 702 while, number is also formed
According to line, data cable lead wire.
Concrete, it is possible to use chemical vapor deposition method deposits a layer thickness on whole substrate and existsExtremelyBetween transparent conductive film, its conventional transparent conductive film is permissible
For ITO or IZO film；Then on described transparent conductive film, coat a layer photoetching glue,
And utilize common mask plate that substrate is exposed, develop, etch formation source electrode 701 and
Drain electrode 702, described drain electrode 702 is by described via 501 and described pixel electrode 30
Electrical connection.
S106, on the substrate completing step S105, make passivation layer film, formed as figure
Passivation layer 80 shown in 13.
Concrete, a layer thickness can be coated on whole substrate and existArrive's
Passivation layer film, its material is typically silicon nitride or transparent with machine resin material.
S107, on the substrate completing step S106, make transparent conductive film, by one
Secondary patterning processes process is formed with reference to the public electrode 90 shown in Fig. 2.
Embodiments provide the preparation method of a kind of bottom gate type array base palte, the method bag
Include: on substrate, sequentially form gate electrode 20 and pixel electrode 30, metallic conduction district 40, grid
Insulating barrier 50, active layer 60, source electrode 701 and drain electrode 702, passivation layer 80 and
Public electrode 90, wherein said metallic conduction district 40 be positioned at above described gate electrode 20 and with
Described active layer 60 is corresponding, and the area of described metallic conduction district 40 and described active layer 60
The most equal, described gate electrode 20, source electrode 701 and drain electrode 702 are and described pixel electricity
The identical material in pole 30；So, increasing aperture opening ratio and avoiding transparent conductive material (such as ITO)
While the thin film transistor (TFT) delay phenomenon that resistance is relatively big and causes, due to gate electrode 20 and picture
Element electrode 30 is formed by a patterning processes, can reduce patterning processes number of times, cost-effective.
For bottom gate type array base palte, optionally, its preparation method the most specifically may include that
Step 1, form described gate electrode 20 on the substrate 10.
Step 2, on the substrate completing abovementioned steps, on described gate electrode 20 formed institute
State metallic conduction district 40, have described in described metallic conduction district 40 is to be formed with following step 4
Active layer 60 is corresponding.
Step 3, on the substrate completing abovementioned steps, form described gate insulation layer 50.
Step 4, on the substrate completing abovementioned steps, form described active layer 60.
Step 5, on the substrate completing abovementioned steps, make transparent conductive film, by one
Secondary patterning processes process forms described source electrode 701, drain electrode 702 and described pixel electrode 30.
Herein, this transparent conductive film can be ITO, say, that described source electrode 701
Also it is made up of ITO with drain electrode 702.As such, it is possible to by a patterning processes, i.e.
Use and i.e. include that source electrode 701 and drain electrode 702 pattern include again pixel electrode 30 pattern
Mask plate is exposed technique, thus forms source electrode 701, electric leakage at the certain area of substrate
Pole 702 and pixel electrode 30.Certainly, described source electrode 701 and drain electrode 702 are being formed
Meanwhile, data wire, data cable lead wire are also formed.
Here, described source electrode 701, drain electrode 702 and pixel electrode 30 are by a structure
Figure technique is formed, it is possible to reduce the number of times of patterning processes, cost-effective.
Further, described method can also include:
Step 6, on the substrate completing abovementioned steps, form described passivation layer 80 and described
Public electrode 90.
Embodiment two, embodiments provides the preparation side of a kind of bottom gate type array base palte
Method, as shown in figure 14, comprises the steps:
S201, make transparent conductive film on the substrate 10, processed by a patterning processes
Form gate electrode 20 as shown in figure 15.
Certainly, here while forming gate electrode 20, also formed and electrically connect with gate electrode 20
Grid line and grid line lead-in wire.
S202, on the substrate completing step S201, make conductive metal film, by one
Secondary patterning processes processes the metallic conduction district 40 formed on described gate electrode 20 as shown in figure 16,
The described active layer 60 that described metallic conduction district 40 is to be formed with following step S204 is corresponding.
Here the forming position according to active layer 60 is needed to determine the formation position in metallic conduction district 40
Put, i.e. need first to determine which region that active layer 60 is positioned at substrate, further according to active layer 60
Position, determines the forming position in metallic conduction district 40.
Additionally, in the preparation process of actual array base palte, if in order to further increase opening
Rate, the size of described active layer 60 can meet normal tft opening and closing effect
In the case of, that may do is the least, and therefore, the area of described active layer 60 need to be according to reality
Depending on situation.
For the area in described metallic conduction district 40, then depending on needing the area according to active layer 60,
The time delay opened for the described thin film transistor (TFT) of maximized reduction, thus avoid film brilliant
Body pipe delay phenomenon, in this step, it is preferred that described metallic conduction district 40 and active layer 60
Area equation.
S203, on the substrate completing step S202, make insulation film, formed such as Figure 17
Shown gate insulation layer 50.
S204, on the substrate completing step S203, make active layer film, by once
Patterning processes process forms active layer 60 as shown in figure 18.
S205, on the substrate completing step S204, make transparent conductive film, by one
Secondary patterning processes process formed source electrode 701 as shown in figure 19 and drain electrode 702 and
Pixel electrode 30.
Concrete, it is possible to use chemical vapor deposition method deposits a layer thickness on whole substrate and existsArriveBetween transparent conductive film layer, wherein conventional transparent conductive film can
Think ITO or IZO film；Then on described transparent conductive film, coat a layer photoetching glue,
And utilization i.e. includes that source electrode 701 and drain electrode 702 pattern include again pixel electrode 30 pattern
Mask plate the substrate being formed with photoresist is exposed, after developing, etching, at substrate
Certain area forms described source electrode 701 and drain electrode 702 and described pixel electrode 30.
Certainly, here forming described source electrode 701 and drain electrode 702 while, also form data wire,
Data cable lead wire.
S206, on the substrate completing step S205, formed with reference to passivation as shown in Figure 3
Layer 80 and public electrode 90.
Embodiments provide the preparation method of a kind of bottom gate type array base palte, the method bag
Include: on substrate, sequentially form gate electrode 20, metallic conduction district 40, gate insulation layer 50, have
Active layer 60, source electrode 701, drain electrode 702 and pixel electrode 30, passivation layer 80 and
Public electrode 90, wherein said metallic conduction district 40 be positioned at above described gate electrode 20 and with
Described active layer 60 is corresponding, and the area of described metallic conduction district 40 and described active layer 60
The most equal, described gate electrode 20, source electrode 701 and drain electrode 702 are and described pixel electricity
The identical material in pole 30；So, increasing aperture opening ratio and avoiding transparent conductive material (such as ITO)
While the thin film transistor (TFT) delay phenomenon that resistance is relatively big and causes, due to source electrode 701 and leakage
Electrode 702 is formed by a patterning processes with pixel electrode 30, can reduce patterning processes
Number, cost-effective.
For top gate type array base palte, optionally, its preparation method includes:
Step 1, on substrate, make transparent conductive film, process shape by patterning processes
Become described source electrode 701, drain electrode 702 and described pixel electrode 30.
Here, described source electrode 701, drain electrode 702 and pixel electrode 30 are by a structure
Figure technique is formed, it is possible to reduce the number of times of patterning processes, cost-effective.
Step 2, on the substrate completing abovementioned steps, form described active layer 60.
Step 3, on the substrate completing abovementioned steps, form described gate insulation layer 50.
Step 4, on the substrate completing abovementioned steps, form described metallic conduction district 40, institute
State metallic conduction district 40 corresponding with described active layer 60.
Step 5, on the substrate completing abovementioned steps, shape in described metallic conduction district 60
Become described gate electrode 20.
Further, described method can also include:
Step 6, on the substrate completing abovementioned steps, form described passivation layer 80 and described
Public electrode 90.
Embodiments provide a kind of top gate type array base palte, as shown in figure 20, this battle array
Row substrate comprises the steps:
S301, on substrate make transparent conductive film, by a patterning processes process formed
Source electrode 701 as shown in figure 21 and drain electrode 702 and pixel electrode 30.
Concrete, it is possible to use chemical vapor deposition method deposits a layer thickness on whole substrate and existsArriveBetween transparent conductive film layer, wherein conventional transparent conductive film can
Think ITO or IZO film；Then on described transparent conductive film, coat a layer photoetching glue,
And utilization i.e. includes that source electrode 701 and drain electrode 702 pattern include again pixel electrode 30 pattern
Mask plate the substrate being formed with photoresist is exposed, after developing, etching, at substrate
Certain area forms described source electrode 701 and drain electrode 702 and described pixel electrode 30.
Certainly, forming described source electrode 701 and drain electrode 702 while, also form data wire, number
Go between according to line.
Here, described source electrode 701, drain electrode 702 and pixel electrode 30 are by a structure
Figure technique is formed, it is possible to reduce the number of times of patterning processes, cost-effective.
S302, on the substrate completing step S301, make active layer film, by once
Patterning processes process forms active layer 60 as shown in figure 22.
S303, on the substrate completing step S302, make insulation film, formed such as Figure 23
Shown gate insulation layer 50.
S304, on the substrate completing step S303, make conductive metal film, by one
Secondary patterning processes process forms metallic conduction district 40 as of fig. 24, described metallic conduction district 40
Corresponding with described active layer 60.
Here, in the preparation process of actual array base palte, if in order to further increase opening
Rate, the size of described active layer 60 can meet normal tft opening and closing effect
In the case of, that may do is the least, and therefore, the area of described active layer 60 need to be according to reality
Depending on situation.
For the area in described metallic conduction district 40, then depending on needing the area according to active layer 60,
The time delay opened for the described thin film transistor (TFT) of maximized reduction, thus avoid film brilliant
Body pipe delay phenomenon, in this step, it is preferred that described metallic conduction district 40 and active layer 60
Area equation.
S305, on the substrate completing step S304, make transparent conductive film, by one
Secondary patterning processes processes and forms gate electrode as shown in figure 25 above described metallic conduction district 40
20。
S306, on the substrate completing step S305, formed with reference to passivation as shown in Figure 3
Layer 80 and public electrode 90.
Embodiments provide the preparation method of a kind of top gate type array base palte, the method bag
Include: on substrate, sequentially form source electrode 701, drain electrode 702 and pixel electrode 30, active
Floor 60, gate insulation layer 50, metallic conduction district 40, gate electrode 20, passivation layer 80 and
Public electrode 90, wherein said metallic conduction district 40 be positioned at below described gate electrode 20 and with
Described active layer 60 is corresponding, and the area of described metallic conduction district 40 and described active layer 60
The most equal, described gate electrode 20, source electrode 701 and drain electrode 702 are and described pixel electricity
The identical material in pole 30；So, increasing aperture opening ratio and avoiding transparent conductive material (such as ITO)
While the thin film transistor (TFT) delay phenomenon that resistance is relatively big and causes, due to source electrode 701 and leakage
Electrode 702 is formed by a patterning processes with pixel electrode 30, can reduce patterning processes
Number, cost-effective.
Certainly, for top gate type array base palte, optionally, its preparation method can also include:
Step 1, on substrate, make described source electrode 701 and described drain electrode 702.
Step 2, on the substrate completing abovementioned steps, form described active layer 60；
Step 3, on the substrate completing abovementioned steps, form described gate insulation layer 50.
Step 4, on the substrate completing abovementioned steps, form described metallic conduction district 40, institute
State metallic conduction district 40 corresponding with described active layer 60.
Step 5, on the substrate completing abovementioned steps, on substrate make transparent conductive film,
Described gate electrode 20 and described pixel electrode 30 is formed by a patterning processes process.
Further, described method can also include:
Step 6, on the substrate completing abovementioned steps, form described passivation layer 80 and described
Public electrode 90.
Array base palte as shown in Figure 4 can be prepared as by above-mentioned steps, not repeat them here.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is also
Being not limited to this, any those familiar with the art is at the technology model that the invention discloses
In enclosing, change can be readily occurred in or replace, all should contain within protection scope of the present invention.
Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (9)
1. an array base palte, including: thin film transistor (TFT), described thin film transistor (TFT) includes gate electrode, source electricity
Pole and drain electrode and active layer；It is characterized in that, also include being arranged at above or below described gate electrode
Metallic conduction district；
Wherein, the material of described gate electrode, described source electrode and described drain electrode is transparent conductive material, institute
State metallic conduction district corresponding with described active layer, described metallic conduction district and the area equation of described active layer；
Described transparent conductive material is indium tin oxide ITO or indium-zinc oxide IZO.
Array base palte the most according to claim 1, it is characterised in that described metallic conduction district is arranged at
Above described gate electrode, and described metallic conduction district is corresponding with described active layer；Wherein said array base palte is
Bottom gate type array base palte；Or,
Described metallic conduction district is arranged at below described gate electrode, and described metallic conduction district and described active layer
Corresponding；Wherein said array base palte is top gate type array base palte.
Array base palte the most according to claim 1 and 2, it is characterised in that also include pixel electrode；
And described pixel electrode and described gate electrode are positioned at same layer, or described pixel electrode and described source electrode, institute
State drain electrode and be positioned at same layer.
Array base palte the most according to claim 1 and 2, it is characterised in that also include: public electrode.
5. a display device, it is characterised in that include the array base described in any one of Claims 1-4
Plate.
6. a preparation method for array base palte, including: on substrate, form thin film transistor (TFT), pixel electrode,
Described thin film transistor (TFT) includes gate electrode, source electrode and drain electrode and active layer；It is characterized in that, also
Including: forming metallic conduction district above or below described gate electrode, described metallic conduction district is active with described
Layer is corresponding, described metallic conduction district and the area equation of described active layer；
Described gate electrode, source electrode and the drain electrode of being formed on substrate includes: form electrically conducting transparent on substrate
The described gate electrode of material, described source electrode and described drain electrode；Described transparent conductive material is the oxidation of indium tin
Thing ITO or indium-zinc oxide IZO.
Preparation method the most according to claim 6, it is characterised in that for bottom gate type array base palte,
Described metallic conduction district is formed at below described gate electrode, and described metallic conduction district is corresponding with described active layer；
Or,
For top gate type array base palte, described metallic conduction district is formed at below described gate electrode, and described gold
Belong to conduction region corresponding with described active layer.
8. according to the preparation method described in claim 6 or 7, it is characterised in that described gate electrode and described
Pixel electrode is formed by a patterning processes process；Or,
Described source electrode, described drain electrode and described pixel electrode are formed by a patterning processes process.
9. according to the method described in claim 6 or 7, it is characterised in that also include: formed on substrate
Public electrode.
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| PCT/CN2013/088968 WO2014161349A1 (en) | 2013-04-03 | 2013-12-10 | Array substrate and preparation method therefor, and display device |
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| CN105514034B (en) * | 2016-01-13 | 2018-11-23 | 深圳市华星光电技术有限公司 | The production method of TFT substrate |
| CN111146264B (en) * | 2020-02-06 | 2023-08-18 | 合肥鑫晟光电科技有限公司 | OLED display substrate, manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101128939A (en) * | 2005-02-28 | 2008-02-20 | 卡西欧计算机株式会社 | Thin film transistor panel |
| CN102237372A (en) * | 2010-04-30 | 2011-11-09 | 三星移动显示器株式会社 | Array substrate and method of fabricating the same |
| CN102544029A (en) * | 2012-02-07 | 2012-07-04 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
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| KR100583311B1 (en) * | 2003-10-14 | 2006-05-25 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display panel and fabricating method thereof |
| KR101112547B1 (en) * | 2005-01-18 | 2012-03-13 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
| CN101615582B (en) * | 2009-06-25 | 2012-02-15 | 浙江大学 | Method for preparing transparent thin-film transistor of alloyed oxide |
| CN103219341B (en) * | 2013-04-03 | 2016-08-31 | 北京京东方光电科技有限公司 | A kind of array base palte and preparation method, display device |
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| CN101128939A (en) * | 2005-02-28 | 2008-02-20 | 卡西欧计算机株式会社 | Thin film transistor panel |
| CN102237372A (en) * | 2010-04-30 | 2011-11-09 | 三星移动显示器株式会社 | Array substrate and method of fabricating the same |
| CN102544029A (en) * | 2012-02-07 | 2012-07-04 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
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