CN107393933A - Manufacture method, array base palte and the display panel of array base palte - Google Patents
Manufacture method, array base palte and the display panel of array base palte Download PDFInfo
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- CN107393933A CN107393933A CN201710640506.2A CN201710640506A CN107393933A CN 107393933 A CN107393933 A CN 107393933A CN 201710640506 A CN201710640506 A CN 201710640506A CN 107393933 A CN107393933 A CN 107393933A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 141
- 239000010410 layer Substances 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 59
- 238000001259 photo etching Methods 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 35
- 238000012545 processing Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 238000011161 development Methods 0.000 claims description 13
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000011787 zinc oxide Substances 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 55
- 238000010586 diagram Methods 0.000 description 24
- 230000015572 biosynthetic process Effects 0.000 description 15
- 238000000151 deposition Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of manufacture method of array base palte, array base palte and display panel, belong to display technology field.This method includes：Active layer is formed on underlay substrate；First grid insulation patterns and gate patterns are sequentially formed on active layer；Interlayer insulating film and source-drain electrode figure are sequentially formed on gate patterns；Wherein, the upper surface of first grid insulation patterns is formed with bulge-structure, and the lower surface of gate patterns is formed with the groove structure with bulge-structure form fit, orthographic projection covering first grid insulation patterns orthographic projection on underlay substrate of the gate patterns on underlay substrate.The present invention covers orthographic projection of the first grid insulation patterns on underlay substrate by orthographic projection of the gate patterns on underlay substrate, effectively raises TFT ON state current.The present invention is used in display panel.
Description
Technical field
The present invention relates to display technology field, the more particularly to a kind of manufacture method of array base palte, array base palte and display
Panel.
Background technology
Oxide semiconducting material is because its carrier mobility is high, preparation temperature is low, electricity uniformity is good, to visible light transmission
The advantage such as low with cost, it is considered to be best suitable for driving Organic Light Emitting Diode (English：Organic Light-Emitting
Diode；Referred to as：OLED thin film transistor (TFT) (English)：Thin-film transistor；Referred to as：TFT semiconductor active)
One of material, oxide TFT is referred to as using TFT made of oxide semiconductor, oxide TFT has been widely used at present
In OLED display panel.
Because top gate type TFT ghost effects are less, therefore most of oxide TFT is top gate type TFT at present, wherein,
Ghost effect refers to the phenomenon that parasitic capacitance is formed between the grid in TFT and source-drain electrode.For example, it refer to Fig. 1-1, Fig. 1-1
It is a kind of structural representation for array base palte that prior art provides, the array base palte can include：Underlay substrate 01, barrier bed
02nd, cushion 03, active layer 04, gate insulation figure 05, gate patterns 06, interlayer insulating film 07 and source-drain electrode figure 08, this has
Active layer 04 can be divided into grid-control region 041, lightly doped drain (English：Lightly Doped Drain；Referred to as：LDD) region
042 and conductor area 043, wherein, the region of orthographic projection of the gate patterns 06 on active layer 04 is grid-control area in active layer 04
Domain 041, the region not covered by orthographic projection of the gate insulation figure 05 on active layer 04 in active layer 04 is conductor region
043, the region in active layer 04 between conductor region 043 and grid-control region 041 is LDD region domain 042.
During the present invention is realized, inventor has found that prior art at least has problems with：
As shown in figure 1, due to being influenceed by manufacturing process, gate insulation figure 05 and gate patterns 06 are on active layer 04
Frontal projected area be sequentially reduced, cause the width d01 in LDD region domain 042 to increase, therefore dead resistance is larger, and then cause TFT
ON state current it is smaller.
The content of the invention
In order to solve the TFT of prior art ON state current compared with minor issue, the embodiments of the invention provide a kind of array base
Manufacture method, array base palte and the display panel of plate.The technical scheme is as follows：
First aspect, there is provided a kind of manufacture method of array base palte, methods described include：
Active layer is formed on underlay substrate；
First grid insulation patterns and gate patterns are sequentially formed on the active layer；
Interlayer insulating film and source-drain electrode figure are sequentially formed on the gate patterns；
Wherein, the upper surface of the first grid insulation patterns is formed with bulge-structure, the lower surface shape of the gate patterns
The groove structure of bulge-structure form fit described in Cheng Youyu, orthographic projection covering of the gate patterns on the underlay substrate
Orthographic projection of the first grid insulation patterns on the underlay substrate.
Optionally, it is described to sequentially form first grid insulation patterns and gate patterns on the active layer, including：
Gate insulation layer film is formed on the active layer；
Patterning processes are performed to the gate insulation layer film, to form second gate insulation patterns；
Grid film is formed on the second gate insulation patterns；
Patterning processes are performed to the grid film and the second gate insulation patterns, to form the gate patterns
With the first grid insulation patterns；
Wherein, orthographic projection of the second gate insulation patterns on the underlay substrate covers the active layer in the lining
Orthographic projection on substrate, orthographic projection of the active layer on the underlay substrate cover the first grid insulation patterns in institute
State the orthographic projection on underlay substrate.
Optionally, it is described that a patterning processes are performed to the gate insulation layer film, to form second gate insulation patterns, bag
Include：
The first photoresist is coated in the gate insulation layer film；
First exposure-processed and the first development treatment are carried out to first photoresist by gate mask version, to form the
One photoetching offset plate figure；
First etching processing is carried out to the gate insulation layer film, to form second with first photoetching offset plate figure
Gate insulation figure；
First photoetching offset plate figure is peeled off, obtains the second gate insulation patterns.
Optionally, it is described that a patterning processes are performed to the grid film and the second gate insulation patterns, to be formed
The gate patterns and the first grid insulation patterns, including：
The second photoresist is coated on the grid film；
Second exposure-processed and the second development treatment are carried out to second photoresist by the gate mask version, with shape
Into the second photoetching offset plate figure；
Second etching processing is carried out to the grid film and the second gate insulation patterns, described second is carried to be formed
The gate patterns of photoetching offset plate figure and the first grid insulation patterns；
Second photoetching offset plate figure is peeled off, obtains the gate patterns and the first grid insulation patterns；
Wherein, first photoresist and second photoresist are positive photoresist, first exposure-processed
Exposure intensity is more than the exposure intensity of second exposure-processed so that the width of first photoetching offset plate figure is less than described the
The width of two photoetching offset plate figures；
Or, first photoresist and second photoresist are negative photoresist, the exposure of first exposure-processed
Luminous intensity is less than the exposure intensity of second exposure-processed so that the width of first photoetching offset plate figure is less than described second
The width of photoetching offset plate figure.
Optionally, the second etching processing processing includes：Twice etching processing,
It is described that second etching processing is carried out to the grid film and the second gate insulation patterns, to be formed with described
The gate patterns of second photoetching offset plate figure and the first grid insulation patterns, including：
Etching processing is carried out to the grid film, to form the grid figure with second photoetching offset plate figure
Shape；
Etching processing is carried out to the second gate insulation patterns, to form the first grid insulation patterns.
Optionally, described to be formed on underlay substrate before active layer, methods described also includes：
Barrier bed and cushion are sequentially formed on the underlay substrate.
Second aspect, there is provided a kind of array base palte, including：
Underlay substrate；
Active layer, first grid insulation patterns, gate patterns, interlayer insulating film and source are set gradually on the underlay substrate
Drain patterns；
Wherein, the upper surface of the first grid insulation patterns is provided with bulge-structure, and the lower surface of the gate patterns is set
It is equipped with the groove structure with the bulge-structure form fit, orthographic projection covering of the gate patterns on the underlay substrate
Orthographic projection of the first grid insulation patterns on the underlay substrate.
Optionally, the array base palte also includes：
The barrier bed and cushion set gradually on the underlay substrate.
Optionally, the material of the active layer is indium gallium zinc oxide.
The third aspect, there is provided a kind of display panel, including：Any described array base palte of second aspect.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
Manufacture method, array base palte and the display panel of array base palte provided in an embodiment of the present invention, by active layer
On sequentially form first grid insulation patterns and gate patterns, because the upper surface of first gate insulation is formed with bulge-structure, grid
The lower surface of pole figure shape is formed with the groove structure with the bulge-structure form fit so that the gate patterns are on underlay substrate
Orthographic projection can cover orthographic projection of the first grid insulation patterns on underlay substrate, effectively eliminate the LDD region in active layer
Domain, and then dead resistance is effectively reduced, therefore effectively raise TFT ON state current.It can effectively reduce simultaneously
The probability that source-drain electrode figure is broken, and can effectively improve TFT photostability.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1-1 is a kind of structural representation for array base palte that prior art provides；
Fig. 1-2 is a kind of schematic diagram for gate patterns of formation with photoetching offset plate figure that prior art provides；
Fig. 2 is a kind of flow chart of the manufacture method of array base palte provided in an embodiment of the present invention；
Fig. 3-1 is the flow chart of the manufacture method of another array base palte provided in an embodiment of the present invention；
Fig. 3-2 is a kind of schematic diagram that barrier bed and cushion are formed on underlay substrate provided in an embodiment of the present invention；
Fig. 3-3 is a kind of schematic diagram for forming active layer on the buffer layer provided in an embodiment of the present invention；
Fig. 3-4a are that one kind provided in an embodiment of the present invention sequentially forms first grid insulation patterns and grid on active layer
The method flow diagram of figure；
Fig. 3-4b are a kind of schematic diagrames that gate insulation layer film is formed on active layer provided in an embodiment of the present invention；
Fig. 3-4c are a kind of method flow diagrams for forming second gate insulation patterns provided in an embodiment of the present invention；
Fig. 3-4d are a kind of first photoetching offset plate figure schematic diagrames of formation provided in an embodiment of the present invention；
Fig. 3-4e are a kind of second gate insulation patterns of the formation with the first photoetching offset plate figure provided in an embodiment of the present invention
Schematic diagram；
Fig. 3-4f are a kind of schematic diagrames that grid film is formed on second gate insulation patterns provided in an embodiment of the present invention；
Fig. 3-4g are a kind of method flows for forming gate patterns and first grid insulation patterns provided in an embodiment of the present invention
Figure；
Fig. 3-4h are a kind of second photoetching offset plate figure schematic diagrames of formation provided in an embodiment of the present invention；
Fig. 3-4i are a kind of gate patterns and first of the formation with the second photoetching offset plate figure provided in an embodiment of the present invention
The method flow diagram of gate insulation figure；
Fig. 3-4j are a kind of examples for forming the gate patterns with the second photoetching offset plate figure provided in an embodiment of the present invention
Figure；
Fig. 3-4k are a kind of exemplary plots for forming first grid insulation patterns provided in an embodiment of the present invention；
Fig. 3-5 is that one kind provided in an embodiment of the present invention is sequentially forming interlayer insulating film and source-drain electrode on gate patterns
The schematic diagram of figure；
Fig. 4 is a kind of structural representation of array base palte provided in an embodiment of the present invention.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1-2 is refer to, Fig. 1-2 is a kind of showing for gate patterns of formation with photoetching offset plate figure that prior art provides
It is intended to, in order to reduce probability that source-drain electrode figure is broken, it is necessary to ensure that the gradient of the both sides of gate insulation figure 05 is relatively delayed, and
Ensure that the gradient of gate patterns 06 both sides is relatively slow, therefore after being exposed processing and development treatment to the photoresist on grid film
The photoetching offset plate figure A of formation needs have certain radian, then after performing etching processing to grid film, obtained gate patterns
The gradient of 06 both sides is relatively slow, using identical producing principle it is also possible that the gradient of the both sides of gate insulation figure 05 is relatively slow, therefore
The frontal projected area of gate insulation figure 05 and gate patterns 06 on active layer 04 is sequentially reduced, and ultimately results in TFT ON state electricity
Stream is smaller.
In order to solve the above-mentioned technical problem, the embodiments of the invention provide a kind of manufacture method of array base palte, such as Fig. 2 institutes
Show, Fig. 2 is a kind of flow chart of the manufacture method of array base palte provided in an embodiment of the present invention, the manufacture method of the array base palte
It can include：
Step 201, active layer is formed on underlay substrate.
Step 202, first grid insulation patterns and gate patterns are sequentially formed on active layer.
Step 203, interlayer insulating film and source-drain electrode figure are sequentially formed on gate patterns.
Wherein, the upper surface of first grid insulation patterns is formed with bulge-structure, the lower surfaces of gate patterns formed with it is convex
The groove structure of planform matching is played, orthographic projection of the gate patterns on underlay substrate covers first grid insulation patterns in substrate
Orthographic projection on substrate.
In summary, the manufacture method of array base palte provided in an embodiment of the present invention, by being sequentially formed on active layer
First grid insulation patterns and gate patterns, because the upper surface of first gate insulation is formed with bulge-structure, under gate patterns
Surface is formed with the groove structure with the bulge-structure form fit so that orthographic projection of the gate patterns on underlay substrate can
To cover orthographic projection of the first grid insulation patterns on underlay substrate, the LDD region domain in active layer is effectively eliminated, and then effectively
Reduce dead resistance, therefore effectively raise TFT ON state current.
Fig. 3-1 is refer to, Fig. 3-1 is the flow of the manufacture method of another array base palte provided in an embodiment of the present invention
Figure, the manufacture method of the array base palte can include：
Step 301, the barrier bed set gradually on underlay substrate and cushion.
In practical application, the active layer in array base palte provided in an embodiment of the present invention is located at the aspect compared on the lower, should
Active layer easily by irradiating for external light source below underlay substrate is come from, cause TFT threshold voltage produce it is very tight
The drift of weight, therefore the barrier bed set below active layer can be blocked effectively to active layer, it is outer so as to avoid
The irradiation of boundary's light source, the threshold voltage for avoiding TFT produces serious drift, and then effectively raises TFT photostability.
Example, it refer to Fig. 3-2, Fig. 3-2 is that one kind provided in an embodiment of the present invention is formed on underlay substrate and blocked
The schematic diagram of layer and cushion, by depositing, applying, any of the various ways such as sputter and form screening on underlay substrate 11
Barrier film, layer film then is blocked to this and forms barrier bed 12 by a patterning processes, a patterning processes can wrap
Include：Photoresist coating, exposure, development, etching and photoresist lift off；By heavy on the underlay substrate 11 formed with barrier bed 12
Any of various ways such as product, coating, sputtering form cushion 13.
Step 302, active layer is formed on the buffer layer.
Optionally, the material of the active layer can be indium gallium zinc oxide (English：Indium Gallium Zinc
Oxide；Referred to as：IGZO), tin indium oxide (English：Indium Tin Oxide；Referred to as：ITO) or indium-doped zinc oxide is (English：
Indium-doped Zinc Oxide；Referred to as：IZO) etc..
Example, Fig. 3-3 is refer to, Fig. 3-3 is that one kind provided in an embodiment of the present invention forms active layer on the buffer layer
Schematic diagram.By depositing, applying, any of the various ways such as sputtering on the underlay substrate 11 formed with cushion 13
Active layer film is formed, active layer 14, a patterning processes then are formed by a patterning processes to the active layer film
It can include：Photoresist coating, exposure, development, etching and photoresist lift off.
Step 303, first grid insulation patterns and gate patterns are sequentially formed on active layer.
Example, Fig. 3-4a are refer to, Fig. 3-4a are that one kind provided in an embodiment of the present invention sequentially forms on active layer
The method flow diagram of first grid insulation patterns and gate patterns, this method can include：
Step 3031, gate insulation layer film is formed on active layer.
Optionally, the material of the gate insulation layer film can be silica, silicon nitride or high dielectric constant material etc..
Example, Fig. 3-4b are refer to, Fig. 3-4b are that one kind provided in an embodiment of the present invention formation grid on active layer are exhausted
The schematic diagram of edge layer film, by depositing, applying, sputtering etc. in various ways on the underlay substrate 11 formed with active layer 13
Any formation gate insulation layer film 151.
Step 3032, a patterning processes are performed to gate insulation layer film, to form second gate insulation patterns.
Example, Fig. 3-4c are refer to, Fig. 3-4c are a kind of formation second gate insulation patterns provided in an embodiment of the present invention
Method flow diagram, this method can include：
Step a1, the first photoresist is coated in gate insulation layer film.
Optionally, first photoresist can be positive photoresist.
Step a2, the first exposure-processed and the first development treatment are carried out to the first photoresist by gate mask version, with shape
Into the first photoetching offset plate figure.
Example, Fig. 3-4d are refer to, Fig. 3-4d are a kind of first photoetching offset plate figures of formation provided in an embodiment of the present invention
Schematic diagram, the first exposure is carried out to the first photoresist by gate mask version on the underlay substrate 11 formed with the first photoresist
Processing and the first development treatment, to form the first photoetching offset plate figure A1.
Step a3, the first etching processing is carried out to gate insulation layer film, to form second with the first photoetching offset plate figure
Gate insulation figure.
Example, Fig. 3-4e are refer to, Fig. 3-4e are that a kind of formed provided in an embodiment of the present invention carries the first photoresist
The second gate insulation patterns schematic diagram of figure is thin to gate insulation layer on the underlay substrate 11 formed with the first photoetching offset plate figure A1
Film carries out the first etching processing, to form the second gate insulation patterns 152 with the first photoetching offset plate figure A1.Implement in the present invention
Example in, to gate insulation layer film carry out the first etching processing when, can by underlay substrate 11 not by the first photoetching offset plate figure A1
The gate insulation layer film of covering carries out partial etching so that certain thickness gate insulation layer material is still left on underlay substrate 11
Material, that is to say, the thickness d 1 of the gate insulator layer material etched during the first etching processing etches less than second gate insulation patterns 152
The thickness d 2 of (namely gate insulation layer film) before.
Step a4, the first photoetching offset plate figure is peeled off, obtains second gate insulation patterns.
In embodiments of the present invention, orthographic projection of the second gate insulation patterns on underlay substrate covers active layer in substrate base
Orthographic projection on plate.
Step 3033, grid film is formed on second gate insulation patterns.
Optionally, grid film can be formed using metal material, for example, grid film is using metal molybdenum (abbreviation：Mo)、
Metallic copper is (referred to as：Cu), metallic aluminium (abbreviation：Al) or alloy material is fabricated.
Example, Fig. 3-4f are refer to, Fig. 3-4f are one kind provided in an embodiment of the present invention on second gate insulation patterns
The schematic diagram of grid film is formed, by depositing, applying, splashing on the underlay substrate 11 formed with second gate insulation patterns 152
Any of the various ways such as penetrate and form grid film 161.
Step 3034, a patterning processes are performed to grid film and second gate insulation patterns, with formed gate patterns and
First grid insulation patterns.
Example, Fig. 3-4g are refer to, Fig. 3-4g are a kind of formation gate patterns and first provided in an embodiment of the present invention
The method flow diagram of gate insulation figure, this method can include：
Step b1, the second photoresist is coated on grid film.
Optionally, second photoresist can be positive photoresist.
Step b2, the second exposure-processed and the second development treatment are carried out to the second photoresist by gate mask version, with shape
Into the second photoetching offset plate figure.
Example, Fig. 3-4h are refer to, Fig. 3-4h are a kind of second photoetching offset plate figures of formation provided in an embodiment of the present invention
Schematic diagram, the second exposure is carried out to the second photoresist by gate mask version on the underlay substrate 11 formed with the second photoresist
Processing and the second development treatment, to form the second photoetching offset plate figure A2.
Step b3, the second etching processing is carried out to grid film and second gate insulation patterns, the second photoetching is carried to be formed
The gate patterns and first grid insulation patterns of glue pattern.
In embodiments of the present invention, second etching processing processing can include：Twice etching processing.Example, it please join
Fig. 3-4i are examined, Fig. 3-4i are a kind of gate patterns and first of the formation with the second photoetching offset plate figure provided in an embodiment of the present invention
The method flow diagram of gate insulation figure, this method can include：
Step b31, an etching processing is carried out to grid film, to form the grid figure with the second photoetching offset plate figure
Shape.
Example, Fig. 3-4j are refer to, Fig. 3-4j are that a kind of formed provided in an embodiment of the present invention carries the second photoresist
The exemplary plot of the gate patterns of figure, one is carried out to grid film on the underlay substrate 11 formed with the second photoetching offset plate figure A2
Secondary etching processing, to form the gate patterns 16 with the second photoetching offset plate figure A2.In embodiments of the present invention, to grid film
When carrying out an etching processing, the grid film on underlay substrate 11 not by the second photoetching offset plate figure A2 coverings can be carried out entirely
Portion etches, to form the gate patterns 16 with the second photoetching offset plate figure A2.
Step b32, an etching processing is carried out to second gate insulation patterns, to form first grid insulation patterns.
Example, Fig. 3-4k are refer to, Fig. 3-4k are a kind of formation first grid insulation patterns provided in an embodiment of the present invention
Exemplary plot, to the second gate insulation figure on the underlay substrate 11 formed with the gate patterns 16 with the second photoetching offset plate figure B2
Shape carries out an etching processing, to form first grid insulation patterns 15.In embodiments of the present invention, second gate insulation patterns are entered
During etching processing of row, the second gate insulation patterns not covered on underlay substrate 11 by gate patterns 16 can be carried out complete
Portion etches, to form first grid insulation patterns 15.
Step b4, the second photoetching offset plate figure is peeled off, obtains gate patterns and first grid insulation patterns.
In embodiments of the present invention, orthographic projection of the active layer on underlay substrate covers first grid insulation patterns in substrate base
Orthographic projection on plate.
It should be noted that because the thickness of the gate insulator layer material of step b32 etchings is smaller, the first grid after etching
The gradient is not present in insulation patterns both sides, therefore orthographic projection of the gate patterns 16 on underlay substrate 11 can cover the first gate insulation
Orthographic projection of the figure 15 on underlay substrate 11.
In practical application, the width d3 for the first photoetching offset plate figure A1 that above-mentioned steps a2 is formed is less than step b2 is formed the
Two photoetching offset plate figure A2 width d4, can cause the upper surface of first grid insulation patterns 15 that is obtained after step 303 formed with
Bulge-structure, the lower surface of gate patterns 16 is formed with the groove structure with bulge-structure form fit.Due to the first photoresist
It is positive photoresist with the second photoresist, it is therefore desirable to ensure that the exposure intensity of the first exposure-processed in step a2 needs to be more than
The exposure intensity of second exposure-processed in step b2.
It should be noted that the embodiment of the present invention is so that the first photoresist and the second photoresist are positive photoresist as an example
Schematically illustrated, in practical application, the first photoresist and the second photoresist can also be negative photoresist, this time step
The exposure intensity of the first exposure-processed needs the exposure intensity for being less than the second exposure-processed in step b2 in rapid a2, so that the first light
The width of photoresist figure is less than the width of the second photoetching offset plate figure, and the embodiment of the present invention is to the first photoresist and the second photoresist
Material is not specifically limited, but needs to ensure that the first photoresist is identical with the material of the second photoresist to simplify technique, now
Identical mask plate can be used when forming the first photoetching offset plate figure and the second photoetching offset plate figure.
Step 304, interlayer insulating film and source-drain electrode figure are sequentially formed on gate patterns.
Optionally, the material of the interlayer insulating film can be silica, silicon nitride or high dielectric constant material etc., be somebody's turn to do
The material for having drain patterns can be formed for metal material, for example, source-drain electrode figure can use metal Mo, Ni metal, metal
Al or alloy material are fabricated.
Example, it refer to Fig. 3-5, Fig. 3-5 is provided in an embodiment of the present invention a kind of in the shape successively on gate patterns
Into interlayer insulating film and the schematic diagram of source-drain electrode figure, by depositing, applying on the underlay substrate 11 formed with gate patterns 16
Any of various ways such as deposited, sputtering form interlayer insulating layer of thin-film, and then the layer insulation layer film is passed through once
Patterning processes form interlayer insulating film 17, and a patterning processes can include：Photoresist coating, exposure, development, etching and light
Photoresist is peeled off；By depositing, applying, the appointing in various ways such as sputtering on the underlay substrate 11 formed with interlayer insulating film 17
One kind forms source and drain very thin films, then forms source-drain electrode figure 18 by a patterning processes to the source and drain very thin films, this is once
Patterning processes can include：Photoresist coating, exposure, development, etching and photoresist lift off.
In practical application, array base palte can be produced after the step of above-described embodiment, example, it refer to figure
4, Fig. 4 be a kind of structural representation of array base palte provided in an embodiment of the present invention, due to the upper table of first grid insulation patterns 15
Face is formed with bulge-structure, and the lower surface of gate patterns 16 is formed with the groove structure with bulge-structure form fit, grid figure
The both ends of shape 16 are in small distance to active layer 14, therefore effectively raise gate patterns 16 to the grid-control area in active layer 14
The control ability in domain 141, further improve TFT ON state current.In embodiments of the present invention, active layer 14 is being eliminated
In LDD region domain on the premise of, can be by changing technique when forming gate patterns 16 so that the slope of the both sides of gate patterns 16
Degree is relatively slow, and then improves the flatness of deposition intermediate insulating layer 17, occurs to break so as to effectively reduce source-drain electrode figure 18
The probability split.
In the prior art, as Figure 1-1, when the array base palte is arranged in OLED display panel, OLED is shown
The light L that luminescent layer in panel is sent may be mapped to the grid-control region in active layer 04 by the side of gate insulator 05
In 041, now TFT threshold voltage produces very serious drift, and then causes TFT photostability relatively low.
And in embodiments of the present invention, Fig. 4 is refer to, when the array base palte is arranged in OLED display panel, due to
The upper surface of first grid insulation patterns 15 formed with bulge-structure, the lower surfaces of gate patterns 16 formed with bulge-structure shape
The groove structure of matching, and gate patterns 16 are light tight, the light L that the luminescent layer in OELD display panels is sent is by gate patterns
16 side is blocked, therefore can effectively be avoided in the grid-control region 141 that light L is mapped in active layer 14, avoids TFT's
Threshold voltage produces serious drift, and then effectively raises TFT photostability.
In summary, the manufacture method of array base palte provided in an embodiment of the present invention, by being sequentially formed on active layer
First grid insulation patterns and gate patterns, because the upper surface of first gate insulation is formed with bulge-structure, under gate patterns
Surface is formed with the groove structure with the bulge-structure form fit so that orthographic projection of the gate patterns on underlay substrate can
To cover orthographic projection of the first grid insulation patterns on underlay substrate, the LDD region domain in active layer is effectively eliminated, and then effectively
Reduce dead resistance, therefore effectively raise TFT ON state current.Source-drain electrode figure can be effectively reduced simultaneously
The probability being broken, and can effectively improve TFT photostability.
The embodiment of the present invention also provides a kind of array base palte, and the structure of the array base palte may be referred to Fig. 4, the array base palte
It can include：
Underlay substrate 11.
Active layer 14, first grid insulation patterns 15, gate patterns 16, interlayer insulating film are set gradually on underlay substrate 11
17 and source-drain electrode figure 18.
Wherein, the upper surface of first grid insulation patterns 15 is provided with bulge-structure, and the lower surface of gate patterns 16 is provided with
With the groove structure of bulge-structure form fit, orthographic projection of the gate patterns 15 on underlay substrate 11 covers the first gate insulation figure
Orthographic projection of the shape 16 on underlay substrate 11.
Optionally, as shown in figure 4, the array base palte can also include：The barrier bed set gradually on underlay substrate 11
12 and cushion 13.
Optionally, the material of the active layer is IGZO, ITO or IZO etc..
It is apparent to those skilled in the art that for convenience and simplicity of description, the array of foregoing description
The concrete principle of the specific manufacturing process of substrate and array base palte, may be referred to the corresponding process in preceding method embodiment,
This is repeated no more.
In summary, array base palte provided in an embodiment of the present invention, by setting gradually the first gate insulation on active layer
Figure and gate patterns, because the upper surface of first gate insulation is provided with bulge-structure, the lower surface of gate patterns is provided with
With the groove structure of the bulge-structure form fit so that orthographic projection of the gate patterns on underlay substrate can cover first
Orthographic projection of the gate insulation figure on underlay substrate, the LDD region domain in active layer is effectively eliminated, and then effectively reduce and post
Raw resistance, therefore effectively raise TFT ON state current.It can effectively reduce what source-drain electrode figure was broken simultaneously
Probability, and can effectively improve TFT photostability.
The embodiment of the present invention additionally provides a kind of display device, and it includes any one array base in above-described embodiment
Plate.Display device can be：Liquid crystal panel, OLED display panel, Electronic Paper, mobile phone, tablet personal computer, television set, display, pen
Remember any product or part with display function such as this computer, DPF, navigator.
One of ordinary skill in the art will appreciate that hardware can be passed through by realizing all or part of step of above-described embodiment
To complete, by program the hardware of correlation can also be instructed to complete, described program can be stored in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only storage, disk or CD etc..
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (10)
1. a kind of manufacture method of array base palte, it is characterised in that methods described includes：
Active layer is formed on underlay substrate；
First grid insulation patterns and gate patterns are sequentially formed on the active layer；
Interlayer insulating film and source-drain electrode figure are sequentially formed on the gate patterns；
Wherein, the upper surface of the first grid insulation patterns is formed with bulge-structure, the lower surfaces of the gate patterns formed with
With the groove structure of the bulge-structure form fit, the gate patterns on the underlay substrate orthographic projection covering described in
Orthographic projection of the first grid insulation patterns on the underlay substrate.
2. according to the method for claim 1, it is characterised in that
It is described to sequentially form first grid insulation patterns and gate patterns on the active layer, including：
Gate insulation layer film is formed on the active layer；
Patterning processes are performed to the gate insulation layer film, to form second gate insulation patterns；
Grid film is formed on the second gate insulation patterns；
Patterning processes are performed to the grid film and the second gate insulation patterns, to form the gate patterns and institute
State first grid insulation patterns；
Wherein, orthographic projection of the second gate insulation patterns on the underlay substrate covers the active layer in the substrate base
Orthographic projection on plate, orthographic projection of the active layer on the underlay substrate cover the first grid insulation patterns in the lining
Orthographic projection on substrate.
3. according to the method for claim 2, it is characterised in that
It is described that a patterning processes are performed to the gate insulation layer film, to form second gate insulation patterns, including：
The first photoresist is coated in the gate insulation layer film；
First exposure-processed and the first development treatment are carried out to first photoresist by gate mask version, to form the first light
Photoresist figure；
First etching processing is carried out to the gate insulation layer film, it is exhausted to form the second gate with first photoetching offset plate figure
Edge figure；
First photoetching offset plate figure is peeled off, obtains the second gate insulation patterns.
4. according to the method for claim 3, it is characterised in that
It is described that a patterning processes are performed to the grid film and the second gate insulation patterns, to form the gate patterns
With the first grid insulation patterns, including：
The second photoresist is coated on the grid film；
Second exposure-processed and the second development treatment are carried out to second photoresist by the gate mask version, to form the
Two photoetching offset plate figures；
Second etching processing is carried out to the grid film and the second gate insulation patterns, second photoetching is carried to be formed
The gate patterns of glue pattern and the first grid insulation patterns；
Second photoetching offset plate figure is peeled off, obtains the gate patterns and the first grid insulation patterns；
Wherein, first photoresist and second photoresist are positive photoresist, the exposure of first exposure-processed
Intensity is more than the exposure intensity of second exposure-processed so that the width of first photoetching offset plate figure is less than second light
The width of photoresist figure；
Or, first photoresist and second photoresist are negative photoresist, the exposure of first exposure-processed is strong
Degree is less than the exposure intensity of second exposure-processed so that the width of first photoetching offset plate figure is less than second photoetching
The width of glue pattern.
5. according to the method for claim 4, it is characterised in that the second etching processing processing includes：At twice etching
Reason,
It is described that second etching processing is carried out to the grid film and the second gate insulation patterns, carry described second to be formed
The gate patterns of photoetching offset plate figure and the first grid insulation patterns, including：
Etching processing is carried out to the grid film, to form the gate patterns with second photoetching offset plate figure；
Etching processing is carried out to the second gate insulation patterns, to form the first grid insulation patterns.
6. method according to any one of claims 1 to 5, it is characterised in that it is described on underlay substrate formed active layer it
Before, methods described also includes：
Barrier bed and cushion are sequentially formed on the underlay substrate.
A kind of 7. array base palte, it is characterised in that including：
Underlay substrate；
Active layer, first grid insulation patterns, gate patterns, interlayer insulating film and source-drain electrode are set gradually on the underlay substrate
Figure；
Wherein, the upper surface of the first grid insulation patterns is provided with bulge-structure, and the lower surface of the gate patterns is provided with
With the groove structure of the bulge-structure form fit, the gate patterns on the underlay substrate orthographic projection covering described in
Orthographic projection of the first grid insulation patterns on the underlay substrate.
8. array base palte according to claim 7, it is characterised in that the array base palte also includes：
The barrier bed and cushion set gradually on the underlay substrate.
9. array base palte according to claim 7, it is characterised in that
The material of the active layer is indium gallium zinc oxide.
A kind of 10. display panel, it is characterised in that including：Any described array base palte of claim 7 to 9.
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