CN112542470A - Array substrate and preparation method thereof - Google Patents
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- CN112542470A CN112542470A CN202011408407.XA CN202011408407A CN112542470A CN 112542470 A CN112542470 A CN 112542470A CN 202011408407 A CN202011408407 A CN 202011408407A CN 112542470 A CN112542470 A CN 112542470A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The application provides an array substrate and a preparation method thereof, wherein the array substrate comprises a substrate; the switch thin film transistor is arranged on the substrate in an array mode; the photosensitive thin film transistor is arranged on the substrate; the switch thin film transistor and the photosensitive thin film transistor are arranged at the same layer and at intervals; the switch thin film transistor comprises a first semiconductor layer and a shading layer which are positioned on the substrate; the photosensitive thin film transistor includes a second semiconductor layer on the substrate. According to the array substrate, the light shielding layer, the first semiconductor layer and the second semiconductor layer are prepared by adopting the same photomask manufacturing process, so that the manufacturing process of the array substrate is reduced, the production cost of the prior art is reduced, and the productivity benefit is improved; meanwhile, the shading layer above the first semiconductor layer is reserved, so that the characteristics of the switch thin film transistor are guaranteed, and meanwhile, the influence of illumination on the characteristics of the switch thin film transistor is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
In the field of display technology, driving thin film transistors and sensor thin film transistors are widely used, the sensor thin film transistors require low subthreshold swing, low off-state current density and high electron mobility, and structures of Indium Gallium Zinc Oxide (IGZO) and Indium Zinc Oxide (IZO) are generally adopted as semiconductor layers of the thin film transistors in the prior art to meet the requirements.
At present, a design for manufacturing a driving thin film transistor and a sensor thin film transistor in the same panel appears in an in-cell-touch (in-cell-touch) screen, which requires that both the switching characteristics of the driving thin film transistor and the photosensitivity of the sensor thin film transistor are considered during manufacturing, and since Indium Gallium Zinc Oxide (IGZO) has photosensitivity, a light shielding layer needs to be prepared on the upper layer of the manufactured driving thin film transistor, thereby increasing the photomask process and manufacturing cost.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which are used for solving the technical problems of more complicated steps, higher production cost, longer period and the like of the preparation method in the existing array substrate preparation process.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the application provides a preparation method of an array substrate, which comprises the following steps:
step S10: forming a first metal layer on a substrate, and carrying out patterning treatment on the first metal layer to form a first electrode and a second electrode which are arranged at intervals;
step S20: forming an insulating layer, a semiconductor layer, and a light shielding layer on the substrate, the first electrode, and the second electrode;
step S30: patterning the light shielding layer and the semiconductor layer by using a mask plate to form a first semiconductor layer and a first light shielding layer which are positioned above the first electrode, and a second semiconductor layer which is positioned above the second electrode;
step S40: and forming a second metal layer on the first shading layer, the insulating layer and the second semiconductor layer, and patterning the second metal layer to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.
In the preparation method of the present application, the step 30 includes the following steps:
step S31: preparing a photoresist on the shading layer;
step S32: exposing the photoresist by using a mask adjusting plate, and then developing the photoresist to form a first photoresist layer positioned above the first electrode and a second photoresist layer positioned above the second electrode, wherein the thickness of the first photoresist layer is greater than that of the second photoresist layer;
step S33: etching the shading layer and the semiconductor layer which are not covered by the first light resistance layer and the second light resistance layer to form a first semiconductor layer and a first shading layer which are positioned above the first electrode, and a second semiconductor layer and a second shading layer which are positioned above the second electrode;
step S34: ashing the first photoresist layer and the second photoresist layer to completely strip the second photoresist layer and thin the first photoresist layer;
step S35: etching the first light resistance layer and the second light shielding layer by adopting a dry etching process to completely strip the first light resistance layer and the second light shielding layer;
step S36: and removing the residual photoresist on the surfaces of the first shading layer and the second semiconductor layer after etching.
In the preparation method of the present application, in step S32, masks with different penetration rates are used to perform a photomask process on the photoresist; the mask plate comprises a first penetration rate area, a second penetration rate area and a third penetration rate area;
the first transmittance region corresponds to the first electrode and is opaque; the second penetration rate area corresponds to the second electrode, and the penetration rate of the second penetration rate area is 50%; the third transmittance region corresponds to the remaining region and has a transmittance of 100%.
In the preparation method of the present application, step S33 includes the following steps:
step S331: etching the light shielding layer which is not covered by the first light resistance layer and the second light resistance layer by adopting a dry etching process;
step S332: and etching the semiconductor layer uncovered by the first light resistance layer and the second light resistance layer by adopting a wet etching process.
In the preparation method of the present application, step S40 includes the following steps:
step S41: depositing a second metal layer on the first light-shielding layer, the insulating layer and the second semiconductor layer;
step S42: and patterning the second metal layer through a mask plate to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first light shielding layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.
The present application also provides an array substrate, including:
a substrate;
the switching thin film transistor is arranged on the substrate in an array mode and comprises a first electrode and a first semiconductor layer which are arranged in a stacked mode;
the photosensitive thin film transistor is arranged on the substrate and comprises a second electrode and a second semiconductor layer which are arranged in a stacked mode;
the switch thin film transistor and the photosensitive thin film transistor are arranged at intervals, and the switch thin film transistor further comprises a shading layer located above the first semiconductor layer.
In the array substrate, the array substrate comprises a first metal layer, an insulating layer, a semiconductor layer, a second metal layer and a passivation layer which are stacked;
the first metal layer is arranged on the substrate and comprises the first electrode and the second electrode which are arranged at intervals;
the insulating layer is arranged above the first metal layer;
the semiconductor layer is disposed over the insulating layer, the semiconductor layer including the first semiconductor layer and the second semiconductor layer;
the second metal layer is arranged above the semiconductor layer and comprises a third electrode and a fourth electrode which are positioned in two opposite edge areas of the light shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer;
the passivation layer is disposed over the insulating layer.
In the array substrate of the present application, the switching thin film transistor includes the first electrode, the first semiconductor layer, the light shielding layer, the third electrode, and the fourth electrode on the substrate;
the photosensitive thin film transistor comprises the second electrode, the second semiconductor layer, the fifth electrode and the sixth electrode which are positioned on the substrate; wherein,
the first semiconductor layer and the second semiconductor layer each include a first metal oxide layer and a second metal oxide layer which are stacked.
In the array substrate, the first semiconductor layer, the light shielding layer and the second semiconductor layer are prepared and formed through the same photomask manufacturing process.
In the array substrate of the present application, the material of the light shielding layer is molybdenum oxide.
Has the advantages that: according to the method, the first semiconductor layer, the shading layer and the second semiconductor layer in the array substrate are prepared by adopting the same photomask manufacturing process, so that the manufacturing process of the array substrate is reduced, the production cost of the prior art is reduced, and the productivity benefit is improved; mask plates with different penetration rates are adopted in the photomask manufacturing process, and the mask plates correspond to the light shielding layers and the half mask plate of the first semiconductor layer, so that the light shielding layers are reserved on the switch thin film transistor, the characteristics of the switch thin film transistor are guaranteed, and meanwhile, the influence of illumination on the characteristics of the switch thin film transistor is avoided.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic process flow diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2A-2I are schematic structural diagrams of an array substrate provided in an embodiment of the present disclosure during a manufacturing process;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, a design for manufacturing a driving thin film transistor and a sensor thin film transistor in the same panel appears in an in-cell-touch (in-cell-touch) screen, and the switching characteristic of the driving thin film transistor and the photosensitivity of the sensor thin film transistor are both required to be considered during manufacturing. Based on the above, the application provides an array substrate and a preparation method thereof, which can solve the above-mentioned defect.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Referring to fig. 1, a process flow of the array substrate according to the embodiment of the present disclosure is schematically illustrated.
In this embodiment, the method for manufacturing the array substrate includes:
step S10: a first metal layer is formed on the substrate 10, and the first metal layer is patterned to form a first electrode 21 and a second electrode 22 which are arranged at an interval, as shown in fig. 2A.
In this embodiment, the step S10 includes the following steps:
step S11: a substrate 10 is provided, the substrate 10 including but not limited to a glass substrate and a flexible substrate.
Further, in the embodiment, the substrate 10 is a flexible transparent PI substrate, mainly made of polyimide, and the PI material can effectively improve the light transmittance.
Step S12: depositing a first metal layer on the substrate 10, wherein the material of the first metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper, and alloys thereof, and the method for depositing the first metal layer includes, but is not limited to, physical vapor deposition.
Step S13: and patterning the first metal layer through a mask plate to form a first electrode 21 and a second electrode 22 which are arranged at intervals.
Further, in this embodiment, the first electrode 21 is a first gate, and the second electrode 22 is a second gate.
Step S20: an insulating layer 30, a semiconductor layer 40, and a light-shielding layer 50 are formed on the first electrode layer 20, as shown in fig. 2B.
In this embodiment, the step S20 includes the following steps:
step S21: preparing an insulating layer 30 on the substrate 10, wherein the insulating layer 30 completely covers the first electrode 21 and the second electrode 22, and the preparing method of the insulating layer 30 includes, but is not limited to, a chemical vapor deposition method.
In this embodiment, the insulating layer 30 is a gate insulating layer, the material of the insulating layer 30 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a stack thereof, and the thickness of the insulating layer 30 is 4000A to 8000A.
Step S22: preparing a semiconductor layer 40 on the insulating layer 30, wherein the semiconductor layer 40 includes a first metal oxide layer 41 and a second metal oxide layer 42 sequentially prepared on the insulating layer 30, and the preparation method of the semiconductor layer 40 includes, but is not limited to, a physical vapor deposition method.
The material of the first metal oxide layer 41 includes, but is not limited to, Indium Gallium Zinc Oxide (IGZO), and the thickness of the first metal oxide layer 41 is 40nm to 100 nm; the material of the second metal oxide layer 42 includes, but is not limited to, Indium Zinc Oxide (IZO), and the thickness of the second metal oxide layer 42 is 40nm to 100 nm.
Step S23: preparing a layer of light-shielding material including, but not limited to, molybdenum oxide, indium magnesium oxide, etc., on the semiconductor layer 40; the light shielding material is annealed at 350 deg.c in a dry compressed air (CDA) environment to form the light shielding layer 50.
Step S30: patterning the light-shielding layer 50 and the semiconductor layer 40 by using a mask, so as to form a first semiconductor layer 401 and a first light-shielding layer 501 above the first electrode 21, and a second semiconductor layer 402 above the second electrode, as shown in fig. 2G.
The first semiconductor layer 401 and the second semiconductor layer 402 each include a first metal oxide layer 41 and a second metal oxide layer 42, which are stacked, the first metal oxide layer 41 is made of a material including, but not limited to, Indium Gallium Zinc Oxide (IGZO), and the second metal oxide layer 42 is made of a material including, but not limited to, Indium Zinc Oxide (IZO).
In this embodiment, the step S30 includes the following steps:
step S31: a photoresist is prepared on the light-shielding layer 50.
Step S32: exposing the photoresist by using a mask adjusting plate, and then developing the photoresist to form a first photoresist layer 61 located above the first electrode and a second photoresist layer 62 located above the second electrode, wherein the thickness of the first photoresist layer 61 is greater than that of the second photoresist layer 62, as shown in fig. 2C.
Mask plates with different penetration rates are adopted to carry out photomask processing on the photoresist; the mask includes a first transmittance region Tr1, a second transmittance region Tr2, and a third transmittance region Tr 3.
The first transmittance region Tr1 corresponds to the first electrode 21 and the first transmittance region Tr1 is opaque to light; the second transmittance region Tr2 corresponds to the second electrode 22 and the transmittance of the second transmittance region Tr1 is 50%; the third transmittance region Tr3 corresponds to the remaining region and the transmittance of the third transmittance region is 100%.
In this embodiment, the thickness difference between the second photoresist layer 62 and the first photoresist layer 61 is 1um-2um, which is not limited in this embodiment.
It should be noted that, in this embodiment, the method for exposing the photoresist includes, but is not limited to, using masks with different transmittances; in this embodiment, the mask plates with different transmittances are used to perform the masking process on the photoresist for illustration only, which is not limited in this embodiment.
Step S33: etching the light shielding layer 50 and the semiconductor layer 40 which are not covered by the first photoresist layer 61 and the second photoresist layer 62 to form a first semiconductor layer 401 and a first light shielding layer 501 above the first electrode 21, and a second semiconductor layer 402 and a second light shielding layer 502 above the second electrode 22, as shown in fig. 2D.
In this embodiment, the step S33 includes the following steps:
step S331: and etching the light shielding layer 50 uncovered by the first photoresist layer 61 and the second photoresist layer 62 by using a dry etching process.
Step S332: and etching the semiconductor layer 40 uncovered by the first photoresist layer 61 and the second photoresist layer 62 by using a wet etching process.
Step S34: ashing the first photoresist layer 61 and the second photoresist layer 62 to completely strip the second photoresist layer 62, and thinning the first photoresist layer 61 to form a first sub-photoresist layer 610, as shown in fig. 2E.
Step S35: and etching the second light shielding layer 502 by using an etching process, as shown in fig. 2F.
In this embodiment, the method for etching the second light shielding layer 502 includes, but is not limited to, dry etching.
Step S36: the first sub photoresist layer 610 is stripped. As shown in fig. 2G, the first sub-photoresist layer 610 is stripped off, and the first light-shielding layer 501 remains on the second metal oxide layer 42.
Step S40: a second metal layer is formed on the surfaces of the first light shielding layer 501, the insulating layer 30 and the second semiconductor layer 402, and the second metal layer is patterned to form a third electrode 71 and a fourth electrode 72 located at two opposite edge regions of the light shielding layer 501, and a fifth electrode 73 and a sixth electrode 74 located at two opposite edge regions of the second semiconductor layer 402, as shown in fig. 2H.
In this embodiment, the step S40 includes the following steps:
step S41: a second metal layer is deposited on the first light-shielding layer 501, the insulating layer 30 and the second semiconductor layer 402, the material of the second metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper and alloys thereof, and the method for depositing the second metal layer includes, but is not limited to, a physical vapor deposition method.
Step S42: patterning the second metal layer by a mask to form a third electrode 71 and a fourth electrode 72 at two opposite edge regions of the first light shielding layer 501, and a fifth electrode 73 and a sixth electrode 74 at two opposite edge regions of the second semiconductor layer 402.
Further, in this embodiment, the third electrode 71 and the fourth electrode 72 are first source/drain electrodes, and the fifth electrode 73 and the sixth electrode 74 are second source/drain electrodes.
In this embodiment, the method for manufacturing an array substrate further includes step S50: a passivation layer 80 is formed on the third electrode 71, the first light shielding layer 501, the fourth electrode 72, the insulating layer 30, the fifth electrode 73, the second semiconductor layer 402, and the sixth electrode 74 to form an array substrate, as shown in fig. 2I.
The passivation layer 80 may be made of materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof.
In the embodiment, the light-shielding layer 50 and the semiconductor layer 40 in the array substrate are prepared by using the same photomask process, so that the manufacturing processes of the array substrate are reduced, the production cost of the prior art is reduced, and the productivity effect is improved.
According to the method, the light shielding layer 50 and the semiconductor layer 40 are prepared by adopting the same photomask manufacturing process, so that the manufacturing process of the array substrate is reduced, the production cost of the prior art is reduced, and the productivity benefit is improved; meanwhile, the light shielding layer 51 above the first semiconductor layer 401 is reserved, so that the characteristics of the switching thin film transistor 100 are ensured, and meanwhile, the influence of illumination on the characteristics of the switching thin film transistor 100 is avoided; and, the light shield layer 50 on the photosensitive thin film transistor 200 is removed by dry etching, which enhances the photosensitivity of the photosensitive thin film transistor 200.
Example two
Referring to fig. 3, a schematic structural diagram of an array substrate according to an embodiment of the present disclosure is shown.
In this embodiment, the array substrate includes a substrate 10; a switching thin film transistor 100, the switching thin film transistor 100 being arranged in an array on the substrate 10, the switching thin film transistor 100 including a first electrode 21 and a first semiconductor layer 401 arranged in a stacked manner; a photosensitive thin film transistor 200, wherein the photosensitive thin film transistor 200 is disposed on the substrate 10, and the photosensitive thin film transistor 200 includes a second electrode 22 and a second semiconductor layer 402 which are stacked; the switching thin film transistor 100 and the photosensitive thin film transistor 200 are disposed at an interval, and the switching thin film transistor 100 further includes a light shielding layer 50 located above the first semiconductor layer.
In this embodiment, the photosensitive tft 100 and the display tft 200 are fabricated on the same substrate 10, so as to realize the functions of integrating sensing and displaying, and reduce the thickness of the array substrate.
In this embodiment, the array substrate includes a first metal layer, an insulating layer 30, a semiconductor layer 40, a second metal layer, and a passivation layer 80 sequentially stacked on the substrate 10.
In the present embodiment, the substrate 10 includes, but is not limited to, a glass substrate and a flexible substrate.
Further, in the embodiment, the substrate 10 is a flexible transparent PI substrate, mainly made of polyimide, and the PI material can effectively improve the light transmittance.
In this embodiment, the first metal layer is disposed on the substrate 10, and the first metal layer includes the first electrode 21 and the second electrode 22 disposed at an interval; the material of the first metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper, and alloys thereof.
In this embodiment, the insulating layer 30 is disposed above the first metal layer, the insulating layer 30 is a gate insulating layer, the insulating layer 30 completely covers the first electrode 21 and the second electrode 22, the material of the insulating layer 30 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a stack thereof, and the thickness of the insulating layer 30 is 4000A to 8000A.
In the present embodiment, the semiconductor layer 40 is disposed above the insulating layer 30, and the semiconductor layer 40 includes the first semiconductor layer 401 and the second semiconductor layer 402; the first semiconductor layer 41 is disposed over the first electrode 21; the second semiconductor layer 42 is disposed over the second electrode 22; the first semiconductor layer 401 and the second semiconductor layer 402 each include a first metal oxide layer 41 and a second metal oxide layer 42, which are stacked.
The material of the first metal oxide layer 41 includes, but is not limited to, Indium Gallium Zinc Oxide (IGZO), and the thickness of the first metal oxide layer 41 is 40nm to 100 nm; the material of the second metal oxide layer 42 includes, but is not limited to, Indium Zinc Oxide (IZO), and the thickness of the second metal oxide layer 42 is 40nm to 100 nm.
In this embodiment, the light-shielding layer 50 is disposed above the first semiconductor layer 401, and the material of the light-shielding layer 50 includes, but is not limited to, molybdenum oxide, indium magnesium oxide, and the like.
In this embodiment, the first semiconductor layer 401, the light-shielding layer 50 and the second semiconductor layer 402 are formed by the same photo-masking process, so as to save the manufacturing process and reduce the product cost.
In the present embodiment, the second metal layer is disposed above the semiconductor layer 40 and the insulating layer 30; the second metal layer includes a third electrode 71, a fourth electrode 72, a fifth electrode 73, and a sixth electrode 74 that are disposed at intervals.
The third electrode 71 and the fourth electrode 72 are located above the light shielding layer 50 and cover two opposite edge regions of the light shielding layer 50; the fifth electrode 73 and the sixth electrode 74 are located above the second semiconductor layer 402 and cover two opposite edge regions of the second semiconductor layer 402.
Further, in this embodiment, the third electrode 71 and the fourth electrode 72 are first source/drain electrodes, and the fifth electrode 73 and the sixth electrode 74 are second source/drain electrodes.
In the present embodiment, the passivation layer 80 is disposed above the insulating layer 30, and the material of the passivation layer 80 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like, or a stack thereof.
In this embodiment, the switching thin film transistor 100 includes the first electrode 21, the first semiconductor layer 401, the light shielding layer 50, the third electrode 71, and the fourth electrode 72, which are stacked on the substrate 10; the photosensitive thin film transistor 200 includes the second electrode 22, the first semiconductor layer 402, the fifth electrode 73, and the sixth electrode 74, which are stacked on the substrate 10.
In this embodiment, the light shielding layer 50 above the first semiconductor layer 401 is retained, so that the characteristics of the switching thin film transistor 100 are ensured, and meanwhile, the influence of light on the characteristics of the switching thin film transistor 100 is avoided; moreover, the light shielding layer 50 on the photosensitive thin film transistor 200 is removed, so that the photosensitivity of the photosensitive thin film transistor 200 is enhanced.
The application provides an array substrate and a preparation method thereof, wherein the array substrate comprises a substrate; the switch thin film transistor is arranged on the substrate in an array mode; the photosensitive thin film transistor is arranged on the substrate; the switch thin film transistor and the photosensitive thin film transistor are arranged at the same layer and at intervals; the switch thin film transistor comprises a first semiconductor layer and a shading layer which are positioned on the substrate; the photosensitive thin film transistor includes a second semiconductor layer on the substrate.
According to the method, the light shielding layer and the semiconductor layer are prepared by adopting the same photomask manufacturing process, so that the manufacturing process of the array substrate is reduced, the production cost of the prior art is reduced, and the productivity benefit is improved; meanwhile, the shading layer above the first semiconductor layer is reserved, so that the characteristics of the switch thin film transistor are guaranteed, and meanwhile, the influence of illumination on the characteristics of the switch thin film transistor is avoided; and the light shielding layer on the photosensitive thin film transistor is removed through dry etching, so that the photosensitivity of the photosensitive thin film transistor is enhanced.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained in the present application by applying specific examples, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The preparation method of the array substrate is characterized by comprising the following steps:
step S10: forming a first metal layer on a substrate, and carrying out patterning treatment on the first metal layer to form a first electrode and a second electrode which are arranged at intervals;
step S20: forming an insulating layer, a semiconductor layer, and a light shielding layer on the substrate, the first electrode, and the second electrode;
step S30: patterning the light shielding layer and the semiconductor layer by using a mask plate to form a first semiconductor layer and a first light shielding layer which are positioned above the first electrode, and a second semiconductor layer which is positioned above the second electrode;
step S40: and forming a second metal layer on the first shading layer, the insulating layer and the second semiconductor layer, and patterning the second metal layer to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.
2. The method for preparing an array substrate according to claim 1, wherein the step 30 comprises the steps of:
step S31: preparing a photoresist on the shading layer;
step S32: exposing the photoresist by using a mask plate, and then developing the photoresist to form a first photoresist layer positioned above the first electrode and a second photoresist layer positioned above the second electrode, wherein the thickness of the first photoresist layer is greater than that of the second photoresist layer;
step S33: etching the shading layer and the semiconductor layer which are not covered by the first light resistance layer and the second light resistance layer to form a first semiconductor layer and a first shading layer which are positioned above the first electrode, and a second semiconductor layer and a second shading layer which are positioned above the second electrode;
step S34: ashing the first photoresist layer and the second photoresist layer to completely strip the second photoresist layer and thin the first photoresist layer to form a first sub-photoresist layer;
step S35: etching the second shading layer by adopting an etching process;
step S36: and stripping the first sub photoresist layer.
3. The method according to claim 2, wherein in step S32, masks with different transmittances are used to perform a masking process on the photoresist; the mask plate comprises a first penetration rate area, a second penetration rate area and a third penetration rate area;
the first transmittance region corresponds to the first electrode and is opaque; the second penetration rate area corresponds to the second electrode, and the penetration rate of the second penetration rate area is 50%; the third transmittance region corresponds to the remaining region and has a transmittance of 100%.
4. The method for preparing an array substrate according to claim 2, wherein the step S33 comprises the following steps:
step S331: etching the light shielding layer which is not covered by the first light resistance layer and the second light resistance layer by adopting a dry etching process;
step S332: and etching the semiconductor layer uncovered by the first light resistance layer and the second light resistance layer by adopting a wet etching process.
5. The method for preparing an array substrate of claim 1, wherein the step S40 comprises the following steps:
step S41: depositing a second metal layer on the first light-shielding layer, the insulating layer and the second semiconductor layer;
step S42: and patterning the second metal layer through a mask plate to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first light shielding layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.
6. An array substrate, comprising:
a substrate;
the switching thin film transistor is arranged on the substrate in an array mode and comprises a first electrode and a first semiconductor layer which are arranged in a stacked mode;
the photosensitive thin film transistor is arranged on the substrate and comprises a second electrode and a second semiconductor layer which are arranged in a stacked mode;
the switch thin film transistor and the photosensitive thin film transistor are arranged at intervals, and the switch thin film transistor further comprises a shading layer located above the first semiconductor layer.
7. The array substrate of claim 6, wherein the array substrate comprises a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a passivation layer in a stacked arrangement;
the first metal layer is arranged on the substrate and comprises the first electrode and the second electrode which are arranged at intervals;
the insulating layer is arranged above the first metal layer;
the semiconductor layer is disposed over the insulating layer, the semiconductor layer including the first semiconductor layer and the second semiconductor layer;
the second metal layer is arranged above the semiconductor layer and comprises a third electrode and a fourth electrode which are positioned in two opposite edge areas of the light shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer;
the passivation layer is disposed over the insulating layer.
8. The array substrate of claim 7, wherein the switching thin film transistor comprises the first electrode, the first semiconductor layer, the light shielding layer, the third electrode, and the fourth electrode on the substrate;
the photosensitive thin film transistor comprises the second electrode, the second semiconductor layer, the fifth electrode and the sixth electrode which are positioned on the substrate; wherein,
the first semiconductor layer and the second semiconductor layer each include a first metal oxide layer and a second metal oxide layer which are stacked.
9. The array substrate of claim 7, wherein the first semiconductor layer, the light-shielding layer and the second semiconductor layer are formed by a same photo-masking process.
10. The array substrate of claim 6, wherein the light shielding layer is made of molybdenum oxide.
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| CN202011408407.XA CN112542470A (en) | 2020-12-04 | 2020-12-04 | Array substrate and preparation method thereof |
| PCT/CN2020/141157 WO2022116340A1 (en) | 2020-12-04 | 2020-12-30 | Array substrate and preparation method therefor |
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| CN202011408407.XA CN112542470A (en) | 2020-12-04 | 2020-12-04 | Array substrate and preparation method thereof |
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| WO2022116340A1 (en) | 2022-06-09 |
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