CN203367291U - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN203367291U CN203367291U CN 201320456567 CN201320456567U CN203367291U CN 203367291 U CN203367291 U CN 203367291U CN 201320456567 CN201320456567 CN 201320456567 CN 201320456567 U CN201320456567 U CN 201320456567U CN 203367291 U CN203367291 U CN 203367291U
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- light shield
- shield layer
- pixel electrode
- array base
- base palte
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Abstract
The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel areas, each pixel area comprises a transmittance area and a thin film transistor, the thin film transistor is provided with a drain electrode, and the transmittance area is provided with a pixel electrode. The surface of the thin film transistor corresponding to the position of an active layer is provided with a first light shielding layer, the surface of the thin film transistor corresponding to the drain electrode and the position between the drain electrode and the pixel electrode of the transmittance area are provided with a second light shielding layer, the second light shielding layer is a conductive light shielding layer, and the pixel electrode is connected with the drain electrode of the thin film transistor via the second light shielding layer. The first light shielding layer and the second light shielding layer are provided so that light above the active layer is prevented, the abnormity of device performance due to light influence is prevented, the requirement of the angle of gradient of a via is lowered, and the display effect and the stability of the display device are improved.
Description
Technical field
The utility model relates to the Display Technique field, particularly a kind of array base palte, display floater and display unit.
Background technology
Along with the development of Display Technique, stability and the display effect of display device more and more receive publicity.In the display device manufacture process, the semi-conducting material adopted due to the active layer of thin-film transistor has photoconductive effect, light state is being arranged and changing greatly without electrology characteristics such as its ON state current and off-state currents under light state, problems such as drift easily occur is being arranged under light state.Amorphous silicon hydride in semi-conducting material is under the visible ray prolonged exposure simultaneously, produced new silicon hanging key defect state in band gap, Fermi level near the conduction band side moves to the valence band direction, required activation energy increases, electron lifetime reduces, its dark conductivity and photoconductivity can descend in time, make its ON state current reduce.
The utility model content
(1) technical problem that will solve
The technical problems to be solved in the utility model is: how a kind of array base palte, display floater and display unit are provided, extraneous light be can reduce on the impact of thin-film transistor and to the requirement of the via hole angle of gradient, thereby display effect and the stability of display improved.
(2) technical scheme
For solving the problems of the technologies described above, the utility model provides a kind of array base palte, described array base palte comprises a plurality of pixel regions, each pixel region comprises transmission region and thin-film transistor, be provided with drain electrode on thin-film transistor, transmission region is provided with pixel electrode, the position of the corresponding active layer of described film crystal tube-surface is provided with the first light shield layer, the position of the corresponding drain electrode of film crystal tube-surface and the position between drain electrode and pixel electrode are provided with the second light shield layer, described the second light shield layer is conductive shading, the drain electrode of described pixel electrode and thin-film transistor is connected by described the second light shield layer.
Preferably, the position of the corresponding drain electrode of described thin-film transistor is provided with via structure, and the drain electrode of described pixel electrode and thin-film transistor is connected by the second light shield layer by described via structure.
Preferably, described the first light shield layer is connected for same light shield layer with the second light shield layer.
Preferably, be provided with the 3rd light shield layer between the pixel electrode of described array base palte and data wire cabling, the 4th light shield layer is set between pixel electrode and grid line.
Preferably, described the second light shield layer covers the end that described the second light shield layer is connected with pixel electrode.
The utility model provides a kind of display floater, it is characterized in that, described display floater comprises described array base palte.
The utility model also provides a kind of display unit, it is characterized in that, described display unit comprises described array base palte.
(3) beneficial effect
Array base palte of the present utility model, display floater and display unit arrange the first light shield layer by the position at the corresponding active layer of described film crystal tube-surface, in the position of the corresponding drain electrode of film crystal tube-surface and the position between drain electrode and transmission region pixel electrode, the second light shield layer is set, thereby stop the illumination from the active layer top, prevent the abnormal of the device performance that causes due to light impact, improved display effect and the stability of display unit.Because the second light shield layer is conductive shading, realized the conducting of drain electrode and pixel electrode simultaneously, made the restriction to described conductive shading thickness reduce, do not needed to be consistent with pixel electrode thickness, thereby reduced the requirement to the via hole angle of gradient.
The accompanying drawing explanation
Fig. 1 is the structural representation of the utility model embodiment array base palte;
Fig. 2 is the profile of the utility model embodiment array base palte.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for the utility model is described, but are not used for limiting scope of the present utility model.
The array base palte of the utility model embodiment as shown in Figure 1, array base palte comprises a plurality of pixel regions, each pixel region comprises transmission region 101 and thin-film transistor 102, be provided with drain electrode 103 on thin-film transistor 102, transmission region 101 is provided with pixel electrode 104, the position of described thin-film transistor 102 surperficial corresponding active layers is provided with the first light shield layer 105, the position of the corresponding drain electrode 103 of film crystal tube-surface and the position between drain electrode and transmission region pixel electrode 104 are provided with the second light shield layer 106, described the second light shield layer 106 is conductive shading, the drain electrode 103 of described pixel electrode 104 and thin-film transistor 102 is connected by described the second light shield layer 106.
In the present embodiment, the first light shield layer and the second light shield layer can synchronously form when making.The thickness of light shield layer can be by designer's free setting according to circumstances, to reach good shaded effect.
Position between position by the position at the corresponding active layer of described film crystal tube-surface and the corresponding drain electrode of film crystal tube-surface and the pixel electrode of drain electrode and transmission region arranges light shield layer, because light shield layer is light tight, thereby stop the illumination from the active layer top, prevent the abnormal of the device performance that causes due to light impact, improved display effect and the stability of display.The second light shield layer is conductive shading, not only realize the effect of shading but also realized the conducting of drain electrode and pixel electrode, make the restriction to described conductive shading thickness reduce, do not need to be consistent with pixel electrode thickness, thereby reduced the requirement to the via hole angle of gradient.
Further, the position of the corresponding drain electrode 103 of described thin-film transistor 102 is provided with via structure 107, and the drain electrode 103 of described pixel electrode 104 and thin-film transistor 102 is connected by the second light shield layer 106 by described via structure 107.
Further, can also between the pixel electrode of array base palte and data wire cabling, be provided with the 3rd light shield layer, be provided with the 4th light shield layer between pixel electrode and grid line, for blocking near the light leak of data wire cabling and grid line, thereby solved the light leak problem that between pixel electrode and data wire cabling and grid line, electric field causes extremely.
Concrete, the profile of described array base palte as shown in Figure 2, its hatching is the horizontal dark dotted line in Fig. 1, described array base palte comprises on substrate 201, substrate and is formed with gate electrode 202, be formed with gate insulation layer 203 on gate electrode 202, be formed with active layer 204 on gate insulation layer 203, be formed with source-drain electrode layer 205 on active layer 204, be formed with passivation layer 206 on source-drain electrode layer 205, described substrate 201, grid layer 202, gate insulation layer 203, active layer 204, source-drain electrode layer 205 and passivation layer 206 form described thin-film transistor 102.Transmission region is formed with pixel electrode 104, source-drain electrode layer 205 comprises source electrode 207 and drain electrode 103, the position of the corresponding drain electrode 103 of described passivation layer 206 is provided with via structure 107, described the first light shield layer 105 is formed on the passivation layer 206 of corresponding active layer 204 positions, and described the second light shield layer 106 covers described via structure 107 and connects described drain electrode 103 and pixel electrode 104.
Wherein, the first light shield layer 105 and the second light shield layer 106 can interconnect for same light shield layer, when making, can form together, and the distance of pixel electrode 104 and via structure 107, can be by designer's free setting according to circumstances.For the second light shield layer better is communicated with pixel electrode, the second light shield layer can small part covers on the end that pixel electrode is connected with the second light shield layer.
The material of the first light shield layer occurred in the present embodiment, the second light shield layer the 3rd light shield layer the 4th light shield layer is selected from lighttight metal material or organic conductive polymeric material, have simultaneously and shut out the light and the characteristic of conducting electricity, described metal material can be selected from one or more in the materials such as molybdenum, copper, aluminium.
Following table is same array basal plate, same test point light is arranged and without the TFT electrical performance testing result under optical condition:
Wherein, Ion is ON state current, Ioff is off-state current, Vth is threshold voltage, Mob is the electric charge free mobility, the average result that the Avg average is the whole test points of each parameter, the root mean square result that STDev root mean square is the whole test points of each parameter, the Min minimum value is the minimum value in the whole test points of each parameter, and the Max maximum is the maximum in the whole test points of each parameter.As can be seen from the table, under illumination condition, due to photoconductive effect, its Ion compares unglazed according to obviously becoming large in situation with the Ioff value, and threshold voltage diminishes, data also shown have light with without under optical condition, traditional back of the body channel etching film transistor device exists under illumination condition, there is skew in its electric property, the array base palte of the embodiment of the present invention, due to light shield layer being set above active layer, can effectively shut out the light, effectively avoid the impact of the semi-conducting material of light pair array substrate film transistor active layer, its test effect is identical in the test effect without under optical condition with the prior art film transistor device.
The manufacture method of the array base palte of the utility model embodiment, in the manufacturing process such as four mask technique, grid photoetching, source-drain electrode and active layer photoetching process are same as the prior art, at this, have just repeated no more.
In the via photo carving technology, after deposit passivation layer and pixel electrode, via area is divided into the S1 zone of via hole part, the S2 zone between via hole and pixel electrode layer, the S3 zone of pixel electrode part.When adopting positive photoresist, adopt full exposure technology in the S1 zone, adopt half exposure technology in the S2 zone, the S3 zone adopts not exposure technology.
After the via hole photolithographic exposure, etch process flow is as follows:
The first step, after end exposure, via hole part exposure region (S1) is without positive photoresist, half exposure area (S2) has positive photoresist to exist with unexposed area (S3), can at first adopt wet etching that pixel electrode in exposure region (S1 district) via hole is removed, then adopt dry the quarter that the passivation layer of exposure region (S1 district) is etched away, form via hole.Now half exposure area (S2) has positive photoresist to exist with unexposed area (S3), therefore S2, S3 area pixel electrode and passivation layer are all intact.
Second step, adopt the dry etching ash to melt the positive photoresist of half exposure area (S2), removes the pixel electrode in half exposure area (S2 zone) with the pixel electrode etching liquid.This step is mainly to form the pixel region pixel electrode pattern, for example, in the formation of the tabular pixel electrode of twisted nematic mode (needing the pixel electrode on whole glass substrate is etched into to tabular pixel electrode one by one according to pixel) and the senior super dimension translative mode formation (half exposure area can be etched into pixel electrode one by one according to pixel by pixel electrode herein, or pixel electrode is etched into to list structure) of strip pixel electrode.
The 3rd step, peel off the residue positive photoresist in S3 zone, forms via hole and pixel electrode structure.
After above-mentioned via hole photoetching finishes, carry out the light shield layer photoetching process, at first (this conductive shading is that conduction and opaque material get final product to whole glass substrate depositing electrically conductive light shield layer, be preferably opaque metal), then gluing develops, form pattern at channel structure and via structure exposure, then by common wet-etching technology, complete the etching of conductive shading, form the conductive shading pattern that connects via hole and pixel electrode.The conductive shading that wherein plays the link effect overlaps with pixel electrode part or all overlaps, to guarantee that connection effectively.Preferably, can also be between the pixel electrode and data wire cabling of array substrate pixel structure, make light shield layer between pixel electrode and grid line, for blocking near the light leak of data wire cabling and grid line, thereby solved the light leak problem that between pixel electrode and data wire cabling and grid line, electric field causes extremely.
After the light shield layer pattern of above three positions forms, the film transistor device function realizes, the pixel functional structure completes, by light shield layer is set in the situation that do not increase display effect and the stability that photoetching process has promoted device.
A kind of display floater of the utility model embodiment, described display floater comprises described array base palte.
A kind of display unit of the utility model embodiment, described display unit comprises described array base palte.
Above execution mode is only for illustrating the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that do not break away from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (9)
1. an array base palte, described array base palte comprises a plurality of pixel regions, each pixel region comprises transmission region and thin-film transistor, be provided with drain electrode on thin-film transistor, transmission region is provided with pixel electrode, it is characterized in that, the position of the corresponding active layer of described film crystal tube-surface is provided with the first light shield layer, the position of the corresponding drain electrode of film crystal tube-surface and the position between drain electrode and pixel electrode are provided with the second light shield layer, described the second light shield layer is conductive shading, the drain electrode of described pixel electrode and thin-film transistor is connected by described the second light shield layer.
2. array base palte as claimed in claim 1, is characterized in that, the position of the corresponding drain electrode of described thin-film transistor is provided with via structure, and the drain electrode of described pixel electrode and thin-film transistor is connected by the second light shield layer by described via structure.
3. array base palte as claimed in claim 1, is characterized in that, described the first light shield layer is connected for same light shield layer with the second light shield layer.
4. array base palte as claimed in claim 1, is characterized in that, is provided with the 3rd light shield layer between the pixel electrode of described array base palte and data wire cabling, is provided with the 4th light shield layer between pixel electrode and grid line.
5. array base palte as claimed in claim 1, is characterized in that, described the second light shield layer covers the end that described the second light shield layer is connected with pixel electrode.
6. array base palte as claimed in claim 4, is characterized in that, the material of described the first light shield layer, the second light shield layer, the 3rd light shield layer, the 4th light shield layer is selected from lighttight metal material or organic conductive polymeric material.
7. array base palte as claimed in claim 6, is characterized in that, described metal material is selected from one or more in molybdenum, copper, aluminium.
8. a display floater, is characterized in that, described display floater comprises the described array base palte of claim 1-7 any one.
9. a display unit, is characterized in that, described display unit comprises the described array base palte of claim 1-7 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320456567 CN203367291U (en) | 2013-07-29 | 2013-07-29 | Array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320456567 CN203367291U (en) | 2013-07-29 | 2013-07-29 | Array substrate, display panel and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093618A (en) * | 2017-05-04 | 2017-08-25 | 京东方科技集团股份有限公司 | Image element circuit structure and use its display device |
| CN108389833A (en) * | 2018-03-26 | 2018-08-10 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method and display device |
| CN110112193A (en) * | 2019-04-29 | 2019-08-09 | 上海天马微电子有限公司 | Organic light emitting display panel and organic light-emitting display device |
| CN111725242A (en) * | 2020-06-30 | 2020-09-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
-
2013
- 2013-07-29 CN CN 201320456567 patent/CN203367291U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093618A (en) * | 2017-05-04 | 2017-08-25 | 京东方科技集团股份有限公司 | Image element circuit structure and use its display device |
| CN108389833A (en) * | 2018-03-26 | 2018-08-10 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method and display device |
| CN108389833B (en) * | 2018-03-26 | 2021-01-29 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| US10943928B2 (en) | 2018-03-26 | 2021-03-09 | Boe Technology Group Co., Ltd. | Display substrate, method for manufacturing the same and display device |
| CN110112193A (en) * | 2019-04-29 | 2019-08-09 | 上海天马微电子有限公司 | Organic light emitting display panel and organic light-emitting display device |
| CN111725242A (en) * | 2020-06-30 | 2020-09-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN111725242B (en) * | 2020-06-30 | 2022-09-02 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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