CN103151304B - Array substrate of display panel and manufacturing method thereof - Google Patents
Array substrate of display panel and manufacturing method thereof Download PDFInfo
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- CN103151304B CN103151304B CN201210570674.6A CN201210570674A CN103151304B CN 103151304 B CN103151304 B CN 103151304B CN 201210570674 A CN201210570674 A CN 201210570674A CN 103151304 B CN103151304 B CN 103151304B
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- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 142
- 239000011241 protective layer Substances 0.000 claims abstract description 100
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000010409 thin film Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 208000034699 Vitreous floaters Diseases 0.000 claims 15
- 238000001459 lithography Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000012447 hatching Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000013039 cover film Substances 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Abstract
A method for manufacturing an array substrate of a display panel includes the following steps. A substrate is provided, and a thin film transistor and a connection electrode are formed on the substrate. A first protective layer and a flat layer are formed on the substrate, the flat layer is provided with a first opening and a second opening, and the first opening corresponds to a drain electrode and a connecting electrode of the thin film transistor. Forming a common electrode, a second protection layer and a photoresist pattern layer, wherein the photoresist pattern layer exposes the second protection layer corresponding to the common electrode and the second opening in the first opening. And etching the second protection layer exposed by the photoresist pattern layer to form a third opening, a fourth opening and a fifth opening, etching the first protection layer exposed by the third opening and the fourth opening to form a sixth opening and a seventh opening, and exposing the drain electrode and the connecting electrode. And removing the photoresist pattern layer, and forming a bridging electrode and a pixel electrode on the second protective layer.
Description
Technical field
The present invention relates to array base palte of a kind of display floater and preparation method thereof, particularly relate to one and can reduce array base palte of the display floater of micro-shadow and etch process (photolithography and etching process, hereinafter referred to as PEP) together and preparation method thereof.
Background technology
Flat-panel screens, such as liquid crystal display, owing to having compact, the characteristic such as Low emissivity and low power consumption, replaced traditional cathode ray tube (cathode ray tube, CRT) display, and become the main flow of display.In the development of display, constantly towards the future development that high-resolution requires.But along with the raising of resolution, on panel, the quantity of thin-film transistor (thin film transistor, TFT) also improves, and makes the utilized space on panel constantly reduce thereupon.Meanwhile, in order to improve the usefulness of aperture opening ratio and thin-film transistor, technological design further increases the number of times of PEP.But, reducing and the raising of PEP number of space can be utilized, cause the degree of difficulty of technology controlling and process and cost to continue to raise, and be unfavorable for making and the development of display floater, also therefore the manufacture method of display is there's no one who doesn't or isn't important developing goal to reduce by PEP number now.
It can thus be appreciated that, still need one can reduce difficulty in process degree and process costs at present, effectively can improve dot structure that before and after flatness layer, rete is electrically connected and preparation method thereof simultaneously.
Summary of the invention
An object of the present invention is array base palte providing a kind of display floater and preparation method thereof, to reduce difficulty in process degree and process costs, improves the yield of display floater simultaneously.
For reaching above-mentioned purpose, the invention provides the method for the array base palte making display floater.Said method comprises the following steps.First provide substrate, substrate has pixel region and surrounding zone, is formed with at least one thin-film transistor in the pixel region of substrate, and thin-film transistor comprises gate electrode, source electrode and drain electrode, is then formed with at least one connecting electrode in the surrounding zone of substrate.Next on substrate, sequentially form the first protective layer and flatness layer, the first protective layer cover film transistor AND gate connecting electrode, flatness layer covers the first protective layer.Flatness layer has the first opening and the second opening, and the first opening corresponds to drain electrode and part first protective layer exposed on drain electrode, and the second opening then corresponds to connecting electrode and part first protective layer exposed on connecting electrode.Subsequently, on flatness layer, form the first patterned transparent conductive layer, and the first patterned transparent conductive layer comprises common electrode.After formation first patterned transparent conductive layer, in the first patterned transparent conductive layer and flatness layer, form the second protective layer, and form photoresist design layer on the second protective layer.Photoresist design layer exposes part second protective layer in the first opening and in the second opening, and exposes part second protective layer corresponding to common electrode.Next; the second protective layer that etching photoresist design layer exposes; to form the 3rd opening, the 4th opening and the 5th opening in the second protective layer; 3rd opening exposes part first protective layer in the first opening; 4th opening exposes part first protective layer in the second opening, and the 5th opening then exposes part common electrode.And after formation the 3rd opening, the 4th opening and the 5th opening; etch the first protective layer that the 3rd opening and the 4th opening expose; to form the 6th opening and the 7th opening in the first protective layer; 6th opening exposes part drain electrode, and the 7th opening then exposes part connecting electrode.Next, remove photoresist design layer, on the second protective layer, form the second patterned transparent conductive layer subsequently.Second patterned transparent conductive layer comprises the surrounding zone that bridged electrodes is positioned at substrate, and pixel electrode is positioned at the pixel region of substrate, bridged electrodes is electrically connected common electrode and connecting electrode via the 5th opening and the 7th opening, pixel electrode then via the 6th opening be electrically connected drain electrode, and pixel electrode and bridged electrodes electrically isolated.
For reaching above-mentioned purpose, the present invention separately provides a kind of array base palte of display floater.The array base palte of above-mentioned display floater comprises the substrate with pixel region and surrounding zone, at least one thin-film transistor be arranged in the pixel region of substrate, at least one connecting electrode be arranged in the surrounding zone of substrate, be arranged at the first protective layer of also cover film transistor AND gate connecting electrode on substrate, be arranged at the flatness layer on the first protective layer, be arranged at the common electrode on flatness layer, be arranged at the second protective layer on common electrode and flatness layer, to be arranged on the second protective layer and to be positioned at the bridged electrodes of the surrounding zone of substrate and to be arranged on the second protective layer and to be positioned at the pixel electrode of the pixel region of substrate.Thin-film transistor comprises gate electrode, source electrode and drain electrode.First protective layer has the 6th opening and the 7th opening, the 6th opening emerges part drain electrode and the 7th opening emerges part connecting electrode.Flatness layer comprises the first opening and the second opening, and the first opening corresponds to the 6th opening and exposes part drain electrode, and the second opening corresponds to the 7th opening and exposes part connecting electrode.Second protective layer has the 3rd opening, the 4th opening and the 5th opening, and the 3rd opening corresponds to the first opening and exposes part drain electrode, and the 4th opening corresponds to the second opening and exposes part connecting electrode, and the 5th opening then exposes part common electrode.Bridged electrodes is electrically connected common electrode and connecting electrode via the 5th opening and the 7th opening; And pixel electrode is electrically connected drain electrode via the 6th opening.
Accompanying drawing explanation
The schematic diagram of the method for the array base palte of the making display floater that Fig. 1 to Fig. 8 provides for one embodiment of the invention, the wherein schematic top plan view of array base palte that provides for the present embodiment of Fig. 1, Fig. 2 to Fig. 8 then shows the generalized section along A-A ' hatching line and B-B ' hatching line gained in Fig. 1;
The schematic diagram of the method for the array base palte of the making display floater that Fig. 9 to Figure 10 provides for another embodiment of the present invention.
Reference numeral
100: array base palte 102: pixel region
104: surrounding zone 110: substrate
112: gate electrode 114: insulating barrier
116a: source electrode 116b: drain electrode
118: connecting electrode 120: patterned semiconductor layer
120a: patterned semiconductor layer 120b: patterning protective layer
130: thin-film transistor 140: the first protective layer
142: the six opening 144: the seven openings
150: flatness layer 152: the first opening
154: the second openings 160: common electrode
170: the second protective layer 172: the three openings
174: the four opening 176: the five openings
180: photoresist design layer 190: bridged electrodes
192: pixel electrode 194: slit
GL: gate line DL: data wire
M1: patterned first metal layer M2: patterning second metal level
A-A ': hatching line B-B ': hatching line
Embodiment
For making the those skilled in the art being familiar with the technical field of the invention further can understand the present invention, below enumerate preferred embodiment of the present invention, and coordinate appended accompanying drawing, the effect describing constitution content of the present invention in detail and will reach.
Please refer to Fig. 1 to Fig. 8, Fig. 1 to Fig. 8 shows the schematic diagram of the method for the array base palte of the making display floater that one embodiment of the invention provide, the wherein schematic top plan view of the array base palte of display floater that provides for the present embodiment of Fig. 1, Fig. 2 to Fig. 8 then shows the generalized section along A-A ' hatching line and B-B ' hatching line gained in Fig. 1.As shown in Figures 1 and 2, substrate 110 is first provided.Substrate 110 can be rigid substrate such as glass substrate, or flexible substrate such as plastic base, but not as limit, on substrate 110, definition has pixel region 102 and surrounding zone 104 in addition.Next on substrate 110, form patterned first metal layer M1, wherein patterned first metal layer M1 comprises gate electrode 112, is arranged in pixel region 102.And patterned first metal layer M1 also can comprise the gate lines G L(that is electrically connected with gate electrode 112 as shown in Figure 1) etc. element.Patterned first metal layer M1 can be single metal layer or more metal layers, its material can be various there is satisfactory electrical conductivity metal, alloy or its combination, but not as limit.After formation patterned first metal layer M1, form the insulating barrier 114 of cover gate electrode 112.Insulating barrier 114 is as the use of gate insulator, and its material can be silica, silicon nitride or silicon oxynitride etc., but also not as limit.
Please continue to refer to Fig. 2.Subsequently, form patterning second metal level M2 on insulating barrier 114, patterning second metal level M2 can be single metal layer or more metal layers, and the material of patterning second metal level M2 can be various there is satisfactory electrical conductivity metal, alloy or its combination.Patterning second metal level M2 comprises source electrode 116a, drain electrode 116b and connecting electrode 118.Source electrode 116a and drain electrode 116b is formed in pixel region 102, and corresponds to gate electrode 112.Connecting electrode 118 is formed in surrounding zone 104, and the element such as connecting electrode 118 and gate electrode 112, source electrode 116a and drain electrode 116b is all electrically isolated.Patterning second metal level M2 also can comprise the data wire DL(that is electrically connected with source electrode 116a as shown in Figure 1).Should be noted in addition, for meeting the circuit design needs in surrounding zone 104, when forming patterned first metal layer M1, also can form common line (not shown) in surrounding zone 104, insulating barrier 114 also can cover the common line (not shown) in surrounding zone 104.Further, before formation patterning second metal level M2, prior to forming the opening (not shown) of an expose portion common line in the insulating barrier 114 of the common line in surrounding zone 104, therefore connecting electrode 118 is electrically connected by this opening and common line.
Refer to Fig. 3.After formation patterning second metal level M2, on insulating barrier 114, sequentially form patterned semiconductor layer 120a and patterning protective layer 120b.As shown in Figure 3, patterned semiconductor layer 120a and patterning protective layer 120b corresponds to gate electrode 112 and cover part source electrode 116a and part drain electrode 116b.In the present embodiment, patterned semiconductor layer 120a can comprise patterned oxide semiconductor layer, such as indium oxide gallium zinc (indium gallium zinc oxide, IGZO) layer; Patterning protective layer 120b then can comprise inorganic protective layer such as silicon oxide layer, but is all not limited thereto.The material of patterned semiconductor layer 120a also can comprise other semi-conducting material, and the material of patterning protective layer 120b also can be other inorganic or organic material.As shown in Figure 3, at least one thin-film transistor 130 is formed in the pixel region 102 of the present embodiment so far on substrate 110.Owing to forming the step of each composition rete of thin-film transistor 130 known by those skilled in the art in the art, therefore these details repeat no more in this.
Please continue to refer to Fig. 3.After the making completing thin-film transistor 130, the present embodiment sequentially forms the first protective layer 140 and flatness layer 150, first protective layer 140 cover film transistor 130 and connecting electrode 118 on substrate 110; Flatness layer 150 then covers the first protective layer 140.First protective layer 140 can comprise inorganic protective layer such as silicon nitride; Flatness layer 150 can comprise organic insulation layers as acrylic layer, but is all not limited thereto.It should be noted that; as shown in Figure 3; flatness layer 150 has the first opening 152 and the second opening 154; first opening 152 corresponds to drain electrode 116b and part first protective layer 140, second opening 154 exposed on drain electrode 116b then corresponds to connecting electrode 118 and part first protective layer 140 exposed on connecting electrode 118.Flatness layer 150 is better can use sense optical activity material, and the first opening 152 and the second opening 154 can utilize exposure imaging technique to be defined whereby.As shown in Figure 3, flatness layer 150 has thicker thickness, to make substrate 110 to obtain a comparatively smooth surface, and is conducive to the rotation of liquid crystal molecule.
Refer to Fig. 4.After formation has the flatness layer 150 of the first opening 152 and the second opening 154, then on substrate 110, namely on flatness layer 150, form the first patterned transparent conductive layer.In the present embodiment, the first patterned transparent conductive layer comprises common electrode 160.First patterned transparent conductive layer can comprise transparency conducting layer, such as tin indium oxide (indium tin oxide, ITO) layer, but is not limited thereto.Common electrode 160 is formed at surrounding zone 104 with on the flatness layer 150 in pixel region 102, and is a successional rete, but common electrode 160 is all electrically isolated with the element such as thin-film transistor 130 and connecting electrode 118.
Refer to Fig. 5.After formation first patterned transparent conductive layer; namely after forming common electrode 160; in the first patterned transparent conductive layer (i.e. common electrode 160) with flatness layer 150, form the second protective layer 170, and form photoresist design layer 180 on the second protective layer 170.Second protective layer 170 can have identical inorganic material such as silicon nitride with the first protective layer 140, but also can comprise other material and be not limited thereto.Photoresist design layer 180 exposes part second protective layer 170 in the first opening 152 and the second opening 154.The more important thing is, photoresist design layer 180 exposes part second protective layer 170 corresponding to common electrode 160 as shown in Figure 5 in surrounding zone 104.
Refer to Fig. 6.After formation photoresist design layer 180, utilize the second protective layer 170 that etch process etching photoresist design layer 180 exposes, to form the 3rd opening 172, the 4th opening 174 and the 5th opening 176 in the second protective layer 170.As shown in Figure 6; 3rd opening 172 part first protective layer the 140, the 4th opening 174 part first protective layer the 140, five opening 176 exposed in the second opening 154 exposed in the first opening 152 then exposes the part common electrode 160 in surrounding zone 104.
Refer to Fig. 7.After formation the 3rd opening 172, the 4th opening 174 and the 5th opening 176; continue to utilize photoresist design layer 180 as etch shield; etch the first protective layer 140 that the 3rd opening 172 and the 4th opening 174 expose, and form the 6th opening 142 and the 7th opening 144 in the first protective layer 140.As shown in Figure 7, the 6th opening 142 is less than the first opening 152, and in like manner the 7th opening 144 is less than the second opening 154.The more important thing is, the 6th opening 142 exposes part drain electrode 166b; And the 7th opening 144 exposes part connecting electrode 118.Therefore; after the etch process completing the first protective layer 140, the part common electrode 160 in surrounding zone 104 is exposed in the 5th opening 176, part drain electrode 166b is exposed to part connecting electrode 118 in the 6th opening 142 and is then exposed in the 7th opening 144.
Refer to Fig. 8.After formation the 6th opening 142 and the 7th opening 144, namely remove photoresist design layer 180.Subsequently, on the second protective layer 170 and in the 5th opening 176, the 6th opening 142 and the 7th opening 144, the second patterned transparent conductive layer is formed.In the present embodiment, the second patterned transparent conductive layer comprises bridged electrodes 190 and pixel electrode 192, and bridged electrodes 190 is preferably and comprises isolated island shape, and electrically isolated with pixel electrode 192.Because the second patterned transparent conductive layer comprises pixel electrode 192, therefore be preferably a transparency conducting layer, such as an ITO layer, but be not limited thereto.In other words, bridged electrodes 190 and pixel electrode 192 are made up of same layer patterned transparent conductive layer.As shown in Figure 8, pixel electrode 192 is electrically connected to the drain electrode 116b be exposed in the 6th opening 142.The more important thing is, in the present embodiment, the bridged electrodes 190 of the second patterned transparent conductive layer as shown in Figure 8, is electrically connected the first patterned transparent conductive layer (i.e. common electrode 160) be exposed in the 5th opening 176 and the connecting electrode 118 be exposed in the 7th opening 144.In other words, connecting electrode 118 and common electrode 160 are electrically connected by bridged electrodes 190.In addition, in the present embodiment, the pixel electrode 192 in pixel region 102 can have multiple slit (slit) 194 as shown in Figure 1, but the mode being familiar with slit 194 in personnel Ying Zhi Fig. 1 of correlation technique is only illustration, and is not limited thereto.
Please again consult Fig. 1 and Fig. 8.The method of the array base palte of the making display floater provided according to the present embodiment, provide array base palte 100, array base palte 100 comprises substrate 110, and on substrate 110, definition has pixel region 102 and surrounding zone 104.Array base palte 100 also comprises at least one connecting electrode 118 and at least one thin-film transistor 130, connecting electrode 118 is arranged in the surrounding zone 104 of substrate 110, and thin-film transistor 130 is arranged in the pixel region 102 of substrate 110, and thin-film transistor 130 comprises gate electrode 112, source electrode 116a and drain electrode 116b.Array base palte 100 comprises be arranged on substrate 110 and cover connecting electrode 118 and the first protective layer 140 of thin-film transistor 110, the flatness layer 150 be arranged on the first protective layer 140, be arranged on flatness layer 150 and extend into from surrounding zone 104 pixel region 102 common electrode 160, be arranged at common electrode 160 and the second protective layer 170 on flatness layer 150 and the bridged electrodes 190 be arranged on the second protective layer 170 and pixel electrode 192.As shown in Figure 8, the first protective layer 140 has the 6th opening 142 and the 7th opening the 144, six opening 142 expose portion drain electrode 116b, the 7th opening 144 then expose portion connecting electrode 118.Flatness layer 150 comprises the first opening 152 and the second opening 154, first opening 152 corresponds to the 6th opening 142 and exposes part drain electrode 116b, and the second opening 154 corresponds to the 7th opening 144 and exposes part connecting electrode 118.Second protective layer 170 has the 3rd opening 172, the 4th opening 174 and the 5th opening 176; 3rd opening 172 exposes drain electrode 116b corresponding to the first opening 152 and the 6th opening 142; 4th opening 174 exposes connecting electrode 118 corresponding to the second opening 154 and the 7th opening 144, and the 5th opening 176 exposes the part common electrode 160 in surrounding zone 104.Array base palte 100 also comprises bridged electrodes 190 and pixel electrode 192.Bridged electrodes 190 is arranged in surrounding zone 104, and be electrically connected to connecting electrode 118 by the second opening 154, the 4th opening 174 and the 7th opening 144, also be electrically connected to the common electrode 160 in surrounding zone 104 by the 5th opening 176 simultaneously, therefore the bridged electrodes 190 of this island is successfully electrically connected common electrode in surrounding zone 104 160 and connecting electrode 118, guarantees the foundation of the common electrode 160 in surrounding zone 104 and the electrical relationship of connecting electrode 118.Therefore common signal can be passed to the common electrode 160 in surrounding zone 104 by bridged electrodes 190 by the connecting electrode 118 of surrounding zone 104, and enters pixel region 102.Pixel electrode 192 is electrically connected to drain electrode 116b by the first opening 152, the 3rd opening 172 and the 6th opening 142, guarantees the foundation of pixel electrode 192 and drain electrode 116b electrical relationship.
Array base palte of the display floater provided according to the present embodiment and preparation method thereof; be used in the second protective layer 170, etching the photoresist design layer 180 of the 3rd opening 172, the 4th opening 174 and the 5th opening 176 as etch shield; therefore when etching first protective layer 140 forms the 6th opening 142 and the 7th opening 144; no longer need extra PEP step; it uses identical light shield (mask) to reduce process costs; that is, the first protective layer 140 is etched and the second protective layer 170 completes in micro-shadow and etch process.In other words, the manufacture method of the array base palte that the present embodiment provides can reduce PEP step once, effectively reaches the object reducing process costs.In addition, owing to can remove the PEP step forming the 6th opening 142 and the 7th opening 144 from, therefore array base palte of display floater provided by the present invention and preparation method thereof also can exempt the derivative problem of PEP step, such as alignment issues etc.Due to the requirement of high-resolution and high dot structure density, utilized space on panel is subject to increasing restriction, the PEP step deducted once not only can reach the object shortening the process time, reduce costs, more can avoid the derivative problem of PEP step occurs in this all the more narrow space, and then reduce process complexity.Even more noteworthy, because the present embodiment additionally provides bridged electrodes 190 in surrounding zone 104, therefore common electrode in surrounding zone 104 160 and connecting electrode 118 can be electrically connected by bridged electrodes 190.In other words, the present embodiment under the prerequisite of the electrical relationship setting up each element that assures success, can deduct PEP step once and derivative problem thereof.Briefly, array base palte of the display floater that the present embodiment provides and preparation method thereof, can reach objects such as guaranteeing product yield, Simplified flowsheet, reduction process costs and process complexity.
Refer to Fig. 9 to Figure 10, Fig. 9 to Figure 10 shows the schematic diagram of the method for the array base palte of the making display floater that another embodiment of the present invention provides.In addition it is noted that composed component identical with previous embodiment in the present embodiment uses identical symbol description.As shown in Figure 9, the manufacture method of the array base palte that the present embodiment provides, first substrate 110 is provided, in the pixel region 102 next on substrate 110, sequentially forms the insulating barrier 114 of patterned first metal layer M1 as gate electrode 112 and cover gate electrode 112.Next, patterned semiconductor layer 120 is formed on insulating barrier 114, in the present embodiment, patterned semiconductor layer 120 comprises patterning amorphous silicon semiconductor layer, but the those skilled in the art in this field should know that the material of patterned semiconductor layer 120 also can comprise other semi-conducting material.
Please continue to refer to Fig. 9.After formation patterned semiconductor layer 120, patterning second metal level M2 is formed on substrate 102, patterning second metal level M2 comprises source electrode 116a and drain electrode 116b, and source electrode 116a and drain electrode 116b corresponds to gate electrode 112 and patterned semiconductor layer 120.Therefore, the present embodiment forms at least one thin-film transistor 130 in the pixel region 102 of substrate 110.As previously mentioned, owing to forming the step of each composition rete of thin-film transistor 130 known by those skilled in the art in the art, therefore these details repeat no more in this.Refer to Figure 10.And after the making completing thin-film transistor 130, the first protective layer 140 is sequentially formed on substrate 110, there is the flatness layer 150 of the second opening 154 of the first opening 152 connecting electrode 118 corresponding to of a corresponding drain electrode 116b, comprise the first patterned transparent conductive layer of common electrode 160, second protective layer 170, with photoresist design layer 180, next photoresist design layer 180 is utilized to form the 3rd opening 172 of corresponding first opening 152 as shielding etching second protective layer 170, 4th opening 174 of corresponding second opening 154 and the 5th opening 176 of part common electrode 160 in exposed perimeter district 104.Utilize same photoresist design layer 180 to etch the first protective layer 140 as etch shield subsequently, form the 6th opening 142 and the 7th opening 144 exposing part connecting electrode 118 that expose part drain electrode 116b.That is; etch the first protective layer 140 and the second protective layer 170 completes in micro-shadow and etch process; no longer need extra PEP step, it uses identical light shield (mask), so do not need to use new light shield (mask) to reduce process costs.Next on substrate 110, the second patterned transparent conductive layer is formed, and the second patterned transparent conductive layer comprises and is formed in the first opening 152, the 3rd opening 172 and the 6th opening 142, and the pixel electrode 192 be electrically connected with drain electrode 116b, and be formed in the second opening 154, the 4th opening 174, the 7th opening 144 and the 5th opening 176, and be electrically connected the bridged electrodes 190 of common electrode 160 and connecting electrode 118.Above-mentioned steps is identical with step illustrated in aforementioned preferred embodiment, and therefore those skilled in the art in the art should according to previous embodiment and Fig. 1 to Fig. 8 apparent, therefore these details repeat no more.
According to array base palte of display floater provided by the present invention and preparation method thereof, successfully can be integrated in existing thin-film transistor technique, and can reduce by one PEP step, therefore can reduce costs and process complexity.In addition, in the manufacture method due to array base palte provided by the present invention, the bridged electrodes by island guarantees the electrical connection of common electrode and connecting electrode.In other words, array base palte provided by the present invention and preparation method thereof can under the prerequisite of the electrical relationship setting up each element in array base palte that assures success, effectively Simplified flowsheet, shorten the process time and reduce process costs and process complexity.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (15)
1. make a method for the array base palte of display floater, it is characterized in that, comprising:
One substrate is provided, this substrate has a pixel region and a surrounding zone, be formed with at least one thin-film transistor in this pixel region of this substrate, and this thin-film transistor comprises a gate electrode, one source pole electrode and a drain electrode, in this surrounding zone of this substrate, be formed with at least one connecting electrode;
One first protective layer and a flatness layer is sequentially formed on this substrate, this first protective layer covers this thin-film transistor and this connecting electrode, this flatness layer covers this first protective layer, this flatness layer has one first opening and one second opening, this first opening corresponds to this drain electrode and this first protective layer of part exposed on this drain electrode, and this second opening corresponds to this connecting electrode and this first protective layer of part exposed on this connecting electrode;
On this flatness layer, form one first patterned transparent conductive layer, wherein this first patterned transparent conductive layer comprises a common electrode;
One second protective layer is formed in this first patterned transparent conductive layer and this flatness layer;
On this second protective layer, form a photoresist design layer, this photoresist design layer exposes this second protective layer of part in this first opening and in this second opening, and exposes this second protective layer of part corresponding to this first patterned transparent conductive layer;
Etch this second protective layer that this photoresist design layer exposes, to form one the 3rd opening, one the 4th opening and one the 5th opening in this second protective layer, 3rd opening exposes this first protective layer of part in this first opening, the 4th opening exposes this first protective layer of part in the second opening, and the 5th opening exposes this common electrode of part;
Etch this first protective layer that the 3rd opening and the 4th opening expose, to form one the 6th opening and one the 7th opening in this first protective layer, 6th opening exposes this drain electrode of part, and the 7th opening exposes this connecting electrode of part, wherein etching this first protective layer and etching this second protective layer is complete in lithography technique;
Remove this photoresist design layer; And
One second patterned transparent conductive layer is formed on this second protective layer; this second patterned transparent conductive layer comprises this surrounding zone that a bridged electrodes is positioned at this substrate; and one pixel electrode be positioned at this pixel region of this substrate; this bridged electrodes is electrically connected this common electrode and this connecting electrode via the 5th opening and the 7th opening; this pixel electrode is electrically connected this drain electrode via the 6th opening, and this pixel electrode and this bridged electrodes electrically isolated.
2. the method for the array base palte of making display floater according to claim 1, is characterized in that, etches this first protective layer and etch this second protective layer to use this photoresist design layer same.
3. the method for the array base palte of making display floater according to claim 1, is characterized in that, etches this first protective layer and etch this second protective layer to use identical light shield.
4. the method for the array base palte of making display floater according to claim 1, is characterized in that, the step forming this thin-film transistor also comprises:
The insulating barrier that this gate electrode and covers this gate electrode is formed on this substrate;
This source electrode and this drain electrode is formed on this insulating barrier; And
A patterned semiconductor layer and a patterning protective layer is formed on this insulating barrier.
5. the method for the array base palte of making display floater according to claim 4, is characterized in that, this patterned semiconductor layer comprises a patterned oxide semiconductor layer.
6. the method for the array base palte of making display floater according to claim 1, is characterized in that, the step forming this thin-film transistor comprises:
The insulating barrier that this gate electrode and covers this gate electrode is formed on this substrate;
A patterned semiconductor layer is formed on this insulating barrier; And
This source electrode and this drain electrode is formed on this insulating barrier and this patterned semiconductor layer.
7. the method for the array base palte of making display floater according to claim 6, is characterized in that, this patterned semiconductor layer comprises a patterning amorphous silicon semiconductor layer.
8. an array base palte for display floater, is characterized in that, comprising:
One substrate, this substrate has a pixel region and a surrounding zone;
At least one thin-film transistor, is arranged in this pixel region of this substrate, and this thin-film transistor comprises a gate electrode, one source pole electrode and a drain electrode;
At least one connecting electrode, is arranged in this surrounding zone of this substrate;
One first protective layer, being arranged on this substrate and covering this thin-film transistor and this connecting electrode, this first protective layer has one the 6th opening and one the 7th opening, the 6th this drain electrode of opening emerges part and the 7th this connecting electrode of opening emerges part;
One flatness layer, be arranged on this first protective layer, this flatness layer comprises one first opening and one second opening, and this first opening corresponds to the 6th opening and exposes this drain electrode of part, and this second opening corresponds to the 7th opening and exposes this connecting electrode of part;
One common electrode, is arranged on this flatness layer;
One second protective layer, be arranged on this common electrode and this flatness layer, this second protective layer has one the 3rd opening, one the 4th opening and one the 5th opening, 3rd opening corresponds to this first opening and exposes this drain electrode of part, 4th opening corresponds to this second opening and exposes this connecting electrode of part, and the 5th opening exposes this common electrode of part; And
One bridged electrodes, being arranged on this second protective layer and being positioned at this surrounding zone of this substrate, this bridged electrodes is electrically connected this common electrode and this connecting electrode via the 5th opening and the 7th opening; And
One pixel electrode, being arranged on this second protective layer and being positioned at this pixel region of this substrate, this pixel electrode is electrically connected this drain electrode via the 6th opening, and wherein this bridged electrodes and this pixel electrode are same layer patterned transparent conductive layer.
9. the array base palte of display floater according to claim 8, is characterized in that, this pixel electrode and this bridged electrodes electrically isolated from each other.
10. the array base palte of display floater according to claim 8, is characterized in that, this first opening is greater than the 3rd opening and the 6th opening, and this second opening is greater than the 4th opening and the 7th opening.
The array base palte of 11. display floaters according to claim 8, is characterized in that, this thin-film transistor also comprises a patterned semiconductor layer, arranges corresponding to this gate electrode.
The array base palte of 12. display floaters according to claim 11, is characterized in that, this source electrode and this drain electrode are arranged between this patterned semiconductor layer and this gate electrode.
The array base palte of 13. display floaters according to claim 12, is characterized in that, this patterned semiconductor layer comprises a patterned oxide semiconductor layer.
The array base palte of 14. display floaters according to claim 11, is characterized in that, this patterned semiconductor layer is arranged between this source electrode and drain electrode and this gate electrode.
The array base palte of 15. display floaters according to claim 14, is characterized in that, this patterned semiconductor layer comprises a patterning amorphous silicon semiconductor layer.
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| TW101140798 | 2012-11-02 | ||
| TW101140798A TWI477869B (en) | 2012-11-02 | 2012-11-02 | Array substrate of display panel and manufacturing method thereof |
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| TWI553837B (en) | 2014-06-17 | 2016-10-11 | 友達光電股份有限公司 | Method for fabricating display panel |
| TW201627731A (en) * | 2015-01-26 | 2016-08-01 | 中華映管股份有限公司 | Array substrate and method for rubbing the same |
| CN106129063B (en) * | 2016-07-05 | 2019-06-25 | 深圳市华星光电技术有限公司 | Thin-film transistor array base-plate and its manufacturing method |
| CN108873509A (en) | 2017-05-08 | 2018-11-23 | 中华映管股份有限公司 | The method for forming dot structure |
| CN109390286B (en) * | 2017-08-09 | 2022-04-15 | 昆山国显光电有限公司 | Array substrate and manufacturing method thereof, display panel and manufacturing method thereof |
| CN109656069A (en) * | 2017-10-11 | 2019-04-19 | 京东方科技集团股份有限公司 | Production method, array substrate and the display device of array substrate |
| TWI663719B (en) * | 2018-01-30 | 2019-06-21 | 友達光電股份有限公司 | Method for manufacturing array substrate |
| CN108305879B (en) * | 2018-01-31 | 2020-12-29 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate, manufacturing method and display device |
| CN109148481B (en) * | 2018-08-21 | 2020-09-01 | 武汉华星光电半导体显示技术有限公司 | Flexible array substrate and manufacturing method thereof |
| CN112701127A (en) * | 2019-10-23 | 2021-04-23 | 群创光电股份有限公司 | Electronic device |
| CN113433742B (en) * | 2021-06-17 | 2023-05-02 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of IPS type TFT-LCD array substrate and IPS type TFT-LCD array substrate |
| CN113433747B (en) * | 2021-07-12 | 2023-06-27 | 武汉华星光电技术有限公司 | Array substrate, manufacturing method and mobile terminal |
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| TW201418855A (en) | 2014-05-16 |
| CN103151304A (en) | 2013-06-12 |
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