CN106847835B - Display panel, preparation method of display panel and display device - Google Patents
Display panel, preparation method of display panel and display device Download PDFInfo
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- CN106847835B CN106847835B CN201710212674.1A CN201710212674A CN106847835B CN 106847835 B CN106847835 B CN 106847835B CN 201710212674 A CN201710212674 A CN 201710212674A CN 106847835 B CN106847835 B CN 106847835B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910052793 cadmium Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052725 zinc Inorganic materials 0.000 claims description 7
- 229910001849 group 12 element Inorganic materials 0.000 claims description 6
- 229910021472 group 8 element Inorganic materials 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- 229910052753 mercury Inorganic materials 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052711 selenium Inorganic materials 0.000 claims description 6
- 229910052717 sulfur Inorganic materials 0.000 claims description 6
- 229910052714 tellurium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 229910052716 thallium Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 239000003574 free electron Substances 0.000 abstract description 4
- 230000001443 photoexcitation Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 15
- 239000000370 acceptor Substances 0.000 description 9
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The application belongs to the technical field of display, and particularly relates to a display panel, a preparation method of the display panel and a display device. The display panel comprises a thin film transistor, wherein the thin film transistor comprises a semiconductor layer, and the semiconductor layer comprises a channel region, a light doped region and a heavy doped region; the lightly doped region is located between the channel region and the heavily doped region, and is doped with an element for forming a deep energy level. The thin film transistor is doped with elements for forming deep energy levels in a lightly doped region, the elements can play a role of a donor and an acceptor and can be ionized for multiple times to form multiple energy levels; after the deep energy levels are generated by doping, electron-hole pairs generated by photoexcitation can be recombined through the deep energy levels, free electrons/holes which can participate in conduction are reduced, and therefore off-state leakage current of the TFT can be reduced.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel, a preparation method of the display panel and a display device.
Background
Display panels include Liquid Crystal Display (LCD) panels, Organic Light Emitting Diode (OLED) panels, and the like.
For example, fig. 1 is a schematic structural diagram of a conventional liquid crystal display panel, and as shown in fig. 1, the liquid crystal display panel includes a lower substrate 100 and an upper substrate 200. A color filter (not shown) is generally disposed on the upper substrate 200, a thin film transistor is integrated on the lower substrate 100, and a liquid crystal layer 400 is interposed between the upper substrate 200 and the lower substrate 100, and the liquid crystal layer 400 is formed of a corresponding liquid crystal material according to a display mode of the liquid crystal display panel. The upper and lower substrates 200 and 100 have upper and lower polarizers 300 and 300' attached to sides thereof facing away from the liquid crystal layer 400, respectively. The lower substrate 100 includes a plurality of sub-pixel units defined by a plurality of data lines and a plurality of gate lines, the plurality of sub-pixel units are distributed in a matrix, each sub-pixel unit includes a pixel electrode and a Thin Film Transistor (TFT), a source of the TFT is connected to the data line, a drain of the TFT is connected to the pixel electrode, a gate of the TFT is connected to the gate line, the gate line is connected to a gate driving circuit, the gate driving circuit controls the Thin Film Transistor to be turned on and off through the gate line, and when the Thin Film Transistor is turned on, the data line provides a data voltage to the corresponding pixel electrode through the Thin Film Transistor to charge the pixel electrode. The thin film transistor includes a semiconductor layer, a gate electrode, and source/drain electrodes. The semiconductor layer includes source/drain regions and a channel region between the source/drain regions, and may be formed of low temperature polysilicon or amorphous silicon. Low temperature polysilicon is typically used because it has a higher electron mobility than amorphous silicon. However, the low-temperature polysilicon TFT has a higher off-state leakage current (off-current) than the amorphous silicon TFT, and the low-temperature polysilicon TFT is likely to generate a photogenerated carrier after light irradiation, thereby generating a leakage current. In the practical manufacturing of the low-temperature polysilicon TFT, a metal light blocking layer is adopted to block backlight from irradiating the TFT, and even if the backlight is turned on, the leakage current of the TFT still has a great increase.
In view of this, the present application is specifically made.
Disclosure of Invention
The present application provides a display panel.
The second invention of the present application is directed to a method for manufacturing the display panel.
A third object of the present application is to provide a display device including the display panel.
In order to accomplish the purpose of the application, the technical scheme is as follows:
the present application relates to a display panel including a thin film transistor including a semiconductor layer including a channel region, a lightly doped region, and a heavily doped region;
the lightly doped region is positioned between the channel region and the heavily doped region;
the lightly doped region is doped with an element for forming a deep energy level.
Preferably, the lightly doped region is doped with phosphorus.
Preferably, the element for forming the deep energy level is at least one selected from the group consisting of group ib elements, group iib elements, group via elements, group viib elements, group viii elements, group iia elements, and group iiia elements.
Preferably, the IB group elements are selected from at least one of Cu, Ag and Au; the group IIB element is selected from at least one of Zn, Cd and Hg; the VIA group element is selected from at least one of S, Te, Se and O; the VIIB group element is selected from Mn; the VIII group element is selected from at least one of Fe, Co and Ni; the group IIA element is selected from at least one of Mg and Be; the IIIA group element is selected from at least one of In and Tl.
Preferably, the element for forming the deep level is selected from at least one of Cu, Ag, and Au.
Preferably, the doping amount of the element for forming the deep energy level is 10 per cubic centimeter12～1014And (4) atoms.
Preferably, the width of the lightly doped region is 1.0-2.0 μm.
Preferably, the thin film transistor is a low-temperature polycrystalline silicon thin film transistor.
Preferably, the thin film transistor includes a light-shielding layer, a gate insulating layer is disposed on one side of the semiconductor layer, and the light-shielding layer is disposed on the other side of the semiconductor layer; the shading layer covers the channel region in the orthographic projection of the semiconductor layer.
The application relates to a display device, comprising the display panel of the application.
The present application relates to a method of manufacturing a display panel comprising thin film transistors, the preparation of the thin film transistors comprising at least the steps of: forming a lightly doped region; and doping elements for forming a deep energy level in the lightly doped region.
Preferably, the forming of the lightly doped region includes:
a semiconductor layer is formed on the substrate,
forming a first photoresist pattern on the semiconductor layer, then doping phosphorus, forming a heavily doped region in a region which is not covered by the first photoresist pattern, and forming an undoped region in a region which is covered by the first photoresist pattern;
stripping the first photoresist pattern to form a gate insulating layer on the semiconductor layer;
forming a gate metal layer on the gate insulating layer;
forming a second photoresist pattern on the gate metal layer, wherein a projection region of the second photoresist pattern is located in a projection region of the undoped region along a direction in which the second photoresist pattern points to the undoped region, and the area of the second photoresist pattern is smaller than that of the undoped region;
and etching the grid metal layer and the grid insulating layer which are not covered by the second photoresist pattern, then carrying out phosphorus doping, forming a channel region by the undoped region covered by the grid insulating layer, and forming a lightly doped region by the undoped region which is not covered by the grid insulating layer.
Preferably, the element for forming the deep energy level is at least one selected from the group consisting of group ib elements, group iib elements, group via elements, group viib elements, group viii elements, group iia elements, and group iiia elements.
Preferably, the IB group elements are selected from at least one of Cu, Ag and Au; the group IIB element is selected from at least one of Zn, Cd and Hg; the VIA group element is selected from at least one of S, Te, Se and O; the VIIB group element is selected from Mn; the VIII group element is selected from at least one of Fe, Co and Ni; the group IIA element is selected from at least one of Mg and Be; the IIIA group element is selected from at least one of In and Tl.
The technical scheme of the application has at least the following beneficial effects:
the method comprises the steps of doping elements for forming a deep energy level (deep-state) in a lightly doped region of a thin film transistor, wherein the elements can play a donor role and an acceptor role and can be ionized for multiple times to form multiple energy levels; after the deep energy levels are generated by doping, electron-hole pairs generated by photoexcitation can be recombined through the deep energy levels, and free electrons/holes which can participate in conduction are reduced, so that off-state leakage current (off current) of the TFT can be reduced.
Drawings
FIG. 1 is a schematic structural diagram of a conventional LCD panel;
fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;
FIG. 3 is an energy band diagram of Si element;
fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present application;
fig. 5 is a flowchart of a process for manufacturing a thin film transistor according to an embodiment of the present disclosure.
Detailed Description
The present application relates to a display panel, the display panel includes a Thin-film transistor 1 (TFT for short), fig. 2 is a schematic structural diagram of the Thin-film transistor 1 provided in this application (the Thin-film transistor 1 is shown in a dashed-line frame in the figure), the Thin-film transistor 1 includes a semiconductor layer 10, a gate electrode 23, a source electrode 24 and a drain electrode 25, the source electrode 24 is connected to a data line (not shown in the figure), the drain electrode 25 is connected to a pixel electrode 26, and the gate electrode 23 is used for being connected to a gate line (not shown in the figure); the semiconductor layer 10 includes a channel region 101, a lightly doped region 102, and a heavily doped region 103; lightly doped region 102 is located between channel region 101 and heavily doped region 103.
Forming the lightly doped region 102 between the source/drain region and the channel region 101 region of the polysilicon TFT can reduce off-state leakage current thereof. The lightly doped region 102 can reduce the leakage current of the LTPS-TFT by one to two orders of magnitude, however, the TFT photogenerated leakage current also mainly occurs in the LDD region, the lightly doped region 102 generates light to generate carriers after being irradiated by light, and under the action of a strong field in the lightly doped region 102, electron/hole pairs are pulled to different directions, so that the leakage current can be detected. In the present application, the lightly doped region 102 is doped with an element for forming a deep energy level. After deep energy levels (deep-state) are generated in the lightly doped region 102 through doping, electron-hole pairs generated by light excitation can be recombined through the deep energy levels (deep-state), so that free electrons/holes which can participate in electric conduction are reduced, and the leakage current of the thin film transistor 1 can be reduced.
The element for forming the deep level in the present application refers to an element that enables electrons of the Si element in the lightly doped region 102 to form a deep level (deep-state) close to the intrinsic level (Ei). The elements used to form the deep level are also called deep level impurities, the deep level impurities are positioned near the center of the forbidden band, the ionization energy is larger, the donor level is far away from the bottom of the conduction band, and the acceptor level is far away from the top of the valence band. At room temperature, impurities at these impurity levels generally do not ionize and do not contribute to the carriers of the semiconductor material, but they can act as recombination centers for electrons or holes, affecting the lifetime of the non-equilibrium minority carriers. Deep level impurities may function as donors and also as acceptors; multiple ionization can be produced to form multiple energy levels. The energy band diagram of Si element is shown in FIG. 3, as shown in FIG. 3, Ev is called valence band top, Ec is called conduction band bottom, deep energy level (deep-state) is close to intrinsic energy level (Ei), e-Represents an electron, h + represents a hole; as shown by the left ellipse in the figure, electron/hole pairs are generated upon optical excitation; as shown in the right side of the figure, when a deep level (deep-state) is generated, electron/hole pairs may recombine via the deep level (deep-state), thereby reducing free electrons/holes that may participate in conduction.
The deep level impurity has the following basic characteristics: firstly, ionization is not easy, and the influence on the carrier concentration is not great; secondly, multiple energy levels are generally generated, even a donor level and an acceptor level are generated; thirdly, the material can play a role of a recombination center, so that the service life of minority carriers is reduced; fourthly, the ionized deep-level impurities are taken as a charge center, and the charge center plays a scattering role on the current carrier, so that the mobility of the current carrier is reduced, and the conductivity is reduced.
The lightly doped region 102 is doped with phosphorus in an amount of 10 per cubic centimeter17～1018And a phosphorus atom.
As an improvement of the display panel of the present application, the element for forming the deep energy level is at least one selected from the group consisting of group IB elements, group IIB elements, group VIA elements, group VIIB elements, group VIII elements, group IIA elements, and group IIIA elements.
Specifically, the IB group element is selected from at least one of Cu, Ag and Au; in which Au is an substitutional impurity (forming a donor type deep level Au [ EV +0.35eV ]]And an acceptor type deep energy level Au ([ Ec-0.54 eV)]Other energy levels may also be too deep (into the energy band) to be detected); the charge state of Au atoms in a semiconductor is related to the type and doping concentration of the semiconductor, i.e., Au is easily obtained as electrons in an n-type semiconductor-In p-type semiconductors, electrons are easily lost and Au is formed+. Cu forms 3 acceptor type deep levels and Ag forms one acceptor type deep level.
The group IIB element is at least one of Zn, Cd and Hg; both Zn and Cd are substitutional impurities (each forming 2 acceptor levels), and Hg also forms 2 donor levels.
The VIA group element is selected from at least one of S, Te, Se and O; s is a substitutional impurity (forming 3 donor levels) and Te is a substitutional impurity (forming 2 donor levels).
The VII B group element is selected from Mn; mn is a substitutional impurity (forming a donor level);
the VIII group element is selected from at least one of Fe, Co and Ni; fe is a substitutional impurity (forming a donor level). Co and Ni are substitutional impurities (each forming 2 acceptor levels).
As an improvement of the display panel of the present application, the element for forming the deep level is selected from at least one of Cu, Ag and Au. The elements of Cu, Ag and Au are adopted, so that the forming efficiency of the deep energy level is higher.
As an improvement of the display panel, the doping amount of the element for forming the deep energy level is 10 per cubic centimeter12～1014And (4) atoms. If the amount of doping is too small, deep level formation may resultThe effect of reducing leakage current cannot be achieved; if the doping amount is too large, the resistance in the lightly doped region is lowered too much, and the characteristics of the thin film transistor are deteriorated.
As an improvement of the display panel of the present application, the heavily doped region 103, the lightly doped region 102 and the channel region 101 are sequentially disposed along a first direction (w-w' direction), and the width of the lightly doped region 102 in the first direction is 1.0 to 2.0 μm. If the lightly doped region 102 is too long, its resistance will be greater; since there may be some variations in the fabrication of the thin film transistor 1, selecting a width greater than 1 μm may affect its function of reducing off-state leakage current if the width is further reduced.
As an improvement of the display panel of the present application, the thin film transistor 1 is a low-temperature polysilicon thin-film transistor (LTPS-TFT). The physical and electrical characteristics of the low-temperature polycrystalline silicon thin film transistor are more excellent than those of an a-Si TFT, the low-temperature polycrystalline silicon thin film transistor has higher integration level, the integration of a driving circuit and even the integration of a computer system can be realized, a large number of external elements are reduced, the performance of the device is greatly improved, the low-temperature polycrystalline silicon thin film transistor is more reliable, and the cost of the device is lower.
As a modification of the display panel of the present application, as shown in fig. 2, the thin film transistor 1 includes a light shielding layer 27, a gate insulating layer 21 is disposed on one side of the semiconductor layer 10, and the light shielding layer 27 is disposed on the other side of the semiconductor layer 10; the light-shielding layer 27 covers the channel region 101 in an orthogonal projection of the semiconductor layer 10. The light-shielding layer 27 serves to block light from entering the channel region 101, and has an area equal to or larger than that of the channel region 101. The light shielding layer 27 may be made of a material having a good light shielding property, such as metal.
As shown in fig. 4, an embodiment of the present invention further provides a display device, including the display panel. The specific structure and principle of the display panel 500 are the same as those of the above embodiments, and are not described herein again. The display device may be any electronic device with a liquid crystal display function, such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.
The application also relates to a manufacturing method of the display panel, the display panel comprises a thin film transistor 1, and the preparation of the thin film transistor 1 at least comprises the following steps:
forming a lightly doped region 102;
the lightly doped region 102 is doped with an element for forming a deep energy level.
The process of forming the lightly doped region 102 includes:
a semiconductor layer 10 is formed and,
forming a first photoresist 30 pattern on the semiconductor layer 10, and then performing phosphorus doping, wherein a heavily doped region 103 is formed in a region not covered by the first photoresist 30 pattern, and a non-doped region 20 is formed in a region covered by the first photoresist 30 pattern;
stripping the first photoresist 30 pattern to form a gate insulating layer 21 on the semiconductor layer 10;
forming a gate metal layer 22 on the gate insulating layer 21;
forming a second photoresist 40 pattern on the gate metal layer 22, wherein a projection region of the second photoresist 40 pattern is located in a projection region of the undoped region 20 along a direction in which the second photoresist 40 pattern points to the undoped region 20, and an area of the second photoresist 40 pattern is smaller than an area of the undoped region 20;
the gate metal layer 22 and the gate insulating layer 21, which are not covered by the second photoresist 40 pattern, are etched and then phosphorus doping is performed, the undoped region 20 covered by the gate insulating layer 21 forms the channel region 101, and the undoped region 20 not covered by the gate insulating layer 21 forms the lightly doped region 102.
As an improvement of the manufacturing method of the present application, the element for forming the deep energy level is at least one selected from the group consisting of group IB elements, group IIB elements, group VIA elements, group VIIB elements, group VIII elements, group IIA elements, and group IIIA elements.
As an improvement of the manufacturing method, the IB group element is at least one selected from Cu, Ag and Au; the group IIB element is at least one of Zn, Cd and Hg; the VIA group element is selected from at least one of S, Te, Se and O; the VII B group element is selected from Mn; the VIII group element is selected from at least one of Fe, Co and Ni; at least one IIIA group element selected from Mg and Be is selected from In and Tl.
The method for manufacturing the thin film transistor in the display panel according to the embodiment of the application has a flow chart of a manufacturing process as shown in fig. 5, specifically comprising the following steps:
1. depositing to form a semiconductor layer 10;
2. a first photoresist 30 is patterned on the semiconductor layer 10 and then highly doped with phosphorus in an amount of more than 10 per cubic centimeter19An atom; the region not covered by the first photoresist 30 pattern is doped with high dose phosphorus to form a heavily doped region 103, and the region not covered by the first photoresist 30 pattern is undoped with elements to form an undoped region 20 for the subsequent formation of a lightly doped region 102 and a channel region 101;
3. stripping the first photoresist 30 pattern, forming a gate insulating layer 21 on the semiconductor layer 10, and forming a gate metal layer 22 on the gate insulating layer 21;
4. forming a second photoresist 40 pattern on the gate metal layer 22, wherein a projection region of the second photoresist 40 pattern is located in a projection region of the undoped region 20 along a direction in which the second photoresist 40 pattern points to the undoped region 20, and an area of the second photoresist 40 pattern is smaller than an area of the undoped region 20; that is, the region corresponding to the second photoresist 40 is used to form the channel region 101, and the undoped region 20 not covered by the second photoresist 40 is used to form the lightly doped region 102; etching the gate metal layer 22 and the gate insulating layer 21 which are not covered by the second photoresist 40 pattern, wherein the gate metal layer 22 is etched to form a gate 23;
5. carrying out low-concentration phosphorus doping with the doping amount of 10 per cubic centimeter17～1018A phosphorus atom; the undoped region 20 covered by the gate insulating layer 21 forms a channel region 101; the undoped region 20 not covered by the gate insulating layer 21 forms a lightly doped region 102;
6. the lightly doped region 102 is continuously doped with an element for forming a deep energy level to obtain a thin film transistor of the present application, and the thin film transistor is continuously assembled to obtain a display panel for off-state leakage current (off current) detection.
The thin film transistors 1# to 12# and the thin film transistor D1# were fabricated according to the above method, and the doping elements and the doping amounts in the lightly doped region of the thin film transistor are shown in table 1. Note that, the thin film transistors 1# to 12# in tables 1 and 2 have almost the same physical parameters (such as channel region aspect ratio, lightly doped region area, and the like) except for different doped deep level elements and contents, where the channel region aspect ratio is 20: 5.
Table 1:
| numbering | Deep level element species | Amount of impurities blended |
| Thin film transistor 1# | Cu | 1012Atom/cm3 |
| Thin film transistor 2# | Cu | 1013Atom/cm3 |
| Thin film transistor 3# | Cu | 1014Atom/cm3 |
| Thin film transistor 4# | Ag | 1013Atom/cm3 |
| Thin film transistor 5# | Au | 1013Atom/cm3 |
| Thin film transistor 6# | S | 1013Atom/cm3 |
| Thin film transistor 7# | Mn | 1013Atom/cm3 |
| Thin film transistor 8# | Fe | 1013Atom/cm3 |
| Thin film transistor 9# | Mg | 1013Atom/cm3 |
| Thin film transistor 10# | In | 1013Atom/cm3 |
| Thin film transistor 11# | Cu | 1011Atom/cm3 |
| Thin film transistor 12# | Cu | 1015Atom/cm3 |
| Thin film transistor D1# | — | — |
Wherein "-" means that any deep level element is not doped.
The results of the tests obtained are shown in table 2:
table 2:
according to the above experiment, the leakage current of the thin film transistor is greatly reduced compared with the comparative example by doping the corresponding element in the lightly doped region, so that the leakage current of the thin film transistor can be further reduced by doping the element for forming the Si element into the deep energy level in the lightly doped region.
According to experimental data of the thin film transistor with the number D1#, the thin film transistors 1# -12 # doped with the deep level elements can obviously reduce the leakage current of the thin film transistors.
As can be seen from experimental data of the thin film transistors numbered 1# -3 #, when Cu doping is adopted, the doping amount is 10 per cubic centimeter12、1013、1014When the atoms are contained, the leakage current of the thin film transistor can be obviously reduced. As can be seen from experimental data of the thin film transistor numbered 11#, if the doping amount of the element for forming the deep level is too small, the formation of the deep level is insufficient, and the effect of reducing the leakage current of the thin film transistor is poor; as is clear from experimental data of the thin film transistor numbered 12#, if the doping amount of the element for forming the deep level is too high, the effect of reducing the drain current of the thin film transistor is also poor.
Although the present application has been described with reference to preferred embodiments, it is not intended to limit the scope of the claims, and many possible variations and modifications may be made by one skilled in the art without departing from the spirit of the application.
Claims (13)
1. A display panel includes a thin film transistor including a semiconductor layer including a channel region, a lightly doped region, and a heavily doped region;
the lightly doped region is positioned between the channel region and the heavily doped region; it is characterized in that the preparation method is characterized in that,
the lightly doped region is doped with elements for forming a deep energy level;
the doping amount of the element for forming the deep energy level is 10 per cubic centimeter12～1014And (4) atoms.
2. The display panel according to claim 1, wherein the lightly doped region is doped with phosphorus.
3. The display panel of claim 1, wherein the element for forming the deep energy level is at least one element selected from the group consisting of group ib elements, group iib elements, group via elements, group viib elements, group viii elements, group iia elements, and group iiia elements.
4. The display panel according to claim 3,
the IB group elements are selected from at least one of Cu, Ag and Au;
the group IIB element is selected from at least one of Zn, Cd and Hg;
the VIA group element is selected from at least one of S, Te, Se and O;
the VIIB group element is selected from Mn;
the VIII group element is selected from at least one of Fe, Co and Ni;
the group IIA element is selected from at least one of Mg and Be;
the IIIA group element is selected from at least one of In and Tl.
5. The display panel according to claim 3, wherein the element for forming the deep level is at least one selected from Cu, Ag, and Au.
6. The display panel of claim 1, wherein the lightly doped region has a width of 1.0-2.0 μm.
7. The display panel according to any one of claims 1 to 6, wherein the thin film transistor is a low temperature polysilicon thin film transistor.
8. The display panel according to any one of claims 1 to 6, wherein the thin film transistor includes a light-shielding layer;
a grid electrode insulating layer is arranged on one side of the semiconductor layer, and the shading layer is arranged on the other side of the semiconductor layer;
the shading layer covers the channel region in the orthographic projection of the semiconductor layer.
9. A display device comprising the display panel according to any one of claims 1 to 8.
10. A method of manufacturing a display panel comprising thin film transistors, the preparation of the thin film transistors comprising at least the steps of:
forming a lightly doped region;
doping the lightly doped region with an element for forming a deep energy level; the doping amount of the element for forming the deep energy level is 10 per cubic centimeter12～1014And (4) atoms.
11. The method of claim 10, wherein the forming the lightly doped region comprises:
a semiconductor layer is formed on the substrate,
forming a first photoresist pattern on the semiconductor layer, then doping phosphorus, forming a heavily doped region in a region which is not covered by the first photoresist pattern, and forming an undoped region in a region which is covered by the first photoresist pattern;
stripping the first photoresist pattern to form a gate insulating layer on the semiconductor layer;
forming a gate metal layer on the gate insulating layer;
forming a second photoresist pattern on the gate metal layer, wherein a projection region of the second photoresist pattern is located in a projection region of the undoped region along a direction in which the second photoresist pattern points to the undoped region, and the area of the second photoresist pattern is smaller than that of the undoped region;
and etching the grid metal layer and the grid insulating layer which are not covered by the second photoresist pattern, then carrying out phosphorus doping, forming a channel region by the undoped region covered by the grid insulating layer, and forming a lightly doped region by the undoped region which is not covered by the grid insulating layer.
12. The method of claim 10, wherein the element for forming the deep energy level is selected from at least one of group ib elements, group iib elements, group via elements, group viib elements, group viii elements, group iia elements, and group iiia elements.
13. The method of claim 12,
the IB group elements are selected from at least one of Cu, Ag and Au;
the group IIB element is selected from at least one of Zn, Cd and Hg;
the VIA group element is selected from at least one of S, Te, Se and O;
the VIIB group element is selected from Mn;
the VIII group element is selected from at least one of Fe, Co and Ni;
the group IIA element is selected from at least one of Mg and Be;
the IIIA group element is selected from at least one of In and Tl.
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