JPS61199665A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPS61199665A JPS61199665A JP3877385A JP3877385A JPS61199665A JP S61199665 A JPS61199665 A JP S61199665A JP 3877385 A JP3877385 A JP 3877385A JP 3877385 A JP3877385 A JP 3877385A JP S61199665 A JPS61199665 A JP S61199665A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- grow
- film
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 20
- 239000000969 carrier Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000010931 gold Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010453 quartz Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000003949 trap density measurement Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- -1 Phospho Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は薄膜半導体装置に係り、特に液晶を表示に用い
るディスプレイに好適な薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film semiconductor device, and particularly to a thin film transistor suitable for a display using liquid crystal for display.
近年、液晶を表示に用いるディスプレイなどでは、各画
素の液晶を駆動するために、各画素ごとに薄膜トランジ
スタ（Ｔｈ１ｎ ｐｉｌｍ Ｔｒａｎｓｉｓｔｏｒ略し
てＴＰＴ ）を形成するアクティブマトリクス方式が用
いられている。第２図に示すように、このＴＰＴは、普
通、石英基板かガラス基板１上に成長した多結晶シリコ
ン（Ｐｏ１ｙｃｒｙｓｔｏｌｌｉｎｅ３ｉ１ｉｃｏｎ
略してｐｏｌｙ−８ｉｌか非晶質シリコン（７ｖｎｏｒ
ｐｈｏｕｓ ５ｉｌｉｃｏｎ略してａ−３ｉ）９忙形成
される。ｐｏｌｙ−３ｉ を用いて通常のエンハンスメ
ント（［ｎｈａｎｃｅｍｅｎｔ ）型のＭＯ８（Ｍｅｔ
ｅｌＯｘｙｓｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ）
トランジスタを作ると、ソース、ドレイン両領域２．４
間の漏れ電流が大きい。このため、チャネルが形成され
る領域３はｐ型、ｎ型いずれの場合も不純物をドープし
ない真性ｔ ）ｎｔｒｉｎｓｉｃ略してｉ）半導体を使
用する。トランジスタを作動するときは、酸化膜５を介
してゲート電極６に電圧を印加してｉ領域３にチャネル
を形成する。尚、７は酸化膜である。In recent years, in displays using liquid crystal for display, an active matrix method is used in which a thin film transistor (TPT) is formed for each pixel in order to drive the liquid crystal of each pixel. As shown in FIG. 2, this TPT is usually made of polycrystalline silicon grown on a quartz or glass substrate 1.
Abbreviated as poly-8il or amorphous silicon (7vnor)
phous 5iliconabbreviated a-3i)9. Using poly-3i, the usual enhancement type MO8 (Met
elOxyside Sem1conductor)
When making a transistor, both the source and drain regions are 2.4
The leakage current between the two is large. For this reason, the region 3 in which the channel is formed uses an intrinsic semiconductor which is not doped with impurities, whether p-type or n-type. When the transistor is operated, a voltage is applied to the gate electrode 6 through the oxide film 5 to form a channel in the i-region 3. Note that 7 is an oxide film.
ＴＰＴを停止するときは、ｐｎ接合の電位障壁でなく、
ｉ層の高抵抗領域を利用する方法がとられている。しか
しながら、この方向もまだ十分とはいえない。一般に、
ｐｏｌｙ−３ｉのキャリアの移動度は１〜１０ｍ／ＶＳ
と単結晶の場合に比べて２桁以上小さく、また、ｉ層の
抵抗率は半絶縁体と考えるほど大きくけなめ。このため
、ＴＰＴを作動したときの電流、■、、ｃ主としてキャ
リアの移動度に関係する）が十分でなく、ＴＰＴを停止
したときの電流、ＬｔｔＣ主としてｉ層の抵抗率に関係
する）が小さくならない。このため両者の化工、。／Ｌ
ｔｔ が十分大きくとれず、液晶を用いた表示が鮮明
でないという問題がやった。When stopping TPT, do not use the potential barrier of the pn junction,
A method has been adopted that utilizes the high resistance region of the i-layer. However, this direction is still not sufficient. in general,
The carrier mobility of poly-3i is 1-10m/VS
This is more than two orders of magnitude smaller than that of a single crystal, and the resistivity of the i-layer is so large that it can be considered a semi-insulator. For this reason, the current when the TPT is activated (■, , c, which is mainly related to the carrier mobility) is not sufficient, and the current when the TPT is stopped, LttC (which is mainly related to the resistivity of the i-layer), is small. No. For this reason, both chemicals and engineering. /L
The problem was that tt was not large enough, and the display using liquid crystal was not clear.
ａ−８ｉを用いたＴＰＴの場合、漏れ電流はｐｏｌｙ−
８ｉの場合より小さいが、キャリア移動度が１ｃＩＩＩ
／ｖＳ以下とさらに小さ贋。このため、１、− ／ １
．ｔｔ はｐｏｌｙ−３ｉの場合より小さく、液晶を
用いた表示は一層不鮮明である（実開昭５７−５７５５
５号公報）。In the case of TPT using a-8i, the leakage current is
Although it is smaller than the case of 8i, the carrier mobility is 1cIII
An even smaller fake with /vS or less. Therefore, 1, - / 1
．． tt is smaller than that of poly-3i, and the display using liquid crystal is even more unclear (Utility Model Application Publication No. 57-5755).
Publication No. 5).
本発明の目的は、キャリアの移動度をそこなわずにＴＰ
Ｔの漏れ電流を減らし、１．、／Ｉ。ｆｆ を十分大き
くすることができるＴＰＴを提供することにある。The object of the present invention is to transfer TP without impairing carrier mobility.
Reduce T leakage current, 1. ,/I. The object of the present invention is to provide a TPT that can make ff sufficiently large.
本発明は、深いエネルギ単位を持ったキャリアのトラッ
プ層をキャリアの走行領域と分離したことを特徴とする
。The present invention is characterized in that the carrier trap layer having deep energy units is separated from the carrier travel region.
本発明は、特にｐｏｌｙ−３ｉの抵抗率とキャリアの移
動度が結晶粒径、結晶粒界におけるキャリアのトラップ
密度、結晶粒内のキャリアの濃度に密接に関連すること
を確認して成し遂げられた。The present invention was achieved by confirming that the resistivity and carrier mobility of poly-3i are closely related to the grain size, the carrier trap density at the grain boundaries, and the carrier concentration within the grains. .
本発明を具体的に述べれば次のようになる。The present invention will be specifically described as follows.
第１図に本発明の概略図を示す。尚、第１図において、
９は真性半導体領域であシ、第２図と同−物相当物には
同一符号を付けている。ゲートに電圧を印加してＴＰＴ
を作動させるときは、チャネル領域３とキャリアのトラ
ップ層８が分離隣接されているために１キヤリアはトラ
ップに妨害されることなく通常の移動度で移動する。ゲ
ート電圧をアースにおとしてＴ’ Ｆ Ｔを停止すると
きは、チャネル領域３のキャリアはその下にある深いエ
ネルギ単位に“トラップされ、ソース、ドレイン両領域
２．４間のキャリア濃度が小さくなる。これは、特にｐ
ｏｌｙ−８ｉの結晶粒は等方向な大きさでなく、ｐｏｌ
ｙ−８ｉ膜の成長方向（この場合、チャネルと垂直方向
）に長く、キャリアはこの方向に移動しやすいためであ
る。FIG. 1 shows a schematic diagram of the present invention. In addition, in Figure 1,
9 is an intrinsic semiconductor region, and the same reference numerals are given to the same parts as in FIG. 2. TPT by applying voltage to the gate
When the carrier is operated, one carrier moves with normal mobility without being hindered by the trap because the channel region 3 and the carrier trap layer 8 are separated and adjacent to each other. When the gate voltage is grounded to stop the T' F T, carriers in the channel region 3 are "trapped" in the deep energy unit below, and the carrier concentration between the source and drain regions 2.4 becomes small. .This is especially true for p
The crystal grains of oly-8i are not isodirectional in size and have pol
This is because the y-8i film is long in the growth direction (in this case, perpendicular to the channel), and carriers tend to move in this direction.
一般に、ＴＰＴの作動、停止時におけるソースドレイン
両領域２．４間の電流は、それぞれ、と表わされる。こ
こで、μはｐｏｌｙ−８ｉの移動度、ρはチャネル領域
の抵抗率、ｔはトランジスタの厚さ、Ｗ／Ｌはチャネル
の幅と長さの比、ｖｌはゲート電圧、ｖｔｋはしきい値
電圧、Ｃｏ１は酸化膜の容量である。Ｗ／Ｌは工□とＩ
ｅｔｔの個々の値に対するパラメータであるが％ Ｌ
ｍ ／ Ｉｅｔｔなる比はＷ／Ｌに依存しない。（１）
、 （２）式から、１．、／Ｉ。ｆｆなる比を大きぐす
るには、μρなる積を大きくしなければならないことが
わかる。一般に、ｐＯｌｙ−８ｉの成長温度を下げれば
、結晶粒径が小さくなり、トラップ密度が増加してρは
大きくなる。しかし、トラップ密度の増加は急激なμの
減少をもたらすために、１．、／Ｉ。ｆｆは減少する。Generally, the current between the source and drain regions 2.4 when the TPT is activated and deactivated is expressed as follows. Here, μ is the mobility of poly-8i, ρ is the resistivity of the channel region, t is the thickness of the transistor, W/L is the ratio of channel width to length, vl is the gate voltage, and vtk is the threshold value. The voltage Co1 is the capacitance of the oxide film. W/L is engineering□ and I
The parameter for each value of ett is %L
The ratio m/Iett is independent of W/L. (1)
, From equation (2), 1. ,/I. It can be seen that in order to increase the ratio ff, the product μρ must be increased. Generally, if the growth temperature of pOly-8i is lowered, the crystal grain size becomes smaller, the trap density increases, and ρ becomes larger. However, since an increase in trap density causes a rapid decrease in μ, 1. ,/I. ff decreases.
ｐｏｌｙ−８ｉの成長温度をさらに下げると、ａ−３ｉ
が形成される。この場合、ρ゛の増加、μの減少が起シ
、Ｉ−、／Ｌ−ｔｔは減少する。When the growth temperature of poly-8i is further lowered, a-3i
is formed. In this case, ρ' increases and μ decreases, so that I- and /L-tt decrease.
本発明は、チャネル領域３のすぐ下に深いエネルギ準位
を持つトラップ層８を設け、チャネル領域３とトラップ
層８を分離し、キャリア走行領域にトラップが存在しな
いようにしたことにより、キャリアの移動度をそこなわ
ずにチャネル領域３の抵抗率を大きくすることができる
。このため、（ｌ）、（２）式よりＴＰＴのＩ−／Ｌｔ
ｔが増加し、液晶などを用いたアクティブマトリクス方
式の表示を鮮明にすることができる。The present invention provides a trap layer 8 having a deep energy level immediately below the channel region 3, separates the channel region 3 and the trap layer 8, and prevents the existence of traps in the carrier travel region. The resistivity of the channel region 3 can be increased without impairing the mobility. Therefore, from equations (l) and (2), I-/Lt of TPT
t increases, and active matrix display using liquid crystal or the like can be made clearer.
以下、本発明の一実施例を説明する。第３図は本発明を
用いたＴＰＴ全体の断面構造を示す。基板ｌとして石英
を用いている。基板温度を５５０Ｃに保ち、分子線蒸着
（Ｍｏ１ｅｃｕｌａｒ ＢｅａｍＤｅｐｏｓ ｉ ｔ
ｉｏｎ略してＭＢＤ）法により厚さ１５００人のｐｏｌ
ｙ−８ｉのｉ領域９を成長させる。次に、伝導帯から約
０．５５ ｅ Ｖ下にアクセプタ準位を持っている金（
略してＡｕ）を約Ｉ Ｘ ｌ Ｏ”ｃｍ−３の濃度でド
ーピングしながら、約４００人のｐｏｌｙ−３ｉｉ成長
させ深いエネルギ準位を有するトラップ層９を形成する
。次に、ドーピングをしないｉ層ｐｏｌｙ−８ｉ金２０
ＯＡ成長してＴＦ”Ｔのソース、ドレイン、チャネル領
域２〜４を作る。基板温度を一定にしておいても、絶縁
膜上に成長したｐｏｌｙ−８ｉの結晶粒径は、初め小さ
く、かつ、ａ−Ｓｉ成分を含んでいる。膜厚が厚くなる
に従い、結晶粒径は徐々に大きくなる。約１０００人の
膜厚ではｐｏｌｙ−３ｉの結晶粒は平均直径約２００人
、長さ約４００人の内在状になる。本実施例で絶縁膜上
に成長した最初のｐｏｌｙ−ｆ３ｉｉ領域９はその上に
成長するトラップ層８およびソース、ドレイン、チャネ
ル領域２〜４のキャリアの移動度を大きくする効果があ
る。全体で約２１００人の厚さのｐｏｌｙ−８ｉ膜の成
長後、ＣＶＤ法によりＳｉｎｇ膜５を１０００人つけて
絶縁層を形成する。続いて、減圧ＣＶＤ法によりゲート
電極用ｐｏｌｙ−８ｉ６を１５００人つける。次に、リ
ン（略してＰ）ｋ５０ＫｅＶのエネルギ、５ Ｘ １０
”ｃｍ−２のドーズ量で打込んでソースとドＶイン領域
２，４を形成する。An embodiment of the present invention will be described below. FIG. 3 shows the cross-sectional structure of the entire TPT using the present invention. Quartz is used as the substrate l. The substrate temperature was maintained at 550C and molecular beam deposition was performed.
ion (abbreviated as MBD) method with a thickness of 1500 people.
Grow i-region 9 of y-8i. Next, gold (
A trap layer 9 having a deep energy level is formed by growing about 400 poly-3ii layers while doping Au (abbreviated as Au) at a concentration of about IXlO"cm-3. Next, a trap layer 9 having a deep energy level is formed. layer poly-8i gold 20
The source, drain, and channel regions 2 to 4 of TF''T are formed by OA growth. Even if the substrate temperature is kept constant, the crystal grain size of poly-8i grown on the insulating film is small at first, and Contains a-Si component.As the film thickness increases, the crystal grain size gradually increases.With a film thickness of about 1000, poly-3i crystal grains have an average diameter of about 200 and a length of about 400. In this example, the first poly-F3II region 9 grown on the insulating film increases the mobility of carriers in the trap layer 8 and the source, drain, and channel regions 2 to 4 grown thereon. After growing a poly-8i film with a total thickness of approximately 2,100 layers, a 1,000 layer Sing film 5 is deposited using the CVD method to form an insulating layer.Subsequently, a poly-8i film for the gate electrode is grown using a low pressure CVD method. Attach 1500 8i6. Next, phosphorus (abbreviated P) k50KeV energy, 5 X 10
The source and V-in regions 2 and 4 are formed by implanting at a dose of "cm-2."
続いて、Ｐ Ｓ Ｇ （Ｐｈｏｓｐｈｏ Ｓｉ １ｉｃ
ａｔｅ Ｇｌａｓｓ ）１１、Ａｔ電極１０、透明電極
であるＩＴＯ１２を蒸着する。ＩＴＯを蒸着したもう一
枚の石英基板との間にＴ Ｎ （Ｔｗｉｓｔｅｄ Ｎｅ
ｍａｔｉｃ ）型の液晶を封入して表示装置が完成する
。Subsequently, P S G (Phospho Si 1ic
ate Glass) 11, an At electrode 10, and a transparent electrode ITO 12 are deposited. Twisted Ne (Twisted Ne
matic) type liquid crystal is sealed to complete the display device.
本実施例のＴＰＴのチャネル幅、チャネル長はそれぞれ
２０μｍ、１０μｍである。このとき１、、／ｘ、ｔｔ
ノ値は５Ｘ１０’となり、従来の１×１０４以下の値に
比べ１桁以上大きくなるため、従来わ表示に比べ鮮明な
画像が得られる。The channel width and channel length of the TPT in this example are 20 μm and 10 μm, respectively. In this case, 1, , /x, tt
The value is 5×10′, which is more than an order of magnitude larger than the conventional value of 1×10 4 or less, so a clearer image can be obtained than in the conventional display.
第４図には他の一実施例を示す。ここでは、前実施例で
金をｐｏｌｙ−８ｉＫドーピングするかわシに、不純物
を用いないで単に基板温度をｓｓｏ’ｃから４００ｔｔ
で下げる。このようにすると、ｐｏｌｙ−８ｉのかわり
にトラップ密度が大きいａ −８ｉが形成されトラップ
層８となる。ａ−８ｉｔ−４００人成長させた後、再び
基板温度を５５０Ｃまで下げてｐｏｌｙ−８ｉを２００
人成長してソース。FIG. 4 shows another embodiment. Here, instead of doping gold with poly-8iK in the previous example, we simply raised the substrate temperature from sso'c to 400tt without using any impurities.
lower it. In this way, a-8i having a large trap density is formed instead of poly-8i, and becomes the trap layer 8. After growing 400 a-8i, lower the substrate temperature to 550C and grow 200 poly-8i.
People grow and source.
ドレイン、チャネル領域２〜４を形成する。以後のプロ
セスは前実施例と同じである。本実施例におけ；ｂ Ｔ
Ｆ Ｔ （ｉ層） Ｉ−／ Ｉ−ｔｔ すｂ値は２×
ｌＯ８となシ、液晶を用いた表示の画像は鮮明である。Drain and channel regions 2 to 4 are formed. The subsequent processes are the same as in the previous embodiment. In this example; b T
F T (i layer) I-/I-tt b value is 2×
As with lO8, images displayed using liquid crystal are clear.
第５図には本発明の一変形例を示す。絶縁基板ｌ上に半
導体層を成長させるとき、最初から深いエネルギ準位を
持つ約１８００人のトラップ層８を作す、ソの上にソー
ス、ドレイン、チャネル各領域２〜４のための約２００
人のｉ層を形成する。FIG. 5 shows a modified example of the present invention. When growing a semiconductor layer on an insulating substrate, a trap layer 8 of about 1,800 layers with deep energy levels is created from the beginning, and about 200 layers for each of the source, drain, and channel regions 2 to 4 are formed on top of the substrate.
Forms the i-layer of people.
トラップ単位として金をドーピングする方法を用いれば
第一番目の実施例と同じ効果が得られる。If a method of doping gold as a trap unit is used, the same effect as in the first embodiment can be obtained.
トラップ層８をａ−８ｉで形成すると、その上の１Ｎｐ
ｏｌｙ−８ｉの結晶粒径が十分大きくならない。When trap layer 8 is formed of a-8i, 1Np on it
The crystal grain size of oly-8i is not large enough.
このため、チャネル領域のキャリアの移動度が小さくな
り、Ｔ Ｆ Ｔ ＯＩ−ａ／ Ｉ−ｔｔ す７）値は１
ｘ １ ｏ’となる。上記実施例はどではないが従来
法と比較すると画像は鮮明である。Therefore, the mobility of carriers in the channel region decreases, and the T F T OI-a/I-tt7) value becomes 1.
x 1 o'. Although the above embodiment is not unique, the image is clearer when compared with the conventional method.
尚、本発明は、ソース、ドレイン、チャネル各領域等が
単結晶半導体、α−半導体で構成されている場合も同様
に適用できる。Note that the present invention can be similarly applied to cases where the source, drain, channel regions, etc. are made of a single crystal semiconductor or an α-semiconductor.
本発明によれば、薄膜トランジスタ（ＴＰＴ）の中ヤリ
アの移動度をそこなわずにその漏れ電流を減らし、トラ
ンジスタの作動、停止時における電流比Ｌ−／Ｌｔｔを
十分大きくしたＴＰＴを得ることができる。According to the present invention, it is possible to reduce the leakage current of a thin film transistor (TPT) without impairing the mobility of the internal transistor, and to obtain a TPT with a sufficiently large current ratio L-/Ltt when the transistor is activated or deactivated. .
第１図は本発明を説明するためのＴＰＴの概略図、第２
図は従来のＴＰＴの概略図、第３図は本発明の一実施例
を示す概略図、第４図は本発明の他の実施例を示す概略
図、第５図は本発明の変形例を示す概略図である。
１・・・基板、２・・・ソース（ｎ型）領域、３・・・
真性半導体領域（チャネル領域）、４・・・ドレインｃ
ｎ型）領域、５・・・酸化膜、６・・・ゲート電極、７
・・・酸化膜、訃・・トラップ層、９・・・真性半導体
領域、１ｏ・・・Ａｔ電極、ｌ １ ・Ｐ Ｓ Ｇ、
１２ ・！明ｔｆｆｌ（Ｉ’ｌ’０）。Fig. 1 is a schematic diagram of TPT for explaining the present invention, Fig. 2 is a schematic diagram of TPT for explaining the present invention;
The figure is a schematic diagram of a conventional TPT, Figure 3 is a schematic diagram showing one embodiment of the present invention, Figure 4 is a schematic diagram showing another embodiment of the present invention, and Figure 5 is a schematic diagram showing a modified example of the present invention. FIG. 1...Substrate, 2...Source (n type) region, 3...
Intrinsic semiconductor region (channel region), 4... drain c
n-type) region, 5... oxide film, 6... gate electrode, 7
... Oxide film, trap layer, 9... Intrinsic semiconductor region, 1o... At electrode, l 1 ・P S G,
12 ・! Clear tffl(I'l'0).
Claims (2)
域間に設けられ絶縁膜を介して設けられたゲート電極に
加えられる信号で上記両領域間でキャリアを走行させる
領域を有する薄膜半導体装置において、上記キャリアの
トラップ層をキャリアの走行領域に隣接して設けている
ことを特徴とする薄膜半導体装置。1. A thin film semiconductor device having a region in which source and drain electrodes are provided, and a region in which carriers are caused to travel between the two regions by a signal applied to a gate electrode provided between the two regions via an insulating film. A thin film semiconductor device characterized in that a trap layer is provided adjacent to a carrier travel region.
て設けていることを特徴とする薄膜半導体装置。2. The thin film semiconductor device according to item 1 above, wherein the trap layer is provided apart from the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3877385A JPS61199665A (en) | 1985-03-01 | 1985-03-01 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3877385A JPS61199665A (en) | 1985-03-01 | 1985-03-01 | Thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61199665A true JPS61199665A (en) | 1986-09-04 |
Family
ID=12534608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3877385A Pending JPS61199665A (en) | 1985-03-01 | 1985-03-01 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199665A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786955A (en) * | 1987-02-24 | 1988-11-22 | General Electric Company | Semiconductor device with source and drain depth extenders and a method of making the same |
| EP0588487A2 (en) * | 1992-08-19 | 1994-03-23 | AT&T Corp. | Method of making thin film transistors |
| CN106847835A (en) * | 2017-04-01 | 2017-06-13 | 厦门天马微电子有限公司 | The preparation method and display device of a kind of display panel, display panel |
-
1985
- 1985-03-01 JP JP3877385A patent/JPS61199665A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786955A (en) * | 1987-02-24 | 1988-11-22 | General Electric Company | Semiconductor device with source and drain depth extenders and a method of making the same |
| EP0588487A2 (en) * | 1992-08-19 | 1994-03-23 | AT&T Corp. | Method of making thin film transistors |
| EP0588487A3 (en) * | 1992-08-19 | 1994-09-28 | At & T Corp | Method of making thin film transistors |
| CN106847835A (en) * | 2017-04-01 | 2017-06-13 | 厦门天马微电子有限公司 | The preparation method and display device of a kind of display panel, display panel |
| CN106847835B (en) * | 2017-04-01 | 2019-12-27 | 厦门天马微电子有限公司 | Display panel, preparation method of display panel and display device |
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