JPH01120868A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPH01120868A JPH01120868A JP27833887A JP27833887A JPH01120868A JP H01120868 A JPH01120868 A JP H01120868A JP 27833887 A JP27833887 A JP 27833887A JP 27833887 A JP27833887 A JP 27833887A JP H01120868 A JPH01120868 A JP H01120868A
- Authority
- JP
- Japan
- Prior art keywords
- source
- drain
- layer
- tpt
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 229920005591 polysilicon Polymers 0.000 abstract description 18
- 239000011521 glass Substances 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 239000010408 film Substances 0.000 description 14
- 239000012535 impurity Substances 0.000 description 10
- 239000013078 crystal Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 Phospho Chemical class 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜半導体装置に係り、特に、液晶等を表示
に用いたアクティブマトリックス方式のデイスプレィに
用いて好適な薄膜半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film semiconductor device, and particularly to a thin film semiconductor device suitable for use in an active matrix type display using liquid crystal or the like for display.
一般に、液晶等を表示に用いるデイスプレィ装置は、各
画素の液晶を駆動するために、各画素毎に薄膜トランジ
スタ（Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ、以
下ＴＰＴという）を形成するアクティブマトリックス方
式を用いて構成されている。In general, display devices that use liquid crystal or the like for display are configured using an active matrix method in which a thin film transistor (hereinafter referred to as TPT) is formed for each pixel in order to drive the liquid crystal of each pixel.
以下、従来技術によるＴＰＴを図面により説明する。Hereinafter, TPT according to the prior art will be explained with reference to the drawings.
第２図及び第３図は従来技術によるＴＰＴの概略を示す
断面図であり、第２図、第３図において、■はガラス基
板、２はソース、３はドレイン、４はチャネル領域、６
はゲート絶縁膜、７はゲート電極、８はＰＳＧ膜、９は
ＡＡ電極、１０は高不純物濃度層である。2 and 3 are cross-sectional views schematically showing TPTs according to the prior art. In FIGS. 2 and 3, ■ is a glass substrate, 2 is a source, 3 is a drain, 4 is a channel region, and 6
7 is a gate insulating film, 7 is a gate electrode, 8 is a PSG film, 9 is an AA electrode, and 10 is a high impurity concentration layer.
第２図に示すＴＰＴは、ごく−膜内なＴＰＴの構造を示
すものであり、ガラス基板１上に成長させた多結晶シリ
コン（Ｐｏ１ｙｃｒｙｓｔａｌｌｉｎｅ Ｓ １ｌｉ
ｃＯｎ％以下ポリシリコンという）を活性層として使用
するため、ｎ−１−ｎ（あるいはｐ−１−ｐ）構造を有
する。すなわち、このＴＰＴは、ｎＳｉ域（あるいはｐ
領域）のソース２、不純物をドープしない真性半導体（
ｉｎｔｒｉｎｓｉｃ ｓｅｍｉｃｏｎｄｕｃｔｏｒ、以
下ｉという）層のチャネル領域４、ｎ領域（あるいはｐ
６ｉ域）のドレイン３がガラス基板１の上に形成され
、チャネル領域４の上層にゲート絶縁膜６を介してゲー
ト電極７が設けられ、ソース２及びドレイン３の上部に
Ａｌ電極９が設けられ、さらに、その他の部分がＰＳＧ
膜８に覆われて構成されている。The TPT shown in FIG.
Since cOn% or less polysilicon (referred to as polysilicon) is used as the active layer, it has an n-1-n (or p-1-p) structure. That is, this TPT is in the nSi region (or p
source 2 of the region), an intrinsic semiconductor (
Intrinsic semiconductor (hereinafter referred to as i) layer has a channel region 4, an n region (or p
6i region) is formed on a glass substrate 1, a gate electrode 7 is provided on the upper layer of the channel region 4 via a gate insulating film 6, and an Al electrode 9 is provided on the upper part of the source 2 and drain 3. , furthermore, other parts are PSG
It is covered with a membrane 8.
一般に、ＴＰＴをｎ−ｐ−ｎ（あるいはｐ−ｎ−ｐ）型
のエンハンスメントＭＯ３）ランジスタで構成すると、
このＴＰＴは、チャネル領域内に反転層を得るために必
要なゲート電圧が高くなり、しかも、ＴＰＴを動作させ
たときのオン電流が充分でないという問題点を有する。Generally, when the TPT is configured with an n-p-n (or p-n-p) type enhancement MO3) transistor,
This TPT has the problem that the gate voltage required to obtain an inversion layer in the channel region is high and, moreover, the on-current when the TPT is operated is insufficient.
このため、前記従来技術によるＴＰＴは、第２図に示す
ように、チャネル領域４として１層を使用して構成され
ている。このＴＰＴは、動作時、ソース２．ドレイン４
がｎ層であるｎチャネル構造の場合、ゲート電極７に正
電圧を印加して、チャネル領域４内に反転層というより
は、電子の蓄積層を形成させ、また、ｐチャネル構造の
場合、ゲート電極７に負電圧を印加して、チャネル領域
４内に、正孔の蓄積層を形成させ、この蓄積層を介して
充分なオン電流を流すことを可能としている。For this reason, the TPT according to the prior art is constructed using one layer as the channel region 4, as shown in FIG. In operation, this TPT is connected to source 2. drain 4
In the case of an n-channel structure, in which the gate electrode 7 is an n-layer, a positive voltage is applied to the gate electrode 7 to form an electron accumulation layer rather than an inversion layer in the channel region 4; A negative voltage is applied to the electrode 7 to form a hole accumulation layer in the channel region 4, making it possible to flow a sufficient on-current through this accumulation layer.
第３図に示すＴＰＴは、第２図に示すＴＰＴがガラス基
板１からポリシリコン層に拡散してくる不純物により、
リーク電流を生じ、オン電流を減少させるという欠点を
解決するものである。すなわち、このＴＰＴは、絶縁基
板上のシリコン（Ｓｉ１ｉｃｏｎ Ｏｎ Ｉ ｎ５ｕ
ｌａｔｏｒｘ略してＳｏ Ｉ）技術に関して、ガラス基
板１とポリシリコン層との界面領域にドープする不純物
濃度を高くすることによって、ガラス基板１の界面付近
に反転層を生じないようにして、リーク電流を低減して
いる。第３図に示す例では、ガラス基板１と、ソース２
．チャネル領域４．ドレイン５を作るポリシリコンとの
間に設けられているｐ＋層による高不純物濃度層が前述
した界面領域にドープされた高不純物濃度層である。そ
して、第３図に示すＴＰＴにおけるチャネル領域４は、
ソース２及びドレイン３の下層部に延びているが、ＴＰ
Ｔとしての動作は、第２図に示す場合と同様である。The TPT shown in FIG. 3 is different from the TPT shown in FIG. 2 due to impurities diffused from the glass substrate 1 into the polysilicon layer.
This solves the drawbacks of generating leakage current and reducing on-state current. That is, this TPT is made of silicon on an insulating substrate.
latorx (abbreviated as So I) technology, by increasing the impurity concentration doped in the interface region between the glass substrate 1 and the polysilicon layer, an inversion layer is not generated near the interface of the glass substrate 1, and leakage current is reduced. It is decreasing. In the example shown in FIG. 3, a glass substrate 1, a source 2
．． Channel region 4. The high impurity concentration layer formed by the p+ layer provided between the polysilicon forming the drain 5 is the high impurity concentration layer doped in the aforementioned interface region. The channel region 4 in the TPT shown in FIG.
Although it extends to the lower layer of the source 2 and drain 3, the TP
The operation as T is the same as that shown in FIG.
なお、この種ｎｉｎ構造のＴＰＴに関する従来技術とし
て、［日経エレクトロニクスＪ （１９８４，９，１
０、第２１１頁）に記載された技術が知られており、ま
たバック チャネル防止に関する従来技術として、「ア
イ イー イー イー トランザクション エレクトロ
ン デバイスＪＥＤ−２５，８６８（１９７Ｂ） （Ｉ
ＥＥＥ Ｔｒａｎｓ、 Ｅｌｅｃｔｒｏｎ Ｄｅｖｉ
ｃｅｓ Ｅ Ｄ ２５．８６Ｂ （１９７Ｂ） 〕
に記載された技術が知られている。In addition, as a conventional technology regarding this type of nin structure TPT, [Nikkei Electronics J (1984, September 1
0, p. 211) is known, and as a prior art related to back channel prevention, "I
EEE Trans, Electron Devi
ces E D 25.86B (197B)]
The technique described in is known.
しかし、前述の第２図に示す従来技術は、ソース２．ド
レイン３と、チャネル領域４とのｎ−１（あるいはｐ−
ｉ）接合におけるポテンシャル障壁が充分でないため、
リーク電流、特に、ゲート電極７に負電圧を印加した場
合のリーク電流が大きいという問題点がある。このリー
ク電流は、ドレイン接合における空乏層内で、結晶粒界
におけるトラップ準位を介して生じる電子−正孔対によ
ると考えられる。従って、ｎ−ｉ接合面を小さ（してリ
ーク電流を抑えることを目的として、ポリシリコン層を
薄くする方法も行われている。しかし、この方法による
ＴＰＴは、接合やチャネルを形成する領域におけるポリ
シリコンの結晶粒径が充分でなく、かつ、基板からポリ
シリコン層に拡散してくる不純物領域に、接合やチャネ
ル領域が入ってしまうため、リーク電流を充分に抑える
ことができず、かつ、オン電流も減少してしまうという
問題点を有する。However, in the prior art shown in FIG. 2 mentioned above, source 2. n-1 (or p-
i) Because the potential barrier at the junction is not sufficient,
There is a problem in that the leakage current, especially when a negative voltage is applied to the gate electrode 7, is large. This leakage current is thought to be caused by electron-hole pairs generated within the depletion layer at the drain junction via trap levels at crystal grain boundaries. Therefore, a method of thinning the polysilicon layer is also being used in order to reduce the n-i junction surface (to suppress leakage current). However, TPT using this method is The polysilicon crystal grain size is not sufficient, and the junction and channel region are included in the impurity region that diffuses from the substrate into the polysilicon layer, making it impossible to sufficiently suppress leakage current, and This has the problem that the on-state current also decreases.
また、第３図に示すＴＰＴは、ＴＰＴを構成するシリコ
ン層が単結晶か、それに準するような粒径の大きい多結
晶シリコン層である場合に目的とする効果を充分に奏す
ることができるが、結晶粒径の小さい多結晶シリコンの
場合には効果が少ないという問題点を有する。Furthermore, the TPT shown in FIG. 3 can sufficiently achieve the desired effect when the silicon layer constituting the TPT is a single crystal or a similar polycrystalline silicon layer with a large grain size. However, in the case of polycrystalline silicon with a small crystal grain size, there is a problem that the effect is small.
本発明の目的は、前述した従来技術の問題点を解決し、
ＴＰＴのオン電流をそこなうことなく、リーク電流を低
減させることのできる薄膜半導体装置を提供することに
ある。The purpose of the present invention is to solve the problems of the prior art described above,
An object of the present invention is to provide a thin film semiconductor device that can reduce leakage current without impairing the on-current of TPT.
本発明によれば、前記目的は、ソース及びドレインとな
る半導体領域の下に、ソース及びドレインとは逆の導電
型の半導体領域を備えることによって達成される。According to the present invention, the above object is achieved by providing a semiconductor region of a conductivity type opposite to that of the source and drain under the semiconductor region serving as the source and drain.
本発明の構成では、ＴＰＴを構成するポリシリコン層の
厚さを充分に厚くすることができるため、チャネル領域
の蓄積層が形成されるｉＮ上部のポリシリコン層の平均
粒径を充分大きくすることができ、かつ、基板ガラスか
らポリシリコン中に拡散してくる不純物の影響を受ける
ことが少なくなる。従って、ゲート電極に正電圧（ある
いは負電圧）を印加し、ＴＰＴをオンとさせた場合、本
発明のＴＰＴは、通常のｎ−１−ｎ（あるいはｐ−１−
ｐ）型の場合と同等のオン電流を得ることができる。一
方、ゲート電極に電圧を印加しないか、ＴＰＴをオフと
するような電圧を印加した場合、ｎ−１（あるいはｐ−
ｉ）接合は、ポリシリコンの平均粒径が大きく、かつ、
基板から拡散する不純物の影響の小さい領域にあるため
、特に、ドレイン接合において、トラップ準位を介して
のり一り電流、すなわち、オフ電流は低減される。また
、ｎ−１（あるいはｐ−ｉ）接合の面積が小さいため、
これもリーク電流をさらに低減させる効果を奏する０本
発明によるＴＰＴは、従来技術によるＴＰＴに比較して
、ｐ−ｎ接合領域が新たに生じることになるが、この接
合も、ｎ−ｉ、（あるいはｐ−ｉ）接合と同様に、結晶
粒径が充分に大きく、かつ、基板から拡散する不純物領
域の外にあり、この接合を介したリーク電流はきわめて
少ないものとなる。In the configuration of the present invention, since the thickness of the polysilicon layer constituting the TPT can be made sufficiently thick, the average grain size of the polysilicon layer above the iN where the accumulation layer of the channel region is formed can be made sufficiently large. In addition, it is less affected by impurities that diffuse into the polysilicon from the substrate glass. Therefore, when a positive voltage (or negative voltage) is applied to the gate electrode to turn on the TPT, the TPT of the present invention turns on the normal n-1-n (or p-1-
An on-state current equivalent to that of the p) type can be obtained. On the other hand, if no voltage is applied to the gate electrode or if a voltage is applied that turns off the TPT, n-1 (or p-
i) The bond has a large average grain size of polysilicon, and
Since the region is in a region where the influence of impurities diffused from the substrate is small, the current flowing through the trap level, that is, the off-state current, is reduced, particularly in the drain junction. Also, since the area of the n-1 (or p-i) junction is small,
This also has the effect of further reducing leakage current.In the TPT according to the present invention, a new p-n junction region is generated compared to the TPT according to the prior art, but this junction also has n-i, ( Alternatively, similar to the p-i junction, the crystal grain size is sufficiently large and located outside the impurity region diffused from the substrate, so that leakage current through this junction is extremely small.
以下、本発明による薄膜半導体装置の一実施例を図面に
より詳細に説明する。Hereinafter, one embodiment of a thin film semiconductor device according to the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例の構造を示す断面図、第４図
は本発明の一実施例によるＴＰＴのＶ−１曲線を示す図
である。第１図において、５はソース、ドレインと反対
導電型の半導体層、他の符号は、第２図、第３図により
説明したと同一である。FIG. 1 is a sectional view showing a structure of an embodiment of the present invention, and FIG. 4 is a diagram showing a V-1 curve of TPT according to an embodiment of the present invention. In FIG. 1, reference numeral 5 denotes a semiconductor layer of a conductivity type opposite to that of the source and drain, and the other symbols are the same as those explained in FIGS. 2 and 3.
第１図に示す本発明によるＴＰＴの一実施例は、第２図
により説明した従来技術によるＴＰＴのｎ領域（あるい
はｐ領域）のソース２及びｎ６１域（あるいはｐ ６Ｎ
域）のドレイン３の下層に、ソース２及びドレイン３を
構成する半導体領域とは逆の導電型の半導体領域である
ｐｌ！（あるいはｎ層）を設けて構成され、その他の部
分は、第２図の場合と同様に構成される。One embodiment of the TPT according to the present invention shown in FIG. 1 is similar to the source 2 and n61 regions (or p 6N
pl!, which is a semiconductor region of a conductivity type opposite to that of the semiconductor regions constituting the source 2 and drain 3, is located below the drain 3 of the region). (or n layers), and the other parts are constructed in the same manner as in the case of FIG.
次に、第１図に示す一実施例の製造方法をｎチャネルＴ
ＰＴを例として説明する。Next, the manufacturing method of one embodiment shown in FIG.
This will be explained using PT as an example.
（１）ガラス基板１として歪温度６４０”Ｃのガラス基
板を用意し、該基板１の上に、減圧ＣＶＤ法により、Ｈ
ｅで２０％に希釈したモノシランを用いて、５５０”Ｃ
，ＩＴｏｒｒの条件で、１層の多結晶シリコン膜を２ｓ
ｏｏＸの厚さに堆積させる。(1) A glass substrate with a strain temperature of 640"C is prepared as the glass substrate 1, and H
550"C using monosilane diluted to 20% with e.
, ITorr, one layer of polycrystalline silicon film was heated for 2s.
Deposit to a thickness of ooX.
（２）多結晶シリコン膜であるポリシリコン層をホトエ
ッチしてＴＦＴ部を構成するポリシリコン層を残した後
、ゲート絶縁膜６として、８．０！を常圧ＣＶＤ法によ
り３５００Ａ堆積させ、次に、減圧ＣＶＤ法によりゲー
ト電極７となるポリシリコン膜を２５００Ａ堆積させる
。(2) After photo-etching the polysilicon layer, which is a polycrystalline silicon film, and leaving the polysilicon layer constituting the TFT section, the gate insulating film 6 is formed using 8.0! 3500 Å of polysilicon film is deposited by normal pressure CVD method, and then 2500 Å of polysilicon film which will become the gate electrode 7 is deposited by low pressure CVD method.
（３）ホトエッチにより、ゲート絶縁膜６とゲート電極
７以外のＳ、０！とポリシリコン膜を除去し、ゲート電
極７上に望ましくは保護層（なお、この保護層は、ｎチ
ャネル形式のイオン打込時にはなくてもよい）を形成し
た後、ボロンを４０ＫｅＶのエネルギー、ｌ Ｘ Ｉ
Ｑ １Ｓｃ ｍ−”のドーズ量で打込み、第１図に示す
ソース２．ドレイン３及びこれらと反対導電型を有する
半導体領域５に相当する部分にｐ領域を形成し、さらに
、リンを２５Ｋ ｅ Ｖ（７）エネルギー、５ｘ １０
ＩＳｃｍ−”のドーズ量で打込み、ソース２及びドレイ
ン３となるｎ型の半導体領域を形成する。(3) By photoetching, S, 0! except for the gate insulating film 6 and the gate electrode 7! After removing the polysilicon film and forming a protective layer on the gate electrode 7 (this protective layer may not be necessary for n-channel ion implantation), boron is implanted at an energy of 40 KeV and l X I
A p-type region is formed in a portion corresponding to the source 2, drain 3 and the semiconductor region 5 having the opposite conductivity type as shown in FIG. (7) Energy, 5x 10
Implantation is performed at a dose of IScm-'' to form n-type semiconductor regions that will become the source 2 and drain 3.
（４） 常圧ＣＶＤ法により、４８０”ＣでＰＳＧ（
Ｐ ｈｏｓｐｈｏ Ｓ １ｌｉｃａｔｅ 、Ｇ １ａ
１１）を６０００Ａ堆積させ、その後、Ｎ！中、６００
”Ｃ，２０時間の条件で加熱処理し、イオン打込み層を
活性化させる。(4) PSG (
Phospho S 1licate, G 1a
11) was deposited at 6000A, and then N! Medium, 600
"C. Heat treatment is performed for 20 hours to activate the ion implantation layer.
（５） コンタクト用穴をホトエッチで形成後、Ａ２
を１００’Ｃで６０００Ａにスパッタし、／１をホトエ
ッチしてソース２及びドレイン３の電極となるアルミ電
極９を形成して、ＴＰＴを完成させる。(5) After forming contact holes by photoetching, A2
is sputtered to 6000 A at 100'C, and /1 is photo-etched to form aluminum electrodes 9 that will serve as source 2 and drain 3 electrodes, thereby completing the TPT.
（６）本発明によるＴＰＴは、デイスプレィ装置の各画
素の駆動用に用いられるので、その後、図示しない透明
電極であるＩＯＴをドレイン３の側のＡｌ電極９に接続
して、ＰＳＧ膜８上に８０ＯＡスパツタし、ホトエッチ
を行なう。図示のＴＰＴは、画素に対応する位置に１個
ずつ、多数ガラス基板上に形成されるので、偏光膜とカ
ラーフィルタを備えた他のガラス基板との間に液晶を封
入して、表示素子が完成する。(6) Since the TPT according to the present invention is used for driving each pixel of a display device, after that, IOT, which is a transparent electrode (not shown), is connected to the Al electrode 9 on the drain 3 side, and the TPT is placed on the PSG film 8. Sputter 80OA and photo-etch. The illustrated TPT is formed in large numbers on a glass substrate, one at a position corresponding to each pixel, so liquid crystal is sealed between a polarizing film and another glass substrate provided with a color filter, and the display element is Complete.
前述した本発明の一実施例によるＴＰＴは、キャリアの
移動度４０ ｃ ｍ”／Ｖｓ 、Ｌ／きい値電圧９Ｖを
得ることができた。このＴＰＴのＶ−Ｉ曲線は、第４図
に実線で示したようになり、ソース。The TPT according to the embodiment of the present invention described above was able to obtain a carrier mobility of 40 cm"/Vs and an L/threshold voltage of 9 V. The V-I curve of this TPT is shown as a solid line in FIG. Source as shown.
ドレイン間に２０ｖ、ゲートに２０Ｖを印加したときの
オン電流は、４Ｘ１０−’Ａ、ソース、ドレイン間に２
０Ｖを印加したときのオフ電流は、６ＸＩＯ−”Ａとな
り、オン電流は、従来技術の場合と同等の大きさが得ら
れ、オフ電流は、点線で示している従来技術の場合のオ
フ電流に比較して、約１／１０の値となった。When 20V is applied between the drain and 20V is applied to the gate, the on-current is 4X10-'A, and 20V is applied between the source and drain.
The off-state current when 0V is applied is 6XIO-"A, the on-state current is the same as that of the conventional technology, and the off-state current is the same as the off-state current of the prior art shown by the dotted line. In comparison, the value was about 1/10.
前述したように、本発明によれば、ＴＰＴのオン電流を
そこなうことなく、オフ電流を低減でき、高性能なＴＰ
Ｔを提供することができる。As described above, according to the present invention, the off-current can be reduced without damaging the on-current of the TPT, and a high-performance TPT can be obtained.
T can be provided.
第１図は本発明の一実施例の構造を示す断面図、第２図
、第３図は従来技術によるＴＰＴの概略を示す断面図、
第４図は本発明の一実施例によるＴＰＴのｖ−１曲線を
示す図である。
１・−・−ガラス基板、２−・−・−ソース、３−・・
−ドレイン、４−・・・−チャネル領域、５−−−−−
・・−ソース、ドレインと反対導電型の半導体層、６・
・・−・ゲート絶縁膜、７・−・−・−ゲート電極、８
−・・−・−ＰＳＧ膜、９・・−・Ａ１電極、１０・−
・・・・高不純物濃度層。
第１図
Ｉ・・・・ｒラス晶あ良 ６・・グー１
色縁５月隻２・・・ソース ７・・・デ
ートｔｍ３・・ ドレイン ８
・・・ＰＳＧ月凰４・・手ヤネル＃Ｈ域（ｊ４）
９・・・・Ａ１電１１５ ・ ソース、Ｆ“レインと
反ｒＩＶ叱包の！＃ＩｓＡ岑１１２図
１１２図！
１０・・・＆千純掬１度層
第４図
ケート電圧 Ｖｇ（Ｖ）FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, FIGS. 2 and 3 are sectional views showing an outline of a TPT according to the prior art,
FIG. 4 is a diagram showing a TPT v-1 curve according to an embodiment of the present invention. 1.--Glass substrate, 2-.--Source, 3-.
- drain, 4-...-channel region, 5-------
...-semiconductor layer of the opposite conductivity type to the source and drain, 6.
---Gate insulating film, 7----Gate electrode, 8
-...--PSG film, 9...-A1 electrode, 10--
...High impurity concentration layer. Figure 1 I...r last crystal 6... goo 1
Colored May ship 2... Source 7... Date tm3... Drain 8
...PSG Getsou 4...Teyanel #H area (j4)
9...A1 electric 115 ・ Source, F "Rain and anti-rIV scolding! #IsA 岑112Figure 112 figure! 10... & Senzumi 1 degree layer Figure 4 Kate voltage Vg (V)
Claims (1)
有する薄膜半導体装置において、半導体層内のチャネル
領域を真性半導体層で形成し、ソース及びドレイン領域
の下部に、該ソース及びドレイン領域と反対導電型の半
導体領域を備えることを特徴とする薄膜半導体装置。1. In a thin film semiconductor device having an insulating substrate and a semiconductor layer formed on the substrate, a channel region in the semiconductor layer is formed of an intrinsic semiconductor layer, and the source and drain regions are formed under the source and drain regions. A thin film semiconductor device comprising a semiconductor region having a conductivity type opposite to that of the semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27833887A JPH01120868A (en) | 1987-11-05 | 1987-11-05 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27833887A JPH01120868A (en) | 1987-11-05 | 1987-11-05 | Thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01120868A true JPH01120868A (en) | 1989-05-12 |
Family
ID=17595941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27833887A Pending JPH01120868A (en) | 1987-11-05 | 1987-11-05 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01120868A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996575A (en) * | 1989-08-29 | 1991-02-26 | David Sarnoff Research Center, Inc. | Low leakage silicon-on-insulator CMOS structure and method of making same |
| JPH0425179A (en) * | 1990-05-21 | 1992-01-28 | Seiko Instr Inc | Semiconductor device |
| US5316960A (en) * | 1989-07-11 | 1994-05-31 | Ricoh Company, Ltd. | C-MOS thin film transistor device manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52122484A (en) * | 1976-04-07 | 1977-10-14 | Hitachi Ltd | Field effect type polisilicon resistance element |
| JPS5586162A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Device and manufacturing method for insulating substrate type semiconductor |
| JPS62193170A (en) * | 1986-02-19 | 1987-08-25 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
-
1987
- 1987-11-05 JP JP27833887A patent/JPH01120868A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52122484A (en) * | 1976-04-07 | 1977-10-14 | Hitachi Ltd | Field effect type polisilicon resistance element |
| JPS5586162A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Device and manufacturing method for insulating substrate type semiconductor |
| JPS62193170A (en) * | 1986-02-19 | 1987-08-25 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316960A (en) * | 1989-07-11 | 1994-05-31 | Ricoh Company, Ltd. | C-MOS thin film transistor device manufacturing method |
| US4996575A (en) * | 1989-08-29 | 1991-02-26 | David Sarnoff Research Center, Inc. | Low leakage silicon-on-insulator CMOS structure and method of making same |
| JPH0425179A (en) * | 1990-05-21 | 1992-01-28 | Seiko Instr Inc | Semiconductor device |
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