JP2761496B2 - Thin film insulated gate semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film insulated gate semiconductor device having a large ON current / OFF current ratio (ON / OFF ratio), and particularly to a small OFF current, and more particularly to a thin film transistor (TFT).

[0002]

2. Description of the Related Art Recently, studies have been made on an insulating gate type semiconductor device having a thin film channel region on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal device, although they have a matrix structure. Depending on the material and crystal state of the semiconductor used,
A distinction is made between an amorphous silicon TFT and a polycrystalline silicon TFT. However, recently, research has been made on using a material exhibiting an intermediate state between polycrystalline silicon and amorphous. This is called semi-amorphous, and is considered to be a state in which small crystals float in an amorphous structure.

[0003] Also in a single crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technique, and this is used as a load transistor in, for example, a highly integrated SRAM. In this case, an amorphous silicon TFT is rarely used.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PTFT) cannot be manufactured. Therefore, in combination with an N-channel TFT (NTFT), a complementary MOS transistor is used. A circuit (CMOS) cannot be formed.

[0005] However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, unlike a transistor of an active matrix of a liquid crystal, such a high-speed operation is not required, and only one conductivity type is sufficient, and T
It is used for applications where FT is required.

On the other hand, a polycrystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and thus can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, a value as high as 300 cm ² / Vs is obtained as the electric field mobility. Since the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value,
The operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring. On the other hand, since the OS circuit is on an insulating substrate, there is no such restriction, and a remarkably high-speed operation is expected.

Further, in the case of polycrystalline silicon, not only the NTFT but also the PTFT can be obtained in the same manner, so that a CMOS circuit can be formed. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also the CMO for peripheral circuits (drivers, etc.)
There is known an S polycrystalline TFT having a so-called monolithic structure.

The above-mentioned TFT used in the SRAM also pays attention to this point, and the PMOS is constituted by the TFT.
This is used as a load transistor.

However, in general, a polycrystalline TFT has a larger electric field mobility than an amorphous TFT,
The OFF current was large, and the ability to hold the charge of the pixels of the active matrix was poor. Conventionally, the size of the pixel was several hundred μm square and the pixel capacity was large, so there was no particular problem. However, recently, the pixel size has been reduced along with the increase in the definition, and the pixel capacity has been reduced. Insufficient for static display. Also, in the case of using the SRAM, when the OFF current is large, the power consumption increases.

Further, in a normal amorphous TFT, it is difficult to form a source / drain region by a self-alignment process as used in a single crystal IC technology, and it is difficult to form a gate electrode and a source / drain region. Parasitic capacitance due to the overlap is a problem,
Since a polycrystalline TFT can adopt a self-alignment process, it has a feature that a parasitic capacitance is remarkably suppressed.

That is, as shown in FIG. 2, a conventional polycrystalline TFT is formed by forming a source region 204, a drain region 202 and a channel region 203 having substantially the same thickness on a substrate 201 and employing a self-alignment process. Done T
In the FT, the channel region (active layer) 203 was formed in almost the same shape as the gate electrode 205. In the figure, 20
6 is an interlayer insulator, and 207 and 208 are a drain electrode and a source electrode, respectively.

[0012]

SUMMARY OF THE INVENTION Such a polycrystalline TF
Several problems have been pointed out with respect to the advantages of T. Several solutions have been proposed for the problem of OFF current, one of them. One of them is
This is a method of thinning the activation region. It has been reported that this reduces the OFF current. For example, it is known that the OFF current can be reduced to 10 ⁻¹³ A or less by setting the thickness of the channel region to 25 nm. However, it is known that it is very difficult to crystallize a thin semiconductor film and it is not easily crystallized. That is, in order to obtain sufficient crystallinity and form an activation region (channel region) having a practically usable electric field mobility, a method of annealing at a high temperature or performing annealing for a long time is required. . When high-temperature annealing is employed, a heat-resistant material such as quartz is required for the substrate. However, quartz substrates, especially those with a large area, are very expensive and pose a problem in terms of cost. Further, performing the annealing for a long time also lowers the throughput, which is also difficult in terms of cost.

On the other hand, thinning the active layer leads to thinning of the source / drain regions. That is, in the normal manufacturing method, both the source / drain and the active region are formed from the semiconductor films manufactured at the same time and have the same thickness. This leads to an increase in the resistance of the source / drain region.

For this purpose, a method of separately forming a large part of the source / drain region so as to increase the thickness is adopted. However, this is an additional mask process, which is not preferable in terms of yield.

According to the knowledge of the present inventors, in a TFT having an active layer of 50 nm or less, the absolute value of the MOS threshold voltage is small.
When S is manufactured, the operation becomes extremely unstable.

On the other hand, when the activation layer is thickened, the OFF current increases. However, the magnitude is not proportional to the thickness of the active layer. Therefore, the OFF current increases nonlinearly due to some factors. Conceivable. FIG. 3A shows an example of characteristics of a TFT in which the thickness of the active layer is 100 nm.
Shown in In this method, the thickness of the gate oxide film is 150 nm, the active layer is formed by a low pressure CVD (LPCVD) method, and annealed at 600 ° C. for 24 hours.
The voltage between the source and the drain is 1V. As shown in the figure, the ON current is large, but the OFF current is also large. Moreover,
When a reverse bias is applied to the gate electrode, the gate electrode exhibits abnormal bumpy characteristics.

When the active layer is thick, a TFT having high crystallinity of the active layer and high electric field mobility can be obtained. No special high temperature or long annealing is required. As a result of the research conducted by the present inventors, it is clear that most of the OFF current of the TFT having a thick active layer flows in a bypass manner via a portion of the active layer on the substrate side as indicated by an arrow 209 in FIG. Was. When the ideal OFF current is I _OFF and the ON current is I _ON , the ON / OFF ratio of the TFT is I _ON
/ I _OFF . However, if a bypass-like leak current I _LK that hardly responds to the gate voltage is flowing, the ON / OFF ratio becomes (I _ON + I _LK ).
/ (I _OFF + I _LK ). Actually I _LK is I _OFF
Very large compared to, but because it is estimated that is either from the I _ON small, the ON / OFF ratio of the apparent, I
It is represented by _ON / _ILK . For this reason, it is considered that the ON / OFF ratio, which is an important index of the characteristics of the TFT, appears to be extremely small.

There are two possible causes of such a leak current. One is that the crystallinity of the active layer on the substrate side is not good. That is, since there are too many grain boundaries, many trap levels are formed there, and charges move by hopping the trap levels. Since this trap level exists regardless of the gate voltage, it always becomes a source of offset current. In this case, it can be overcome by optimizing the conditions of crystal growth, but it is expected to be very difficult.

Another reason is that mobile ions such as sodium enter the active layer from the substrate side to make the portion on the substrate side conductive. This is overcome by increasing the cleanliness of the process.

However, no matter which method is used to solve the problem, if the channel layer (active layer) is thick, the OFF current increases ohmicly. On the other hand, since the thickness of the source / drain is sufficient, the resistance at that portion is sufficiently small.

It is desired that an ideal TFT has a high electric field mobility. It is also desired that the source / drain resistance is small. On the other hand, it is desired that the OFF current be small. Of course, introducing complicated processes into the fabrication should be avoided. In view of the above situation, the present invention has been made to solve some or all of the above problems and to provide a TFT close to an ideal TFT.

[0022]

[Method of Solving the Problems] As a method of solving the above problems, in the present invention, the active layer has poor crystallinity.
Alternatively, a TFT which does not use a portion on the substrate side having poor characteristics as a channel for reasons such as remaining mobile ions is proposed. For this purpose, in the present invention, an impurity is added to a portion of the active layer on the substrate side to have conductivity opposite to that of the source / drain region, so that the portion does not substantially function as a channel.

FIG. 1 shows a conceptual diagram of a TFT according to the present invention. In FIG. 1, an impurity semiconductor region having a conductivity type opposite to that of the source region 104 and the drain region 102 is formed in a lower region 109 of an active layer region below a gate electrode 105. The upper region 103 of the active layer functions as a channel as in the related art, but the lower region 109 having poor characteristics on the substrate 101 side.
Does not function as a channel due to the added impurities. It is sufficient that the concentration of the impurity added to the region 109 is 1/10 to 1/100 of the impurity concentration added to the source / drain. This is because the conductivity type of the region 109 required at this time has a sufficiently different conductivity type than that of the channel region 103, or a gap of a conduction band (valence band) at an interface between the channel 103 and the region 109. Should be large enough. It is known that the level of the conduction (valence) band changes drastically in a semiconductor having a small amount of impurities by adding a very small amount of impurities. If the concentration of the impurity added to the source / drain is 10 ²⁰ cm ⁻³
Thus, the effective impurity concentration of the channel region 103 is 10 ¹⁶
cm ⁻³ , the impurity concentration of the region 109 is 10 ¹⁸ cm
^-3 is enough. Of course, the conductivity type of the impurity added to the region 109 must be selected so as to be opposite to that of the source / drain.

In order to form such a region 109, it is necessary to form two layers of semiconductor films having different impurity concentrations. For that purpose, a method of forming two layers of semiconductor films having different impurity concentrations in a multi-layered manner, or a method in which impurities are added to a substrate in advance and the semiconductor film is formed, and then the impurities may be diffused from the substrate. For example, assuming that the impurity concentration of the region 109 is one-tenth of the impurity concentration of the source / drain, if the source / drain is formed later by the self-alignment process, of the film formed earlier, The part which does not become the region 109 is easily converted to the same conductivity type as the source / drain by the introduction of impurities later. This is because the impurity concentration is low. Therefore, the channel region is thin and the source /
An ideal TFT of the present invention in which the drain region is thick is obtained.

If the impurity concentration in the region 109 is
If the impurity concentration is equal to or higher than the impurity concentration of the drain, the conductivity type cannot be changed at the time of forming the source / drain later.
The drain also becomes thin. of course,
Even with such a shape, it is not against the technical idea of the present invention that the active layer on the substrate side having poor characteristics is not used as a channel.

Although FIG. 1 shows that there is a clear boundary between the channel region 103 and the region 109 therebelow, such a clear boundary exists for the purpose of the present invention. Obviously, there is no need to do so, and it is clear that the material may be such that impurities or compositional elements are gently changed.

In the present invention, when the source / drain regions have uniform electrical characteristics such as resistivity in the thickness direction, the substantial source / drain thickness is smaller than the channel thickness. Is thin, and the source / drain resistance (sheet resistance) is large.

In the present invention, it is presumed that a band gap as shown in FIG. 3B is formed. That is,
FIG. 3B is a band diagram of a source / drain and a channel of the TFT having the structure described in FIG. 1 and a portion thereunder. In this figure, the PTFT is shown.
The same applies to NTFT. As is apparent from such a band diagram, holes in the valence band (electrons in the conduction band in the NTFT) are formed in regions 1 of different conductivity types below the channel.
09 is difficult to enter, and as a result, there is little current leakage through that portion.

The present invention may be applied to a conventional TFT as it is .
No. 40336 (JP-A-5-267666) , or
Japanese Patent Application No. 4-30220 (Japanese Patent Application Laid-Open No. 5-114724)
When applied to a TFT having an offset region as described in (1), a further effect is brought about. Each of the inventions was effective in reducing the OFF current, and particularly in improving reverse leakage when a reverse voltage was applied to the gate electrode, but was ineffective in reducing the absolute value of the OFF current. However, by using the present invention in combination with these inventions, the reverse leakage is suppressed, the absolute value of the OFF current is reduced, and the ON / OF is reduced.
The F ratio could be increased.

FIG. 3A shows an example of the effect. In the figure, (c) shows the characteristics of a conventional TFT (NTFT). (B) shows the case where the present invention is applied to a conventional TFT. Specifically, the channel region is doped with I-type polycrystalline silicon, and the lower portion is doped with boron of 2 × 10 ¹⁹ cm ⁻³ as an impurity. It is formed of weak P-type polycrystalline silicon. The source / drain was doped with 1.1 × 10 ²⁰ cm ⁻³ of phosphorus as an impurity to form a strong N-type.
That is, it is an NTFT. Gate is a silicon gate. In this case, the OFF current when the gate voltage is 0 is significantly reduced as compared with the conventional example, but the reverse leakage current is still large. This is because the channel becomes P-type due to the negative gate voltage, and the band structure of the source / drain (N-type) and the channel (P-type) is broken.
This is considered to be because the hopping current flows through a state existing at this boundary in a semiconductor having poor crystallinity such as a polycrystalline semiconductor in the n) state.

Therefore, for example, Japanese Patent Application No. 3-340336
If the present invention is applied to a TFT (aluminum gate) having an offset region as described in Japanese Patent Application Laid-Open No. 5-267666 , such a reverse leakage can be suppressed and a favorable leakage as shown in FIG. Characteristics are obtained. In this figure, the parts other than the gate electrode are the same as those shown in FIG. In particular, Japanese Patent Application No. 3-340336 (Japanese Unexamined Patent Application Publication No.
Hei 5-267666) or Japanese Patent Application Hei 4-3022
Even when an offset region is provided in a TFT as described in Japanese Patent Application Laid-Open No. 0 (Japanese Patent Application Laid-Open No. 5-114724) , the effect is not so good for a device having poor intercrystalline properties (eg, grain boundaries). This is because the cause of the backward leakage is due to the level existing at the grain boundary as described above, and it does not make much sense to provide an offset region in a semiconductor having poor grain boundary properties. It is.

That is, the aforementioned Japanese Patent Application No. 3-340336 is disclosed.
(JP-A-5-267666), or Japanese Patent Application No. 3-3
To implement the invention of providing an offset region as described in Japanese Patent Application Laid-Open No. 0220 (Japanese Patent Application Laid-Open No. 5-114724) , sufficient attention must be paid to the characteristics of the semiconductor. In this sense, synergistic effects are obtained by additionally implementing a method for preventing a portion having poor characteristics (active layer portion on the substrate side) from substantially functioning as a channel as in the present invention.

In the above description, only a TFT having a simple source / drain or a TFT having an offset region is treated as a TFT, but a TFT having a known low-concentration drain (LDD) structure may be used. . further,
This LDD structure is not only manufactured by a normal method, but also disclosed in, for example, Japanese Patent Application No. Hei 3-23871 of the present inventors.
0 to 3-238712. Examples are shown below to further describe the present invention.

[0034]

[Embodiment 1] FIG. 4 shows a CMO using the present invention.
An example of manufacturing S will be described. In this embodiment, a Corning 7059 glass substrate was used as the substrate 401.
On the substrate 401, a silicon nitride film 402 having a thickness of 20 to 100 nm, for example, 50 nm was formed by RF plasma CVD in order to prevent mobile ions from entering the substrate. Further, a silicon oxide film 403 having a thickness of 20 to 100 nm, for example, 50 nm was formed on the silicon nitride film by an RF plasma CVD method. The thickness of these films is designed according to the degree of penetration of mobile ions or the effect on the active layer.

For example, if the quality of the silicon nitride film 402 is not good and the amount of charge trapping is large, the upper semiconductor layer is affected through the silicon oxide film. In this case, it is necessary to increase the thickness of the silicon oxide film. .

These films may be formed not only by the above-described plasma CVD method but also by a method such as a low pressure CVD method or a sputtering method. The selection of these means may be determined in consideration of investment scale, mass productivity, and the like. Needless to say, these films may be continuously formed.

Further, a photoresist 404 was applied, and using this as a mask, a P-type region 406 and an N-type region 405 were formed. Boron is used as the P-type impurity and 5 × 10
¹² to 1 × 10 ¹⁴ cm ⁻² , for example, 2 × 10 ¹³ cm ⁻² only,
It was implanted by an ion doping method. Acceleration voltage is 10 ke
V. Further, phosphorus is used as the N-type
× 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , for example, 5 × 10 ¹³ cm ⁻²
Only by ion doping. Acceleration voltage is 1
0 keV. These acceleration voltage and dose amount are determined in consideration of the thickness of the silicon oxide film 403, the diffusion coefficient of each impurity by a subsequent heat treatment, and the like. In the present embodiment, since it is not a so-called through implantation, the acceleration voltage may be low. Thus, the state shown in FIG.

After that, the thickness 20
An amorphous silicon film having a thickness of 200 nm, for example, 100 nm was formed. The raw material used was monosilane, and the substrate temperature was 550 ° C. As a result of the study of the present inventors, it has been revealed that the substrate temperature has an important influence upon the subsequent crystallization. For example, it was difficult to crystallize a film formed from monosilane as a raw material at 480 ° C. or lower. On the other hand, a film formed using disilane as a raw material has a substrate temperature of 48.
Even a film formed at 0 ° C. was sufficiently crystallized by annealing at 600 ° C. The amorphous silicon film thus obtained was thermally annealed at 600 ° C. for 24 hours to be crystallized to obtain crystalline silicon called so-called semi-amorphous silicon. At this time, the respective impurities (boron and phosphorus) implanted into the silicon oxide film 403 thermally diffused into the silicon layer. In the study of the present inventors, the above-described annealing formed an impurity region diffused in a portion of about 30 nm below the crystalline silicon layer.

In order to promote crystallization, the concentration of carbon, nitrogen and oxygen in the silicon film is desirably 7 × 10 ¹⁹ cm ⁻³ or less. In the present embodiment, 1 ×
It was confirmed to be 10 ¹⁷ cm ^-3 or less.

In the conventional TFT, the silicon oxide film 40
Since an active layer of a semiconductor film is formed on No. 3, careful preparation was required. For example, the existence of mobile ions in the silicon oxide film 403 should never be present, but the existence of trap levels is even more critical. Although the penetration of mobile ions could be solved to some extent by cleaning the process, the trap level problem could not be improved beyond a certain level due to process constraints. In particular, the interface state density between the silicon oxide film and the semiconductor active layer thereon is determined by the TFT
Was an important factor in determining the characteristics of The level density at the interface between the gate oxide film (silicon oxide) for thermal oxidation and the single crystal semiconductor used in a normal single crystal semiconductor MOSIC is 1
Although it was about 0 ¹⁰ cm ^-2 , for example, the plasma CVD method or the atmospheric pressure CVD method (APCVD
Method) or a low-pressure CVD method (LPCVD method), and the interface state density between the silicon oxide film and the polycrystalline silicon film thereon was 10 ¹² cm ⁻² or more, which was not very practical.

That is, when the interface state density is high, various charges are trapped, and the conductivity type of the active layer is determined by these charges without depending on the gate voltage. invited. Therefore, conventionally, even such an underlying oxide film has been required to have the same high quality as the gate oxide film. For low-temperature and medium-temperature processes where thermal oxidation cannot be used, sputtering and ECR plasma CVD have been adopted, but the level density at the interface obtained by these methods is one order of magnitude higher than that of thermal oxidation. It was a big thing.

However, in the present invention, in a later process, a portion of the semiconductor film on the silicon oxide film 403 which is in contact with the silicon oxide film has a conductivity type different from that of the source / drain regions due to the addition of impurities. It rarely happens. That is, no matter what trap level is present in the silicon oxide film 403 and what kind of charge is trapped, impurities are introduced into the semiconductor film and the conductivity type is determined in advance. The charge trapping does not depend on the conductivity type of the semiconductor film. According to the study of the present inventors, if the impurity concentration of the impurity region formed by diffusion at the time of thermal annealing is 10 ¹⁸ cm ⁻³ , the interface state between the silicon oxide film 403 and the crystalline silicon film thereover is high. The potential density is 5 × 10 ¹² c
It was found that there was no problem up to about m- ² . Silicon oxide film 4
The impurity concentration of the crystalline silicon film formed on the silicon oxide film 03 depends on the balance with the impurity concentration of the source / drain regions to be formed later.
As the impurity concentration of the semiconductor region on the substrate 03 increases, the condition for the interface state density becomes gentler. The impurity concentration of the source / drain region is 10 ²⁰
Since it is possible to cm ^-3, as the impurity concentration of the semiconductor concentration, it can be up to about 10 ¹⁹ cm ^-3. In this case, the calculation allows an interface density of 10 ¹³ cm ^-3 .

Therefore, the RF plasma CV as described above
The silicon oxide film can be formed by the method D or another simple CVD method. RF plasma CVD and LPCV
D method and APCVD method include sputtering method and ECR plasma C
This method is more excellent in mass productivity than the VD method. That is,
In the sputtering method, a batch method cannot be adopted, mass productivity is low, and great care must be taken to prevent mobile ions from adhering to the target. In addition, since the size of the target cannot be increased unnecessarily, it is not suitable for increasing the area. The ECR plasma CVD method requires a huge investment in equipment, and the number and size of substrates that can be processed at one time are greatly restricted.

After the amorphous silicon film is converted into a crystalline silicon film by thermal annealing, the crystalline silicon film is etched into an appropriate pattern to separate the island-like semiconductor region 408 for NTFT and the island-like semiconductor region 407 for PTFT. Form. At this time, the P-type region 41 is formed below each semiconductor region due to the diffusion of impurities during thermal annealing.
0 and an N-type region 409 are formed. The top of each island semiconductor region was substantially intrinsic.

Thereafter, a gate insulating film (silicon oxide) 411 is formed to a thickness of 100 to 200 nm, for example, 150 nm by a sputtering method using silicon oxide as a target in an oxygen atmosphere.
Only nm was formed. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum film having a thickness of 500 nm was formed by a sputtering method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes / wirings 413 and 412. The etching rate is 2 when the etching temperature is 40 ° C.
It was 25 nm / min. Thus, the outer shape of the TFT was adjusted. The size of the channel at this time was 8 μm in length and 20 μm in width. The size of the channel may be designed according to the operation characteristics of the device. The state at this time is shown in FIG.

Further, aluminum oxide was formed on the surface of the aluminum wiring by anodic oxidation. The method of anodic oxidation is described in Japanese Patent Application No. Hei.
1188 or the method described in Japanese Patent Application No. 3-238713. A detailed embodiment may be changed depending on the characteristics of the target device, process conditions, investment scale, and the like. In this embodiment, the aluminum oxide films 415 and 41 having a thickness of 350 nm are anodized.
4 was formed.

Thereafter, an N-type source / drain region 417 and a P-type source / drain region 416 were formed by an ion implantation method through a gate oxide film with the aid of a known CMOS fabrication technique. In each case, the impurity concentration is 8 × 10 ¹⁹ c
m ⁻³ . As the ion source, boron fluoride ions were used for the P type and phosphorus ions were used for the N type. The former was implanted at an acceleration voltage of 80 keV, and the latter was implanted at an acceleration voltage of 110 keV. The acceleration voltage depends on the thickness of the gate oxide film and the semiconductor region 4.
The thickness is set in consideration of the thicknesses of 07 and 408. Instead of the ion implantation method, an ion doping method may be used. In the ion implantation method, ions to be implanted are separated by mass, so unnecessary ions are not implanted,
The size of a substrate that can be processed by the ion implantation apparatus is limited. On the other hand, in the ion doping method, although a relatively large substrate (for example, a diagonal of 30 inches or more) is capable of being processed, hydrogen ions and other unnecessary ions are simultaneously accelerated and implanted, so that the substrate is heated. Cheap. In this case, it is difficult to selectively implant impurities using a photoresist as a mask as used in the ion implantation method.

Thus, a TFT having an offset region was manufactured. This is shown in FIG. Finally, the source / drain regions were recrystallized by laser annealing using the gate electrode as a mask. The conditions for layer annealing are described, for example, in Japanese Patent Application No. Hei.
1188 and 3-238713. Then, silicon oxide is formed as an interlayer insulator 420 by an RF plasma CVD method, holes for forming electrodes are formed in the silicon oxide, and aluminum wirings 421 to 423 are formed.
The device was completed.

In this embodiment, an impurity region 409 formed by an impurity diffused from the silicon oxide film 403 first,
Although the impurity concentration of 410 is about 10 ¹⁸ cm ^-3 , the concentration of the impurity implanted for forming the source / drain is 80 times that of the impurity concentration of the impurity in the initial impurity region 409 as shown in FIG. , 410 have been converted to the same conductivity type as the source / drain except for the lower part of the channel, that is, regions 418 and 419 in FIG. As a result, the source / drain thickness is reduced to the island-shaped semiconductor region 40.
8, 408 were substantially the same. However, as can be seen from the figure, the substantial channel thickness is about 70
nm, which was thinner than the source / drain regions. As a result, it was possible to exhibit excellent characteristics such that the sheet resistance of the source / drain was small and the OFF current was small because the channel was thin.

Embodiment 2 FIG. 5 shows NT using the present invention.
Examples of manufacturing FT and PTFT will be described. In this embodiment, an N-0 glass substrate manufactured by NEC Corporation was used as the substrate 501. The N-0 glass substrate has a glass transition point higher by about 150 ° C. than that of Corning 7059 used in Example 1, and is effective for annealing at 650 ° C. to 750 ° C. However, since the amount of mobile ions contained in the substrate is large, sufficient measures must be taken against it. On the substrate 501, a 50-nm-thick silicon nitride film 502 is formed by RF in order to prevent mobile ions from entering the substrate.
It was formed by a plasma CVD method. Further, a 100-nm-thick silicon oxide film 503 was formed over the silicon nitride film by an RF plasma CVD method.

Further, boron is reduced to 2 by a low pressure CVD method.
Amorphous silicon film 5 containing only × 10 ¹⁸ cm ^-3
04 was formed with a thickness of 10 to 50 nm, for example, 30 nm. Then, a photoresist 506 was applied, and phosphorus was implanted by using this as a mask, for example, in an amount of 5 × 10 ¹⁸ cm ^{−2 by} ion doping to form an N-type region 505. That is, although boron is initially contained only at 2 × 10 ¹⁸ cm ⁻³ , the effect is negated by doping with phosphorus, and the region 505 is converted to N-type. The acceleration voltage at this time was 10 keV. Thus, the state shown in FIG.

After that, a thickness of 10
An amorphous silicon film containing no impurities of up to 150 nm, for example, 10 nm was formed. The substrate temperature was 550 ° C. As in the case of the amorphous silicon film 504 described above, sufficient attention must be paid to the intrusion of impurities. In any of the amorphous silicon films, the concentration of carbon, nitrogen and oxygen in the film is desirably 7 × 10 ¹⁹ cm ⁻³ or less, and in this embodiment, it is confirmed that the concentration is 1 × 10 ¹⁷ cm ⁻³ or less. did. The two-layered amorphous silicon film thus obtained was thermally annealed at 600 ° C. for 24 hours to be crystallized to obtain crystalline silicon called so-called semi-amorphous silicon.

After the amorphous silicon film is converted into a crystalline silicon film by thermal annealing, the crystalline silicon film is etched into an appropriate pattern, and the island-like semiconductor region 507 for NTFT and the island-like semiconductor region 508 for PTFT are formed. Form. The top of each island semiconductor region was substantially intrinsic.

Thereafter, a gate insulating film (silicon oxide) 509 having a thickness of 150 nm was formed by a sputtering method using silicon oxide as a target in an oxygen atmosphere. This thickness is determined by the operating conditions of the TFT and the like.

Next, phosphorus is reduced to 1.2 by a low pressure CVD method.
A silicon film containing × 10 ²⁰ cm ^{-3 is} formed to a thickness of 500 nm, and is patterned to form a gate electrode / wiring 5.
10 and 511 were formed. In this way, the TFT
Has been trimmed. The size of the channel at this time was 8 μm in length and 20 μm in width. The state at this time is shown in FIG.

Thereafter, as shown in FIG. 5C, boron was implanted by an ion implantation method through a gate oxide film. At this time, the acceleration voltage was 100 keV, and the boron concentration was 5 × 10 ¹⁹ cm ⁻² . Thus, the source / drain region 512 of the PTFT on the left side of the figure was formed. At this time, a channel region 514 and an N-type region 515 thereunder are also formed at the same time. On the other hand, NT on the right side of the figure
FT is also doped with boron at its source / drain.
However, at this stage, an impurity region functioning as a TFT is not formed.

Further, a photoresist 513 is applied,
This selectively covers only the PTFT (FIG. 5).
(D)) In this state, phosphorus ions were implanted. The acceleration voltage was 100 keV. In this way, NTF
T source / drain regions 516 were formed. The concentration of phosphorus was set to 1.1 × 10 ²⁰ cm ⁻³ . At the same time, a channel region 517 and a P-type region 518 thereunder are also formed.

Thereafter, annealing was performed at 600 ° C. for 24 hours to recover the damage caused by the ion implantation. Looking at how the region 505 of the PTFT changed thereafter, for example, the TFT obtained in this way was initially N-type, containing 5 × 10 ¹⁸ cm ⁻³ of phosphorus. , Then an order of magnitude more,
Since boron was injected, it was converted to P-type. On the other hand, NTF
Focusing on the area under the channel of T, initially 2 × 10
It was a P-type containing ¹⁸ cm ^-3 boron. Thereafter, the boron concentration was further increased to 5 × 10 ¹⁹ cm ⁻³ by the boron implantation shown in FIG. However, FIG.
By the phosphorus injection of (D), phosphorus more than twice the concentration of boron was injected and converted to N-type. In this example, as is apparent from the figure, the thickness of the source / drain was 40 nm, while the thickness of the channel portion was 10 nm. Further, the impurity regions 515 and 518 do not function as a channel. Therefore, an ideal TFT could be formed.

In this embodiment, the number of masks used is four, that is, the formation of the region 505, the formation of the island regions 507 and 508, the formation of the gate electrodes / wirings 510 and 511, and the patterning of the photoresist 513. Thereafter, further masks are used to form metal interconnects.

On the other hand, according to the method of the first embodiment, the number of masks used until the formation of the source / drain regions is the same as that of the present embodiment. Formation of 407, 408,
Six masks for forming gate electrodes / wirings 412 and 413, forming source / drain 416 (or 417), and forming source / drain 417 (or 416) are required. As described above, this embodiment is effective for simplifying the process and thereby improving the yield.

Embodiment 3 In this embodiment, an example in which the present invention is applied to a TFT formed on a semiconductor integrated circuit formed on a single crystal semiconductor substrate will be described. With the increase in the degree of integration of semiconductor integrated circuits, three-dimensional integrated circuits (three-dimensional integrated circuits) in which circuits are developed not only on the plane of a semiconductor substrate as in the past but also in the vertical direction are required. Was. At present, practically used ones are limited to a two-layer transistor structure using only a PMOS as a TFT among flip-flop circuit transistors, such as a full CMOS type SRAM. As the degree of integration of integrated circuits increases, more multilayer structures are used. At the same time, TFTs are also required to have improved characteristics.

In this embodiment, a case where a first transistor (NMOS) is formed on a single crystal silicon substrate and a second transistor (PMOS) is formed thereon by a TFT will be described.

FIG. 6A shows a semiconductor circuit having such a structure. For simplicity, the metal wiring is not shown in the figure. In the figure, a source region 602 and a drain region 603 (both are N-type) are provided over a substrate 601, and a gate electrode 604 of a first transistor is formed. Further, these are covered by an interlayer insulator 60.
5 are formed. Conventionally, a glass material having a relatively low melting point, such as phosphorus glass or phosphorus boron glass, has been used as the interlayer insulating material.
The reduction of unevenness caused by the formation of wiring has been performed.

The TFT is formed on such an interlayer insulator. That is, a polycrystalline silicon film having a source region (P type) 606, a drain region (P type) 607, and a channel region 608 is formed over the interlayer insulator 605.
Further, a gate insulating film is formed on the polycrystalline silicon film, and a gate electrode 609 of the second transistor is formed. Finally, the entire element is covered with an insulating film 610.

In the TFT having such a structure, if
When the interlayer insulator is made of a conventional material such as phosphorus glass or phosphorus boron glass, the interlayer insulator 6 is formed by a voltage applied to the gate electrode 604 of the first transistor.
There is a possibility that charges may be trapped in the layer 05 or the interlayer insulator may be polarized. For example, assuming that charges 612 are trapped on the upper surface of the first gate electrode 604 and the lower surface of the channel region 608 by such an effect, a P-type inversion layer 611 is formed below the channel region 608, and A leak current flows from the source to the drain via the portion.

Therefore, it is necessary to avoid forming a channel region directly on a material such as phosphorus glass or phosphorus boron glass. Ideally, it was required to form an interlayer insulator with a pure silicon oxide film and further form a high-quality silicon oxide film thereon by thermal oxidation.
However, in that case, reflow was difficult because silicon oxide, which is a high melting point material, was used as the interlayer insulator. Therefore, it is required that an interlayer insulator is formed using a glass material suitable for performing reflow, and an oxide film is formed thereon by a low-temperature film forming technique such as a sputtering method or an ECR plasma CVD method. Regardless of which method is used, doubling the film forming process leads to a decrease in throughput. In particular, low-quality silicon oxide, phosphorus glass, and the like are formed by a low-pressure CVD method with good mass productivity, but the sputtering method and the ECR plasma CVD method are inferior in mass productivity. In particular, in order to sufficiently reduce the influence of the electric charge of the lower insulator, the thickness of the high-quality silicon oxide film is 300 n.
m or more is necessary. It takes a very long time to form a silicon oxide film having such a thickness by sputtering or ECR plasma CVD.

This problem is solved by applying the present invention. An embodiment of the present invention is shown in FIG.
In the figure, a source region 652 and a drain region 653 (both are N-type) are provided on a substrate 651, and
The gate electrode 654 of the transistor is formed.
Further, an interlayer insulator 655 is formed to cover them. This may be a low-grade silicon oxide or a material such as phosphorus glass or phosphorus boron glass.

The TFT is formed on such an interlayer insulator. That is, a source region (P type) 656 and a drain region (P type) 657 are formed over the interlayer insulator 655. Conventionally, a channel region is formed between the source and the drain. In the present invention, an N-type region 661 is formed on the lower side, and a channel region 658 is formed thereon.
Is formed. These are all polycrystalline silicon films. Further, a gate insulating film is formed on the polycrystalline silicon film, and a gate electrode 659 of the second transistor is formed. Finally, the entire element is covered with an insulating film 660.

Whether the material of the interlayer insulator 655 is silicon oxide excellent in heat resistance or a glass-based material capable of reflow must be selected according to the characteristics of the device. That is, when a glass-based material is used, it is difficult to form the gate oxide film of the second transistor by thermal oxidation. Therefore, the properties are not very good.

The impurity concentration of the N-type region 661 which is a feature of the present invention is determined in consideration of the impurity concentration of the source / drain, the impurity concentration of the channel region, the characteristics of the underlying interlayer insulator, and the like. Typically 1 × 10 ^{17 to} 5 × 1
0 ¹⁹ cm ^-3 . For example, 3 × 10
An N-type impurity of ¹⁶ cm ^-3 is doped, a source / drain is doped with a P-type impurity of 6 × 10 ¹⁹ cm ^-3 , and the interface state density of the interlayer insulator is 2 × 10 ¹² cm ^{− In} the case of ² , 1 × 10 ^{18 to} 3 × 10 ¹⁹ cm ⁻³ is appropriate.

The thickness of the N-type region 661 is determined in consideration of the impurity concentration and the characteristics of the underlying interlayer insulator (particularly, interface state density). Since the charge existing in the channel is shielded, it may be thinner than when a channel is formed directly on the interlayer insulator as described above. Typically, there is no problem if it is 10 nm or more. For example, the impurity concentration of the N-type region 661 is 3 × 10 ¹⁹
In the case where a charge of 2 × 10 ¹² cm ⁻² is trapped on the surface of the interlayer insulator at cm ⁻³ , a thickness of 7 nm is sufficient. However, if it is too thin, other factors such as inhomogeneity of the film thickness reduce reliability.

On the other hand, when it is too thick, it takes a long time to form a film. Considering the above, 10 to 100 nm
Is appropriate. In forming such a region, it is desirable to employ the method described in the second embodiment.

That is, an N-type silicon film is formed on the interlayer insulator 655, and then an I-type or N ^- type silicon film is formed. This film formation may be performed continuously by a so-called multi-chamber method. Then, a gate insulating film and a gate electrode are formed, and a source 606 and a drain 607 are formed by a self-alignment process.

[0075]

According to the present invention, a good TFT having extremely small OFF current when a reverse voltage is applied to the gate.
Could be produced. The present invention is even more effective when combined with other inventions. For example, as shown in the embodiment, Japanese Patent Application No. Hei.
A further effect can be obtained by combining it with No. 88 or Japanese Patent Application No. 3-238713. Further, in the present invention, as shown in the embodiment, the thickness of the source / drain can be increased to reduce the sheet resistance. As a result, high-speed operation of the TFT circuit was realized.

Conventionally, polycrystalline TFTs are ON / O, especially for purposes such as the active matrix of liquid crystal display devices.
Although the FF ratio was low and there were various difficulties for practical use,
The present invention appears to have largely solved such problems. Further, as described in the third embodiment, the present invention can be applied to a three-dimensional single crystal semiconductor integrated circuit. Thus, the present invention is considered to be an industrially extremely useful invention.

[Brief description of the drawings]

FIG. 1 shows a conceptual diagram of a TFT of the present invention.

FIG. 2 shows a conceptual diagram of a conventional TFT.

FIG. 3 shows an example of characteristics of the present invention and a conventional TFT, and an expected energy band diagram of the TFT of the present invention.

FIG. 4 shows a manufacturing process of the TFT of the present invention.

FIG. 5 shows a manufacturing process of the TFT of the present invention.

FIG. 6 shows an application example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Drain region 103 ... Channel region 104 ... Source region 105 ... Gate electrode 106 ... Interlayer insulator 107 ... Drain electrode / wiring 108 ... Source electrode .Wiring 109: impurity region

Continuation of the front page (72) Inventor Hiroyuki Zhang 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Laboratory Co., Ltd. (56) References JP-A-62-214668 (JP, A)

Claims (7)

(57) [Claims] (A) a silicon oxide film formed on a substrate having an insulating surface and selectively formed with an impurity region into which an impurity of a first conductivity type is introduced; and (b) a silicon oxide film formed on the impurity region. A polycrystalline silicon film having the second conductive type source and drain regions formed, and a channel forming region sandwiched between the source and drain regions; and (c) the channel forming region of the polycrystalline silicon film. A gate electrode covered with an anodic oxide film disposed so as to have an offset region thereon, wherein only a lower layer portion of the channel forming region which is in contact with the impurity region is of a first conductivity type. Thin-film insulated gate semiconductor device. 2. (a) Oxidation formed on a substrate having an insulating surface, wherein a P-type impurity region into which a P-type impurity is introduced and an N-type impurity region into which an N-type impurity is introduced are selectively formed. A silicon film; and (b) a first channel formation region having an N-type source and drain region formed on the P-type impurity region and a first channel formation region sandwiched between the N-type source and drain regions.
(C) a P-type source and drain region formed on the N-type impurity region, and a second channel formation region sandwiched between the P-type source and drain regions. Having a second
And (d) a gate electrode covered with an anodic oxide film and arranged on the channel forming region of the first and second polycrystalline silicon films so as to have an offset region. Only the lower layer portion of the first channel formation region that contacts the P-type impurity region is P-type, and only the lower layer portion of the second channel formation region that contacts the N-type impurity region is N-type. A thin-film insulated gate semiconductor device characterized by the above-mentioned. (A) forming a silicon oxide film on a substrate having an insulating surface; and (b) selectively forming an impurity region in which a first conductivity type impurity is introduced into the silicon oxide film. (C) forming an amorphous semiconductor thin film exhibiting substantially intrinsic conductivity on the impurity region; and (d) crystallizing the semiconductor thin film by thermal annealing and the first conductive film. (E) forming a gate electrode on the semiconductor thin film via a gate insulating film; and (f) anodizing the surface of the gate electrode. (G) introducing the second conductivity type impurity into the semiconductor thin film using the gate electrode and the anodic oxide film as a mask to form source / drain regions and offset regions. Forming a thin-film insulated gate semiconductor device. (A) forming a silicon oxide film on a substrate having an insulating surface; and (b) introducing an N-type region into which an N-type impurity is introduced and a P-type impurity into the silicon oxide film. Selectively forming a P-type impurity region; (c) forming a semiconductor thin film having substantially intrinsic conductivity on each of the N-type impurity region and the P-type impurity region; Crystallizing the semiconductor thin film by thermal annealing, and diffusing the impurities contained in the N-type impurity region and the P-type impurity region respectively into lower layers of the semiconductor thin film; and (e) a gate insulating film on the semiconductor thin film. Forming a gate electrode through anodization; (f) forming an anodized film by anodizing the surface of the gate electrode; and (g) forming a P-type film using the gate electrode and the anodized film as a mask. of Introducing an impurity into at least the semiconductor thin film on the N-type impurity region to form an N-type source / drain region and a first offset region; and (h) forming an N-type using the gate electrode and the anodic oxide film as a mask. Forming a P-type source / drain region and a second offset region by introducing at least a P-type impurity into a semiconductor thin film on the P-type impurity region. Method of manufacturing. 5. The process according to claim 4, wherein the dose of the P-type impurity is 5 × 10 ¹² to 1 × 10 ^14.
cm ⁻² . 6. The process according to claim 4, wherein the dose of the N-type impurity is 5 × 10 ¹² to 1 × 10 ^14.
cm ⁻² . 7. The method according to claim 4, wherein the dose of the P-type impurity and the dose of the N-type impurity are 5 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , respectively. Thin-film insulated gate semiconductor device.