JP5110888B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a thin film transistor.

In the case where a plurality of semiconductor elements are provided over an insulating surface, a method of processing a semiconductor film formed over the insulating surface into a plurality of island-shaped semiconductor layers by an etching process is used. A semiconductor element has a stacked structure of a plurality of thin films. In the case of a planar thin film transistor, a gate insulating layer is stacked so as to cover a semiconductor layer separated in an island shape.

Since the semiconductor layer processed into an island shape has a step at the end, defects such as thinning of the gate insulating layer and destruction of the film occur at the end of the semiconductor layer.

When the gate insulating layer is thinned, a leak current flows between the gate electrode and the semiconductor layer, and when the gate insulating layer is destroyed, the gate electrode and the semiconductor layer come into contact with each other and short-circuit (short). The characteristic defect occurs.

In order to solve the above problem, a method of laminating two gate insulating layers having different shapes to alleviate a step due to an end portion of a semiconductor layer and improving coverage is performed. (For example, refer to Patent Document 1).
JP-A-10-242471

However, the above-described method for reducing the level difference cannot sufficiently prevent a short circuit due to contact between the semiconductor film and the gate electrode and a defect such as a leakage current depending on the film thickness of the semiconductor layer and the gate insulating layer. It was. In particular, when the semiconductor element is miniaturized (for example, the gate length is 1 μm or less), there is a problem that the leakage current appears remarkably.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device in which a short circuit between a gate electrode and a semiconductor layer due to a poor covering of a gate insulating layer and a defect such as a leakage current are prevented, and a semiconductor device with low power consumption. To do.

The semiconductor device of the present invention has a sidewall insulating layer on the side surface of the semiconductor layer, and a gate insulating layer is provided on the side surface of the semiconductor layer via the insulating layer. Further, the source and drain regions of the semiconductor layer have silicide, and the wiring layer provided in contact with the silicide and the source and drain regions of the semiconductor layer are electrically connected.

By providing the sidewall insulating layer in contact with the side surface of the semiconductor layer, the coverage of the gate insulating layer at the end of the semiconductor layer can be improved. Accordingly, it is possible to prevent defects due to poor coverage of the gate insulating layer at the end portion of the semiconductor layer, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, and the like.

With the silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Furthermore, since operation at a low voltage is possible, power consumption can be reduced.

Therefore, the semiconductor device of the present invention can be a semiconductor device with low power consumption and high reliability.

Note that in the present invention, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. By using the present invention, a device having a circuit including a semiconductor element (a transistor, a memory element, a diode, or the like) or a semiconductor device such as a chip having a processor circuit can be manufactured.

One embodiment of a semiconductor device of the present invention includes a semiconductor layer including a source region, a drain region, and a channel formation region over an insulating surface, a first side insulating layer that covers a side surface of the semiconductor layer, a semiconductor layer, and a first side surface. A gate insulating layer on the insulating layer; a gate electrode layer on the gate insulating layer; and a second side insulating layer that covers a side surface of the gate electrode layer. The gate insulating layer covers a channel formation region of the semiconductor layer. The source region and the drain region are provided with silicide on the surface.

One embodiment of a semiconductor device of the present invention includes a semiconductor layer including a source region, a drain region, and a channel formation region over an insulating surface, a first side insulating layer that covers a side surface of the semiconductor layer, a semiconductor layer, and a first side surface. A gate insulating layer on the insulating layer; a gate electrode layer on the gate insulating layer; and a second side insulating layer that covers a side surface of the gate electrode layer. The gate insulating layer covers a channel formation region of the semiconductor layer. The source region and the drain region are provided with silicide on the surface, and each of the source region and the drain region includes an impurity region having a lower conductivity type than the source region and the drain region between the channel formation region and the source region and the drain region.

One embodiment of a semiconductor device of the present invention includes a semiconductor layer including a source region, a drain region, and a channel formation region over an insulating surface, a first side insulating layer that covers a side surface of the semiconductor layer, a semiconductor layer, and a first side surface. A gate insulating layer on the insulating layer; a gate electrode layer on the gate insulating layer; and a second side insulating layer that covers a side surface of the gate electrode layer. The gate insulating layer covers a channel formation region of the semiconductor layer. The source region and the drain region are provided with silicide on the surface, and a wiring layer is formed in contact with the silicide.

One embodiment of a semiconductor device of the present invention includes a semiconductor layer including a source region, a drain region, and a channel formation region over an insulating surface, a first side insulating layer that covers a side surface of the semiconductor layer, a semiconductor layer, and a first side surface. A gate insulating layer on the insulating layer; a gate electrode layer on the gate insulating layer; and a second side insulating layer that covers a side surface of the gate electrode layer. The gate insulating layer covers a channel formation region of the semiconductor layer. The source region and the drain region are provided with silicide on the surface, and each of the source region and the drain region includes an impurity region having one conductivity type having a lower concentration than the source region and the drain region, and between the source region and the drain region, A wiring layer is formed in contact therewith.

In the semiconductor device of the present invention, by providing the side surface insulating layer on the side surface of the semiconductor layer, the step difference due to the end portion of the semiconductor layer is reduced, so that the coverage of the gate insulating layer is improved.

Accordingly, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented. Therefore, further miniaturization and high precision can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved.

Furthermore, the resistance of the source region and the drain region can be reduced by the silicide structure, and the speed of the semiconductor device can be increased.

Therefore, the semiconductor device of the present invention can be a semiconductor device with low power consumption and high reliability.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a semiconductor device with low power consumption and high reliability and a method for manufacturing the semiconductor device will be described in detail with reference to FIGS.

1A to 1C illustrate one embodiment of a semiconductor device using the present invention. 1A is a plan view of the semiconductor device of this embodiment, FIG. 1B is a cross-sectional view taken along line V-X in FIG. 1A, and FIG. 1C is FIG. Is a sectional view taken along line YZ in FIG. Note that several types of insulating layers are omitted in FIG.

A thin film transistor 115, an insulating film 108, and an insulating layer 109 are formed over a substrate 100 over which insulating layers 101a and 101b functioning as base films for a semiconductor layer are formed. The thin film transistor 115 includes impurity regions 112 a and 112 b having one conductivity type which are source regions or drain regions, a semiconductor layer 103 including a channel formation region 111, a gate insulating layer 105, and a gate electrode layer 106. Silicides 113a and 113b are formed in impurity regions 112a and 112b having one conductivity type which are source regions or drain regions, and a wiring layer 110a which is a source electrode layer or a drain electrode layer connected to the silicides 113a and 113b. A wiring layer 110b which is a source electrode layer or a drain electrode layer connected to the silicide 113b is provided, and the thin film transistor 115 can be electrically connected to another semiconductor element or the like by the wiring layer 211b (FIG. 1A ) To (C)).

The side surface of the semiconductor layer 103 is covered with sidewall insulating layers 104a, 104b, 104c, and 104d. By providing the sidewall insulating layers 104a, 104b, 104c, and 104d in contact with the side surfaces of the semiconductor layer 103, the coverage of the gate insulating layer at the end portion of the semiconductor layer 103 can be improved. Therefore, defects due to poor coverage of the gate insulating layer at the end portion of the semiconductor layer 103, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, or the like can be prevented.

The sidewall insulating layers 104a, 104b, 104c, and 104d can be formed in a self-aligned manner by depositing a silicon oxide film or a silicon nitride film after forming the semiconductor layer 103 and processing it by anisotropic etching. . In addition, the sidewall insulating layers 104a, 104b, 104c, and 104d can be selectively insulated by oxidizing an end portion of the semiconductor layer 103. The oxidation treatment can be performed by plasma treatment in an atmosphere containing oxygen. Alternatively, the surface may be oxidized (also referred to as wet oxidation) using an aqueous solution. Plasma treatment may be performed after introducing a halogen such as fluorine or chlorine into the semiconductor layer side end portion before the plasma treatment. When halogen is added, the oxidation rate is high, so that the oxidation proceeds preferentially, and a thick insulating layer can be formed at the semiconductor layer side end.

A method for forming a sidewall insulating layer at an end portion of a semiconductor layer by using wet oxidation will be described with reference to FIGS. A semiconductor film is formed over the insulating layers 151a and 151b formed over the substrate 150, a mask 153 is selectively formed over the semiconductor film, and the semiconductor film is etched using the mask 153, whereby an island-shaped semiconductor is formed. The layer 152 is formed (see FIG. 4A). Then, by performing wet oxidation 154 on the end portion of the semiconductor layer 152 before removing the mask 153, sidewall insulating layers 155a and 155b are formed on the end portion of the semiconductor layer 152, and the sidewall insulating layers 155a and 155b are formed. The semiconductor layer 156 can be formed (see FIG. 4B). Then, the mask is removed and a gate insulating layer 157 is formed to cover the semiconductor layer 156 including the sidewall insulating layers 155a and 155b (see FIG. 4C). For example, wet oxidation is performed by treating the surface of the semiconductor layer 152 with an aqueous solution (typically ozone water) containing ozone (O ₃ ) of 5 ppm or more, desirably 20 ppm or more, more desirably 100 ppm or more. Sidewall insulating layers 155a and 155b made of an oxide film can be formed on the exposed portion of 152. Note that, instead of an aqueous solution containing ozone, an aqueous solution containing hydrogen peroxide (H ₂ O ₂ ), an aqueous solution containing sulfuric acid (H ₂ SO ₄ ), an aqueous solution containing iodic acid (HIO ₃ ), or nitric acid (HNO ₃ ) An aqueous solution containing can also be used. Each aqueous solution may contain an organic acid such as acetic acid or oxalic acid.

Since the oxidation can proceed from the exposed portion of the end portion of the semiconductor layer 152, an oxide film can be selectively formed thick on the end portion of the semiconductor layer 152. Therefore, the electric field concentration in the vicinity of the end portion of the semiconductor layer can be relaxed, the gate leakage defect can be reduced, and the breakdown voltage of the gate electrode can be improved.

Further, a method for forming a sidewall insulating layer at an end portion of a semiconductor layer by using plasma treatment will be described with reference to FIGS. As described in the wet oxidation, the sidewall insulating layer may be formed by performing plasma treatment on the end portion of the semiconductor layer in an atmosphere containing oxygen with only the end portion of the semiconductor layer exposed. Alternatively, plasma treatment may be performed on the entire surface of the island-shaped semiconductor layer, and the insulating layer may be formed so as to cover the surface of the semiconductor layer.

By sequentially forming a semiconductor film and an insulating layer functioning as the gate insulating layer 168 over the insulating layers 161a and 161b formed over the substrate 160, the semiconductor film and the insulating layer are etched using the mask 163, An island-shaped semiconductor layer 162 and a gate insulating layer 168 are formed. After that, the mask 163 is removed, and plasma treatment 164 is performed on a portion where the semiconductor layer at the end of the gate insulating layer 168 and the semiconductor layer 162 is exposed, whereby an insulating layer is formed on the end and the surface of the semiconductor layer 162. 165 can be formed. Therefore, the semiconductor layer 166 having the insulating layer 165 on the surface and the end portion can be formed (see FIG. 5C).

In FIG. 5, since the plasma treatment 164 is performed from the surface of the gate insulating layer 168, not only the end portion of the semiconductor layer 162 but also the surface of the semiconductor layer 162 in contact with the gate insulating layer 168 is oxidized. Accordingly, the insulating layer 165 is also formed on the surface of the semiconductor layer 162 in contact with the gate insulating layer 168.

By sufficiently covering the end portion of the semiconductor layer 103 with the gate insulating layer, preferably by increasing the thickness of the region in contact with the side surface of the semiconductor layer 103, the electric field applied to the end portion of the semiconductor layer 103 can be reduced. It is possible to prevent the occurrence of leakage current.

In addition, the side wall insulating layers 104a, 104b, 104c, and 104d preferably have a lower dielectric constant than the gate insulating layer 105. Compared with the gate insulating layer 105, by reducing the dielectric constant of the sidewall insulating layers 104a, 104b, 104c, and 104d, it is possible to alleviate the concentration of the electric field at the edge of the semiconductor layer, particularly at the corner (corner). . For example, the sidewall insulating layers 107a to 107h may be formed of a low dielectric constant material having a relative dielectric constant of 2.5 or less. As the low dielectric constant material, porous silicon oxide, carbon or fluorine-containing silicon oxide produced by a CVD method can be used. By forming the sidewall insulating layers 104a, 104b, 104c, and 104d with a low dielectric constant material, the same effect as when the film thickness is increased can be obtained. It is possible to prevent an excessive electric field from being locally applied to the gate insulating layer and to prevent insulation failure of the gate insulating layer. Accordingly, thin film transistors can be manufactured with high yield, and the reliability of a completed semiconductor device can be improved.

The semiconductor device of this embodiment can be a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented.

Further, in FIG. 1B, the impurity region is indicated by hatching and white background, but this does not indicate that the impurity element is not added to the white background portion, but the concentration of the impurity element in this region. This is because it is possible to intuitively understand that the distribution reflects the mask and doping conditions. This also applies to other drawings in this specification.

As the substrate 100 which is a substrate having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used.

As the insulating layers 101a and 101b, the gate insulating layer 105, the insulating film 108, and the insulating layer 109, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used. It may be a structure. Note that in this specification, silicon oxynitride is a substance in which the oxygen content is higher than the nitrogen content, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the nitrogen content is higher than the oxygen content, and can be said to be silicon nitride containing oxygen.

Further, as other materials of the insulating layers 101a and 101b, the gate insulating layer 105, the insulating film 108, and the insulating layer 109, aluminum nitride, aluminum oxynitride having an oxygen content higher than the nitrogen content, and nitrogen content having an oxygen content It can be formed of a material selected from a material including more aluminum nitride oxide or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon, polysilazane, and other inorganic insulating materials. A material containing siloxane may be used. Note that siloxane corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The insulating layers 101a and 101b, the gate insulating layer 105, the insulating film 108, and the insulating layer 109 are formed by a CVD method (Chemical Vapor) such as a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a plasma CVD method. Deposition), a droplet discharge method that can selectively form a pattern, a printing method that can transfer or depict a pattern (a method that forms a pattern such as screen printing or offset printing), and other coating methods such as spin coating. A dipping method, a dispenser method, or the like can also be used.

As the etching process for processing into a desired shape, either plasma etching (dry etching) or wet etching may be employed. Plasma etching is suitable for processing large area substrates. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

Alternatively, the gate insulating layer 105 may be formed by performing plasma treatment on the semiconductor layer.

As a typical example of the semiconductor layer, the surface of the silicon layer is oxidized by plasma treatment, whereby a dense oxide layer without distortion at the interface can be formed. Further, the oxide layer can be further densified by nitriding the plasma layer by plasma treatment to form a nitride layer by replacing oxygen in the surface layer with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

However, in the present invention, plasma treatment is performed under conditions that do not adversely affect the electrical characteristics of the transistor.

In addition, after forming a substrate, an insulating layer, an interlayer insulating layer, and other insulating layers and conductive layers forming a semiconductor device, the substrate, the insulating layer, and the interlayer are formed by performing oxidation treatment or nitriding treatment using plasma treatment. The surface of the insulating layer may be oxidized or nitrided. When a semiconductor layer or an insulating layer is oxidized or nitrided using plasma treatment, the surface of the insulating layer is modified so that the insulating layer becomes denser than an insulating layer formed by a CVD method or a sputtering method. it can. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved. The plasma treatment as described above can also be performed on a conductive layer such as a gate electrode layer, a source wiring layer, and a drain wiring layer, and the surface and the vicinity of the surface can be nitrided or oxidized.

The silicides 113a and 113b are formed by forming a conductive film over the exposed source region and drain region of the semiconductor layer and reacting silicon in the semiconductor layer with the conductive film 766 by heat treatment, a GRTA method, an LRTA method, or the like. To do. As the material of the conductive film, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), tantalum (Ta), vanadium (V ), Neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like. Further, silicide may be formed by laser irradiation or light irradiation with a lamp.

In the present invention, since the sidewall insulating layers 104a to 104d are provided on the side surface of the semiconductor layer 103, the side surface of the semiconductor layer 103 is not in contact with the conductive film 122 for silicide formation. Therefore, the side surface of the semiconductor layer 103 can be prevented from being etched when the conductive film that has not reacted is removed. Accordingly, defects due to the poor coverage of the gate insulating layer at the end portion of the semiconductor layer 103, such as a short circuit between the semiconductor layer and the gate electrode layer, the occurrence of leakage current, and electrostatic breakdown can be prevented.

With the silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Furthermore, since operation at a low voltage is possible, power consumption can be reduced.

The semiconductor layer 103 is preferably formed using a crystalline semiconductor. For example, a semiconductor layer formed over the entire surface of the substrate can be crystallized and formed on the substrate by a sputtering method, a plasma CVD method, or a low pressure CVD method. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used.

An impurity element imparting p-type conductivity may be implanted into the semiconductor layer 103. For example, boron is used as the impurity element imparting p-type conductivity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the transistor, and effectively acts when added to the channel formation region 111.

Note that the wiring layers 110a and 110b and the gate electrode layer 106 which are electrically connected to the thin film transistor 115 are made of indium tin oxide (ITO), IZO (indium zinc oxide) in which indium oxide is mixed with indium oxide, indium oxide. Conductive material mixed with silicon oxide (SiO ₂ ), organic indium, organic tin, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide Or tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel ( Ni), titanium (Ti), platinum (Pt), It can be selected from metals such as aluminum (Al), copper (Cu), silver (Ag), alloys thereof, or metal nitrides thereof.

Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed.

A method for manufacturing the semiconductor device of this embodiment mode illustrated in FIGS. 1A to 1C will be described in detail with reference to FIGS.

Over the substrate 100 having an insulating surface, insulating layers 101a and 101b which are base films are formed as base films. The base film may be a single layer or a laminated structure of two layers or three layers.

The material of the base film is an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide, acrylic acid, methacrylic acid and derivatives thereof, or polyimide, aromatic polyamide, polybenzimidazole. A heat resistant polymer such as siloxane resin may be used. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, melamine resins, and urethane resins may be used. Further, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The base film can be formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), a CVD method such as a plasma CVD method (Chemical Vapor Deposition), or the like. Further, a droplet discharge method, a printing method (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like can also be used.

For example, a silicon nitride oxide film is formed as the insulating layer 101a with a thickness of 10 to 200 nm (preferably 50 to 150 nm), and a silicon oxynitride film is formed as the insulating layer 101b with a plasma CVD method of 50 to 200 nm (preferably 100 to 150 nm). do it.

Next, a semiconductor film is formed over the base film. In the present invention, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser.

As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter, also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A crystalline semiconductor crystallized using energy or thermal energy can be used.

A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization.

As a method for manufacturing the crystalline semiconductor layer, various methods (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using an element that promotes crystallization such as nickel) may be used. Further, the crystallinity can be increased by crystallizing a microcrystalline semiconductor by laser irradiation. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor layer is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor layer with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor layer containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor layer is destroyed. As the heat treatment for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (also referred to as lamp annealing), or the like can be used. There are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method and an LRTA (Lamp Rapid Thermal Anneal) method as heating methods. GRTA is a method for performing heat treatment using a high-temperature gas, and LRTA is a method for performing heat treatment with lamp light.

Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element for promoting crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor layer, and heat treatment ( Crystallization may be carried out at 550 ° C. to 750 ° C. for 3 minutes to 24 hours. Elements that promote crystallization include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum. One or more types selected from (Pt), copper (Cu), and gold (Au) can be used.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

In order to remove or reduce an element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. A semiconductor layer containing a rare gas element is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing a rare gas element that has become a gettering sink is removed.

Laser irradiation can be performed by relatively scanning the laser and the semiconductor layer. In laser irradiation, a marker can be formed in order to superimpose beams with high accuracy and to control the laser irradiation start position and laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor layer.

When laser irradiation is used, a continuous wave laser beam (CW (continuous-wave) laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. This laser can be emitted by CW or pulsed oscillation. When injected at a CW, the power density 0.01 to 100 MW / cm ² of about laser (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. A pulse laser having a pulse width on the order of picoseconds or femtoseconds ( ^10-15 seconds) may be used. When a laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor layer is irradiated with the next pulse after the semiconductor layer is melted by the laser and solidified. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor layer, so that crystal grains continuously grown in the scanning direction can be obtained.

When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, the output can be greatly improved.

Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor layer. This is because laser interference can be prevented.

By irradiating the semiconductor layer with this linear beam, the entire surface of the semiconductor layer can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

The semiconductor layer may be formed to a thickness of about 10 nm to 200 nm, preferably about 10 nm to 50 nm, more preferably about 10 nm to 25 nm. Note that in the case of forming a semiconductor layer with a thickness of 50 nm or less, after forming the semiconductor layer with a thickness of 50 nm or more, a surface of the semiconductor layer is dry-etched to form a semiconductor film with a thickness of about 10 nm to 50 nm. May be. Etching gas at this time includes chlorine gas such as Cl ₂ , BCl ₃ , SiCl ₄ , fluorine gas such as CF ₄ , NF ₃ , SF ₆ , CHF ₃ , CF ₄ , or fluorine. A mixed gas obtained by appropriately adding an inert gas such as O ₂ gas, H ₂ gas, He or Ar to the system gas can be used. Before dry etching, the surface of the semiconductor layer is treated with dilute hydrofluoric acid to remove the natural oxide film formed on the surface of the semiconductor layer, and then the surface of the semiconductor layer is treated with ozone water or the like to form an oxide film on the surface of the semiconductor layer. May be formed.

By forming the semiconductor layer with a thin film having a thickness of about 50 nm or less, it is possible to reduce coating defects on the gate insulating layer formed on the surface of the semiconductor layer. In addition, the TFT can be further reduced in size by forming the semiconductor layer as a thin film. Even when the doping amount of the impurity element in the channel formation region is increased in order to reduce the threshold voltage of the TFT, it is easy to manufacture a fully depleted TFT by forming the semiconductor layer as a thin film. A TFT having a good S value and a small threshold voltage can be manufactured.

In order to control the threshold voltage of the thin film transistor, the semiconductor layer obtained in this manner is selectively doped with a small amount of impurity element (boron or phosphorus). This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization step. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

The semiconductor film is processed into a desired shape using a mask to form the semiconductor layer 103 (see FIG. 2A).

An inclination angle (taper angle) may be provided at an end portion of the semiconductor layer. The angle is preferably 45 to 95 degrees. In order to avoid the influence of the formation of a parasitic transistor having different characteristics from the central portion of the semiconductor layer 103 in this region, the inclination angle is preferably close to vertical.

Note that in this specification, the “end portion” of the semiconductor layer indicates an edge portion (edge portion) of the semiconductor layer formed in an island shape. The “side surface” of the semiconductor layer refers to the surface of the edge portion of the semiconductor layer.

The etching process may be either plasma etching (dry etching) or wet etching, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. In addition, a composition comprising an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, permeable polyimide, a compound material obtained by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer Materials and the like can also be used. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. In the case of using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent, adding a surfactant or the like.

Sidewall insulating layers 104a and 104b in contact with the side surfaces of the semiconductor layer 103 are formed (see FIG. 2B). By forming the sidewall insulating layers 104 a and 104 b in contact with the side surfaces of the semiconductor layer 103, the coverage of the gate insulating layer at the end portion of the semiconductor layer 103 can be improved. Therefore, defects due to poor coverage of the gate insulating layer at the end portion of the semiconductor layer 103, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, or the like can be prevented.

The sidewall insulating layers 104a and 104b can be formed in a self-aligned manner by forming a semiconductor layer, depositing a silicon oxide film or a silicon nitride film, and processing the film by anisotropic etching.

Further, the sidewall insulating layers 104a and 104b can be selectively insulated by oxidizing an end portion of the semiconductor layer 103. The oxidation treatment can be performed by plasma treatment in an atmosphere containing oxygen. Alternatively, the surface may be oxidized (also referred to as wet oxidation) using an aqueous solution. Plasma treatment may be performed after introducing a halogen such as fluorine or chlorine into the semiconductor layer side end portion before the plasma treatment. When halogen is added, the oxidation rate is high, so that the oxidation proceeds preferentially, and a thick insulating layer can be formed at the semiconductor layer side end.

By sufficiently covering the end portion of the semiconductor layer 103 with the gate insulating layer, preferably by increasing the thickness of the region in contact with the side surface of the semiconductor layer 103, the electric field applied to the end portion of the semiconductor layer 103 can be reduced. It is possible to prevent the occurrence of leakage current.

Therefore, when the present invention is used, the level difference due to the end portion of the semiconductor layer is reduced, and the coverage of the gate insulating layer is improved. Therefore, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode layer and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device. . Therefore, further miniaturization and high precision can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

The oxide film over the semiconductor layer is removed, and a gate insulating layer 120 that covers the semiconductor layer 103 is formed.

The gate insulating layer 120 may be formed using silicon oxide or a stacked structure of silicon oxide and silicon nitride. The gate insulating layer 120 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, or may be formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because a gate insulating layer formed by oxidizing or nitriding a semiconductor layer by plasma treatment is dense, has high withstand voltage, and is excellent in reliability.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating film is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

In the case of oxidizing the surface of the semiconductor layer by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) In an atmosphere containing at least one) or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas. In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used.

Note that the plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating layer, and a conductive layer. In these processes, a gas to be supplied may be selected according to the purpose.

The semiconductor layer may be oxidized or nitrided as follows. First, the processing chamber is evacuated and a plasma processing gas containing oxygen or nitrogen is introduced from a gas supply unit. The substrate is heated to 100 ° C. to 550 ° C. at room temperature or by a temperature controller.

Next, a microwave is supplied from the microwave supply unit to the antenna. Then, plasma is generated by introducing the microwave from the antenna through the dielectric plate into the processing chamber. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas. In this method, active radicals excited by plasma can be effectively used to perform oxidation, nitridation, or simultaneous oxidation and nitridation by solid phase reaction at a low temperature of 500 ° C. or lower.

An example of a suitable gate insulating layer formed by plasma treatment is that a semiconductor layer is formed with a thickness of 3 nm to 6 nm by plasma treatment under an oxidizing atmosphere, and then the surface of the silicon oxide layer under a nitrogen atmosphere. This is a laminated structure in which a silicon nitride layer is formed by nitriding. By oxidizing the surface of a silicon layer as a typical example of the semiconductor layer by plasma treatment, a dense oxide film without distortion at the interface can be formed. Further, the oxide film can be further densified by nitriding the oxide film by plasma treatment to form a nitride layer by replacing oxygen in the surface layer portion with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In any case, heat generated at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or lower is used by using the solid phase oxidation treatment or solid phase nitridation treatment by plasma treatment as described above. An insulating layer equivalent to the oxide film can be obtained. That is, a highly reliable film can be formed as the gate insulating layer of the transistor.

Alternatively, a high dielectric constant material may be used for the gate insulating layer 120. By using a high dielectric constant material for the gate insulating layer 120, gate leakage current can be reduced. As the high dielectric constant material, zirconium dioxide, hafnium oxide, titanium dioxide, tantalum pentoxide or the like can be used. Alternatively, the silicon oxide layer may be formed by solid phase oxidation by plasma treatment.

As a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region by using a GRTA method, an LRTA method, or the like and forming a thermal oxide film. . Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film.

Next, a conductive film with a thickness of 100 to 500 nm used as a gate electrode layer is formed over the gate insulating layer 120. The conductive film can be formed by a technique such as sputtering, vapor deposition, or CVD. The conductive film is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or the above What is necessary is just to form with the alloy material or compound material which has an element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the conductive film. Alternatively, a multilayer structure may be used, for example, a two-layer structure, for example, a tungsten film with a thickness of 50 nm as the first conductive film, an aluminum-silicon alloy (Al—Si) film with a thickness of 500 nm as the second conductive film, As the conductive film, a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked may be used. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.

Next, a resist mask is formed by photolithography, the conductive film is processed into a desired shape, and the gate electrode layer 106 is formed (see FIG. 2C). ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to substrate-side electrode layer, substrate-side electrode temperature, etc.) By appropriately adjusting, the first gate electrode layer and the second gate electrode layer can be etched to have a desired tapered shape. Further, the taper shape can control the angle and the like depending on the shape of the mask. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., a fluorine-based gas typified by CF ₄ , SF _6, NF _3, etc., or O ₂ is appropriately used. be able to.

In this embodiment, an example in which the gate electrode layer is formed to have a vertical side surface is described; however, the present invention is not limited thereto, and both the first gate electrode layer and the second gate electrode layer have a tapered shape. Alternatively, only one of the gate electrode layers may have a tapered shape, and the other may have a vertical side surface by anisotropic etching. The taper angle may also be different between the stacked gate electrode layers, or may be the same. By having a tapered shape, the coverage of a film stacked thereon is improved and defects are reduced, so that reliability is improved.

The gate insulating layer 120 may be slightly etched and a film thickness may be reduced (so-called film reduction) by an etching process when forming the gate electrode layer.

Next, using the gate electrode layer 106 as a mask, an impurity element 121 imparting one conductivity type is added to form impurity regions 112a and 112b having one conductivity type which are source regions or drain regions. In addition, a channel formation region 111 is formed in the semiconductor layer 103 (see FIG. 2D). Although the impurity element imparting one conductivity type is an impurity element imparting n-type conductivity (for example, phosphorus (P) or arsenic (As)), an impurity element imparting p-type conductivity (for example, boron (B) or aluminum) (Al) or gallium (Ga) or the like. In this embodiment mode, phosphorus (P) which is an impurity element imparting n-type conductivity is used as the impurity element imparting one conductivity type. In this embodiment mode, phosphine (PH ₃ ) is used as a doping gas containing an impurity element. Here, an impurity element imparting one conductivity type is included in the impurity regions 112a and 112b having one conductivity type, which are source regions or drain regions, at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. Add to.

In this embodiment, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region. In FIG. 3, hatching and white background (or dotted hatching) are shown in the impurity region, but this does not indicate that no impurity element is added to the white background (or dotted hatching) part. This is because it is possible to intuitively understand that the concentration distribution of the impurity element in this region reflects the mask and doping conditions. This also applies to other drawings in this specification.

The impurity regions 112a and 112b having one conductivity type function as a source region or a drain region.

In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

Sidewall insulating layers 107 a and 107 b having a sidewall structure are formed on side surfaces of the gate electrode layer 106. The sidewall insulating layers 107a and 107b are formed by forming an insulating layer covering the gate insulating layer 120 and the gate electrode layer 106, and then processing this by anisotropic etching using a RIE (Reactive ion etching) method. The sidewall insulating layers 107a and 107b having a sidewall structure may be formed in a self-aligned manner on the sidewalls of the gate electrode layer 106. Here, there is no particular limitation on the insulating layer, and the insulating layer may be silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Orso-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, or sputtering.

Further, in this embodiment, when the insulating layer is etched, the insulating layer on the gate electrode layer is removed to expose the gate electrode layer, but the side wall insulating layer is formed so as to leave the insulating layer on the gate electrode layer. 107a and 107b may be formed. In this embodiment, the insulating film 108 is formed as a protective film over the gate electrode layer in a later step. By protecting the gate electrode layer in this way, it is possible to prevent the gate electrode layer from being reduced during etching. Further, when silicide is formed in the source and drain regions, the metal film and the gate electrode layer are not in contact with each other because the metal film formed during the silicide formation is not in contact with the gate electrode layer. However, defects such as chemical reaction and diffusion can be prevented. The etching method may be a dry etching method or a wet etching method, and various etching methods can be used. In this embodiment mode, a dry etching method is used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can.

The gate insulating layer 120 is etched using the sidewall insulating layers 107a and 107b and the gate electrode layer 106 as a mask to expose the source region and the drain region of the semiconductor layer 103. The gate insulating layer 120 is selectively etched to be the gate insulating layer 105 (see FIG. 2E).

A conductive film 122 is formed over the semiconductor layer 103 and the sidewall insulating layers 107a and 107b (see FIG. 3A). As a material of the conductive film 122, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), tantalum (Ta), vanadium ( A film containing V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like is formed. Here, a nickel film is formed by a sputtering method.

Next, silicide 113a and 113b are formed by reacting the conductive film 122 with silicon in the exposed semiconductor layers of the source and drain regions by heat treatment, GRTA method, LRTA method, or the like. Further, silicide may be formed by laser irradiation or light irradiation with a lamp. After that, the conductive film 766 that has not reacted with the semiconductor layer is removed.

Next, an interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. In this embodiment, a stacked structure of the insulating film 108 containing hydrogen and the insulating layer 109 is used (see FIG. 3C). The insulating film 108 and the insulating layer 109 may be a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, or a silicon oxide film formed by sputtering or plasma CVD. You may use as a laminated structure more than a layer.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 108 which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour.

As the insulating film 108 and the insulating layer 109, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) or aluminum oxide whose nitrogen content is higher than oxygen content, diamond like carbon (DLC) A nitrogen-containing carbon film (CN) can be formed of a material selected from substances including other inorganic insulating materials. A siloxane resin may also be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, or polysilazane can be used. A coating film formed by a coating method with good flatness may be used.

For the insulating film 108 and the insulating layer 109, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The insulating film 108 and the insulating layer 109 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used.

Next, contact holes (openings) reaching the semiconductor layers are formed in the insulating film 108 and the insulating layer 109 using a mask made of a resist. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. The insulating film 108 and the insulating layer 109 are removed by etching, and openings reaching the silicides 113a and 113b provided in the source region or the drain region are formed. Etching may be wet etching or dry etching, or both may be used. As an etchant for wet etching, a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride is preferably used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used.

A conductive film is formed so as to cover the opening, and the conductive layers are etched to form wiring layers 110a and 110b functioning as source or drain electrode layers that are electrically connected to a part of each source region or drain region, respectively. Form. The wiring layer can be formed by forming a conductive film by a PVD method, a CVD method, a vapor deposition method or the like and then etching it into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the wiring layer is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, and other metals, and Si, Ge, Alternatively, an alloy thereof or a nitride thereof is used. Moreover, it is good also as these laminated structures. In this embodiment, titanium (Ti) is formed to a thickness of 60 nm, a titanium nitride film is formed to a thickness of 40 nm, aluminum is formed to a thickness of 700 nm, and titanium (Ti) is formed to a thickness of 200 nm to form a stacked structure. Process into the desired shape.

Through the above steps, a semiconductor device including the thin film transistor 115 can be manufactured (see FIG. 4C).

Therefore, by using the present invention, a semiconductor device with low power consumption and high reliability can be provided.

(Embodiment 2)
An object of the present embodiment is to provide a higher reliability by reducing power consumption, preventing a short circuit between the gate electrode layer and the semiconductor layer due to a poor coating of the gate insulating layer, a leakage current, and the like. A CMOS (Complementary Metal Oxide Semiconductor) as an example of a semiconductor device will be described with reference to FIGS. Note that repeated description of the same portions as those in Embodiment 1 or portions having similar functions is omitted.

Insulating layers 201a and 201b are formed as base films over the substrate 200 having an insulating surface. The base film may be a single layer or a laminated structure of two layers or three layers.

The material of the base film is an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide, acrylic acid, methacrylic acid and derivatives thereof, or polyimide, aromatic polyamide, polybenzimidazole. A heat resistant polymer such as siloxane resin may be used. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, melamine resins, and urethane resins may be used. Further, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The base film can be formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), a CVD method such as a plasma CVD method (Chemical Vapor Deposition), or the like. Further, a droplet discharge method, a printing method (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like can also be used.

For example, a silicon nitride oxide film is formed as the insulating layer 201a with a thickness of 10 to 200 nm (preferably 50 to 150 nm), and a silicon oxynitride film is formed as the insulating layer 201b with a plasma CVD method of 50 to 200 nm (preferably 100 to 150 nm). do it.

Next, a semiconductor film is formed over the base film. In the present invention, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser. The semiconductor layers 203a and 203b are formed by processing the semiconductor film into a desired shape.

The semiconductor layer may be formed to a thickness of about 10 nm to 200 nm, preferably about 10 nm to 50 nm, more preferably about 10 nm to 25 nm. Note that in the case of forming a semiconductor layer with a thickness of 50 nm or less, after forming the semiconductor layer with a thickness of 50 nm or more, a surface of the semiconductor layer is dry-etched to form a semiconductor film with a thickness of about 10 nm to 50 nm. May be. Etching gas at this time includes chlorine gas such as Cl ₂ , BCl ₃ , SiCl ₄ , fluorine gas such as CF ₄ , NF ₃ , SF ₆ , CHF ₃ , CF ₄ , or fluorine. A mixed gas obtained by appropriately adding an inert gas such as O ₂ gas, H ₂ gas, He or Ar to the system gas can be used. Before dry etching, the surface of the semiconductor layer is treated with dilute hydrofluoric acid to remove the natural oxide film formed on the surface of the semiconductor layer, and then the surface of the semiconductor layer is treated with ozone water to form an oxide film on the surface of the semiconductor layer. May be formed.

By forming the semiconductor layer with a thin film having a thickness of about 50 nm or less, it is possible to reduce coating defects on the gate insulating layer formed on the surface of the semiconductor layer. In addition, the TFT can be further reduced in size by forming the semiconductor layer as a thin film. Even when the doping amount of the impurity element in the channel formation region is increased in order to reduce the threshold voltage of the TFT, it is easy to manufacture a fully depleted TFT by forming the semiconductor layer as a thin film. A TFT having a good S value and a small threshold voltage can be manufactured.

In order to control the threshold voltage of the thin film transistor, the semiconductor layer obtained in this manner is selectively doped with a small amount of impurity element (boron or phosphorus). This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization step. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

The etching process may be either plasma etching (dry etching) or wet etching, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

In order to form a sidewall insulating layer that covers the side surface of the semiconductor layer, an insulating layer 205 is formed over the semiconductor layers 203a and 203b (see FIG. 6A). The sidewall insulating layer can be formed in a self-aligned manner by forming the semiconductor layers 203a and 203b, and then depositing an insulating layer 205 such as a silicon oxide film or a silicon nitride film and processing it by anisotropic etching.

The insulating layer 205 is processed by anisotropic etching to form sidewall insulating layers 206a to 206d in contact with the side surfaces of the semiconductor layers 203a and 203b (see FIG. 6B). By forming the sidewall insulating layers 206a to 206d in contact with the side surfaces of the semiconductor layers 203a and 203b, the coverage of the gate insulating layer at the end portions of the semiconductor layers 203a and 203b can be improved. Therefore, defects due to the poor coverage of the gate insulating layer at the end portions of the semiconductor layers 203a and 203b, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, and the like can be prevented.

The sidewall insulating layers 206a to 206d can also be selectively insulated by oxidizing the end portions of the semiconductor layers 203a and 203b. The oxidation treatment can be performed by plasma treatment in an atmosphere containing oxygen. Alternatively, the surface may be oxidized (also referred to as wet oxidation) using an aqueous solution. Plasma treatment may be performed after introducing a halogen such as fluorine or chlorine into the semiconductor layer side end portion before the plasma treatment. When halogen is added, the oxidation rate is high, so that the oxidation proceeds preferentially, and a thick insulating layer can be formed at the semiconductor layer side end.

An electric field applied to the end portions of the semiconductor layers 203a and 203b by sufficiently covering the end portions of the semiconductor layers 203a and 203b with the gate insulating layer, preferably by increasing the thickness of a region in contact with the side surfaces of the semiconductor layers 203a and 203b. Can be mitigated, and the occurrence of leakage current and the like can be prevented.

Therefore, when the present invention is used, the level difference due to the end portion of the semiconductor layer is reduced, and the coverage of the gate insulating layer is improved. Therefore, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode layer and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device. . Therefore, further miniaturization and high precision can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

The oxide film over the semiconductor layer is removed, and a gate insulating layer 209 covering the semiconductor layers 203a and 203b is formed.

The gate insulating layer 209 may be formed using silicon oxide or a stacked structure of silicon oxide and silicon nitride. The gate insulating layer 120 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, or may be formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because a gate insulating layer formed by oxidizing or nitriding a semiconductor layer by plasma treatment is dense, has high withstand voltage, and is excellent in reliability.

By oxidizing the surface of a silicon layer as a typical example of the semiconductor layer by plasma treatment, a dense oxide film without distortion at the interface can be formed. Further, the oxide film can be further densified by nitriding the oxide film by plasma treatment to form a nitride layer by replacing oxygen in the surface layer portion with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In any case, heat generated at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or lower is used by using the solid phase oxidation treatment or solid phase nitridation treatment by plasma treatment as described above. An insulating layer equivalent to the oxide film can be obtained. That is, a highly reliable film can be formed as the gate insulating layer of the transistor.

Alternatively, a high dielectric constant material may be used for the gate insulating layer 209. By using a high dielectric constant material for the gate insulating layer 209, gate leakage current can be reduced. As the high dielectric constant material, zirconium dioxide, hafnium oxide, titanium dioxide, tantalum pentoxide or the like can be used. Alternatively, the silicon oxide layer may be formed by solid phase oxidation by plasma treatment.

A first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer 209. The first conductive film and the second conductive film can be formed by a technique such as sputtering, vapor deposition, or CVD. The first conductive film and the second conductive film are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd ), Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. The structure is not limited to a two-layer structure. For example, a tungsten film with a thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film with a thickness of 500 nm is used as the second conductive film, The conductive film may have a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment mode, tantalum nitride (TaN) is formed with a thickness of 30 nm as the first conductive film, and tungsten (W) is formed with a thickness of 370 nm as the second conductive film.

Next, a resist mask is formed using a photolithography method, the first conductive film and the second conductive film are processed into desired shapes, and the first gate electrode layer 110 and the first gate electrode layer are processed. 207a, the first gate electrode layer 207b, the second gate electrode layer 208a, and the second gate electrode layer 207b are formed (see FIG. 6C). ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to substrate-side electrode layer, substrate-side electrode temperature, etc.) By appropriately adjusting, the first gate electrode layer and the second gate electrode layer can be etched to have a desired tapered shape. Further, the taper shape can control the angle and the like depending on the shape of the mask. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., a fluorine-based gas typified by CF ₄ , SF _6, NF _3, etc., or O ₂ is appropriately used. be able to.

In this embodiment, an example in which the first gate electrode layer and the second gate electrode layer are formed to have vertical side surfaces is described; however, the present invention is not limited thereto, and the first gate electrode layer and the second gate electrode layer are formed. Both of the gate electrode layers may have a tapered shape, or only one of the gate electrode layers may have a tapered shape, and the other may have a vertical side surface by anisotropic etching. Good. The taper angle may also be different between the stacked gate electrode layers, or may be the same. By having a tapered shape, the coverage of a film stacked thereon is improved and defects are reduced, so that reliability is improved. In addition, the first electrode layer and the second electrode layer to be stacked may have different shapes, and the end portions thereof may not match.

The gate insulating layer 209 may be slightly etched due to an etching process when forming the gate electrode layer, and the film thickness may be reduced (so-called film reduction).

Next, an impurity element 210 imparting n-type conductivity is added using the first gate electrode layers 207a and 207b and the second gate electrode layers 208a and 208b as masks, and first n-type impurity regions 212a and 212b, 212c and 212d are formed (see FIG. 6D). In this embodiment mode, phosphine (PH ₃ ) is used as a doping gas containing an impurity element. Here, the first n-type impurity regions 212a, 212b, 212c, and 212d are added so that the impurity element imparting n-type is contained at a concentration of about 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

Since the semiconductor layer 203b is a p-type thin film transistor, the semiconductor layer 203b may be covered with a mask without adding the impurity element 210 imparting n-type conductivity. In this embodiment, the first n-type impurity regions 212c and 212d are formed in a p-type by adding an impurity element imparting p-type at a higher concentration than the impurity element concentration imparting added n-type in a later step. Invert to impurity region.

Next, a mask 214 that covers the semiconductor layer 203a is formed. An impurity element 213 imparting p-type conductivity is added using the mask 214, the first gate electrode layer 207b, and the second gate electrode layer 208b as masks, and the first p-type impurity region 215a and the first p-type impurity region 215b are added. Form. In this embodiment, since boron (B) is used as the impurity element, diborane (B ₂ H ₆ ) or the like is used as the doping gas containing the impurity element.

The mask 214 is removed, and sidewall insulating layers 216a to 216d having a sidewall structure are formed on side surfaces of the first gate electrode layers 207a and 207b and the second gate electrode layers 208a and 208b. The sidewall insulating layers 216a to 216d are formed by forming an insulating layer that covers the first gate electrode layers 207a and 207b and the second gate electrode layers 208a and 208b, and then forming the insulating layers using an RIE (Reactive Ion Etching) method. Sidewall insulating layers 216a to 216d having a sidewall structure are formed in a self-aligned manner on the sidewalls of the first gate electrode layers 207a and 207b and the second gate electrode layers 208a and 208b. That's fine. Here, there is no particular limitation on the insulating layer, and the insulating layer may be silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Orso-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, or sputtering.

Further, in this embodiment, when the insulating layer is etched, the insulating layer on the gate electrode layer is removed to expose the gate electrode layer, but the side wall insulating layer is formed so as to leave the insulating layer on the gate electrode layer. 216a to 216db may be formed. In this embodiment, an insulating film 227 is formed as a protective film over the gate electrode layer in a later step. By protecting the gate electrode layer in this way, it is possible to prevent the gate electrode layer from being reduced during etching. Further, when silicide is formed in the source and drain regions, the metal film and the gate electrode layer are not in contact with each other because the metal film formed during the silicide formation is not in contact with the gate electrode layer. However, defects such as chemical reaction and diffusion can be prevented. The etching method may be a dry etching method or a wet etching method, and various etching methods can be used. In this embodiment mode, a dry etching method is used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can.

Using the sidewall insulating layers 216a to 216d, the first gate electrode layers 207a and 207b, and the second gate electrode layers 208a and 208b as masks, the gate insulating layer 209 is etched to expose the source and drain regions of the semiconductor layers 203a and 203b. . The gate insulating layer 209 is selectively etched to be gate insulating layers 217a and 217b (see FIG. 7B).

Next, a mask 219 that covers the semiconductor layer 203b is formed. An impurity element 218 imparting n-type conductivity is added using the mask 219, the first gate electrode layer 207a, the second gate electrode layer 207b, and the sidewall insulating layers 216a and 216b as masks, and second n-type impurity regions 220a and 220b are added. Third n-type impurity regions 231a and 231b are formed. In this embodiment mode, PH ₃ is used as a doping gas containing an impurity element. Here, the second n-type impurity regions 220a and 220b are added so that the impurity element imparting n-type is included at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . In addition, a channel formation region 233 is formed in the semiconductor layer 203a (see FIG. 7C).

The second n-type impurity region 220a and the second n-type impurity region 220b are high-concentration n-type impurity regions and function as a source and a drain. On the other hand, the third n-type impurity regions 231a and 231b are low-concentration impurity regions and become LDD (Lightly Doped Drain) regions. Since the third n-type impurity regions 231a and 231b are formed in the Loff region that is not covered with the first gate electrode layer 207a and the second gate electrode layer 208a, there is an effect of reducing off-state current. As a result, a semiconductor device with higher reliability and lower power consumption can be manufactured.

The mask 219 is removed, and a mask 222 that covers the semiconductor layer 203a is formed. Using the mask 222, the first gate electrode layer 207b, the second gate electrode layer 208b, the sidewall insulating layers 216c and 216d as masks, an impurity element 221 imparting p-type conductivity is added, and second p-type impurity regions 223a, 223b and third p-type impurity regions 232a and 232b are formed.

The second p-type impurity regions 223a and 223b and the third p-type impurity regions 232a and 232b are doped with an impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment, the third p-type impurity regions 232a and 232b are formed to have a lower concentration than the second p-type impurity regions 223a and 223b in a self-aligned manner by the sidewall insulating layers 216c and 216d. In addition, a channel formation region 234 is formed in the semiconductor layer 203b (see FIG. 7D).

The second p-type impurity regions 223a and 223b are high-concentration p-type impurity regions and function as a source and a drain. On the other hand, the third p-type impurity regions 232a and 232b are low-concentration impurity regions and become LDD (Lightly Doped Drain) regions. Since the third p-type impurity regions 232a and 232b are formed in the Loff region that is not covered with the first gate electrode layer 207b and the second gate electrode layer 208b, there is an effect of reducing off-state current. As a result, a semiconductor device with higher reliability and lower power consumption can be manufactured.

The mask 222 may be removed, and heat treatment, intense light irradiation, or laser light irradiation may be performed in order to activate the impurity element. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

A conductive film 224 is formed over the semiconductor layers 203a and 203b and the sidewall insulating layers 216a to 216d (see FIG. 8A). As a material for the conductive film 224, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), tantalum (Ta), vanadium ( A film containing V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like is formed. Here, a nickel film is formed by a sputtering method.

Next, the silicon in the exposed semiconductor layer of the source and drain regions and the conductive film 224 are reacted with each other by heat treatment, a GRTA method, an LRTA method, or the like to form silicides 225a to 225d (FIG. 8B )reference.). Further, silicide may be formed by laser irradiation or light irradiation with a lamp. Thereafter, the conductive film 224 that has not reacted with the semiconductor layer is removed. In this embodiment mode, the silicides 225a to 225d are formed on the surfaces of the second n-type impurity regions 220a and 220b and the second p-type impurity regions 223a and 223b which are the source region and the drain region. Silicide may be formed over the entire region of the second n-type impurity regions 220a and 220b and the second p-type impurity regions 223a and 223b. Silicide can be controlled by the thickness of the conductive film and the heating conditions (temperature, time).

In the present invention, since the sidewall insulating layers 216a to 216d are provided on the side surfaces of the semiconductor layers 203a and 203b, the side surfaces of the semiconductor layers 203a and 203b are not in contact with the conductive film 224. Therefore, the side surfaces of the semiconductor layers 203a and 203b can be prevented from being etched when the conductive film that has not reacted is removed. Accordingly, it is possible to prevent defects due to the poor coverage of the gate insulating layer at the end portions of the semiconductor layers 203a and 203b, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, and the like.

With the silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Furthermore, since operation at a low voltage is possible, power consumption can be reduced.

Next, an interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. In this embodiment, a stacked structure of an insulating film 227 containing hydrogen which serves as a protective film and an insulating layer 228 is used (see FIG. 8C). The insulating film 227 and the insulating layer 228 may be a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, or a silicon oxide film formed by a sputtering method or plasma CVD. You may use as a laminated structure more than a layer.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 227 which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour.

In addition, as the insulating film 227 and the insulating layer 228, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) or aluminum oxide in which the nitrogen content is higher than the oxygen content, diamond like carbon (DLC) A nitrogen-containing carbon film (CN) can be formed of a material selected from substances including other inorganic insulating materials. A siloxane resin may also be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, or polysilazane can be used. A coating film formed by a coating method with good flatness may be used.

As the insulating film 227 and the insulating layer 228, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The insulating film 227 and the insulating layer 228 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used.

Next, contact holes (openings) reaching the semiconductor layer are formed in the insulating film 227 and the insulating layer 228 using a mask made of a resist. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. The insulating film 227 and the insulating layer 228 are removed by etching, and openings reaching the silicides 225a and 225b and the silicides 226a and 226b provided in the source region or the drain region are formed. Etching may be wet etching or dry etching, or both may be used. As an etchant for wet etching, a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride is preferably used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used.

Wiring layers 229a and 229b functioning as a source electrode layer or a drain electrode layer which are formed so as to cover the opening and are electrically connected to a part of each source region or drain region by etching the conductive film, 229c is formed. The wiring layer can be formed by forming a conductive film by a PVD method, a CVD method, a vapor deposition method or the like and then etching it into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the wiring layer is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, and other metals, and Si, Ge, Alternatively, an alloy thereof or a nitride thereof is used. Moreover, it is good also as these laminated structures. In this embodiment, titanium (Ti) is formed to a thickness of 60 nm, a titanium nitride film is formed to a thickness of 40 nm, aluminum is formed to a thickness of 700 nm, and titanium (Ti) is formed to a thickness of 200 nm to form a stacked structure. Process into the desired shape.

Through the above process, a semiconductor device including the thin film transistor 230a which is an n-channel thin film transistor having a CMOS structure and the thin film transistor 230b which is a p-channel thin film transistor can be manufactured (see FIG. 8D). Since this embodiment mode has a CMOS structure, the thin film transistor 230a and the thin film transistor 230b are electrically connected to each other through the wiring layer 229b.

Therefore, by using the present invention, a semiconductor device with low power consumption and high reliability can be provided.
(Embodiment 3)
In this embodiment, another semiconductor device with low power consumption and high reliability is described with reference to FIGS. In this embodiment, an example in which the thin film transistor manufactured in Embodiment 1 has different silicide formation regions is described. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

A thin film transistor 315, an insulating film 308, and an insulating layer 309 are formed over a substrate 300 over which insulating layers 301a and 301b functioning as base films for the semiconductor layers are formed. The thin film transistor 315 includes a semiconductor layer and a gate insulating layer including silicided source or drain regions 313a and 313b which are impurity regions having one conductivity type, impurity regions 312a and 312b having one conductivity type, and a channel formation region 311. 305, a first gate electrode layer 306, and a second gate electrode layer 316 are included. Further, silicide is formed over the entire source or drain region 313a, 313b. Wiring layers 310a and 310b which are source or drain electrode layers connected to the source or drain regions 313a and 313b are provided, and the thin film transistor 315 is electrically connected to another semiconductor element or the like by the wiring layers 310a and 310b. (See FIG. 15).

The semiconductor layer may be formed to a thickness of about 10 nm to 200 nm, preferably about 10 nm to 50 nm, more preferably about 10 nm to 25 nm. Note that in the case of forming a semiconductor layer with a thickness of 50 nm or less, after forming the semiconductor layer with a thickness of 50 nm or more, a surface of the semiconductor layer is dry-etched to form a semiconductor film with a thickness of about 10 nm to 50 nm. May be. Etching gas at this time includes chlorine gas such as Cl ₂ , BCl ₃ , SiCl ₄ , fluorine gas such as CF ₄ , NF ₃ , SF ₆ , CHF ₃ , CF ₄ , or fluorine. A mixed gas obtained by appropriately adding an inert gas such as O ₂ gas, H ₂ gas, He or Ar to the system gas can be used. Before dry etching, the surface of the semiconductor layer is treated with dilute hydrofluoric acid to remove the natural oxide film formed on the surface of the semiconductor layer, and then the surface of the semiconductor layer is treated with ozone water or the like to form an oxide film on the surface of the semiconductor layer. May be formed.

In this embodiment mode, the semiconductor layer is formed with a thin film of about 10 nm to 25 nm. As the semiconductor layer becomes thinner, the gate insulating layer may have a thickness of 1 nm to 10 nm, more preferably about 5 nm. By using an ultra-thin semiconductor layer, it is possible to reduce coating defects on the gate insulating layer formed on the surface of the semiconductor layer. In addition, the TFT can be further reduced in size by forming the semiconductor layer as a thin film. Even when the doping amount of the impurity element in the channel formation region is increased in order to reduce the threshold voltage of the TFT, it is easy to manufacture a fully depleted TFT by forming the semiconductor layer as a thin film. A TFT having a good S value and a small threshold voltage can be manufactured.

In this embodiment mode, as shown in FIG. 15, the shapes of the first gate electrode layer 306 and the second gate electrode layer 316 are different, and the first gate electrode layer 306 and the second gate electrode layer 316 are different. And the ends do not match. The end portion of the first gate electrode layer 306 is located outside the end portion of the second gate electrode layer 316. Since the addition of the impurity element to the semiconductor layer is performed using the second gate electrode layer 316 as a mask, the semiconductor layer overlapping the region of the first gate electrode layer 306 that is not stacked with the second gate electrode layer 316 is used. Impurity regions are formed.

Accordingly, impurity regions 312 a and 312 b having one conductivity type are formed so as to partially overlap with the first gate electrode layer 306. In this manner, the Lov region in which the gate electrode layer partially covers the impurity region through the gate insulating layer can relax the electric field in the vicinity of the drain and suppress deterioration of on-current due to hot carriers. As a result, a thin film transistor capable of high speed operation can be formed.

The side surface of the semiconductor layer is covered with sidewall insulating layers 304a and 304b. By providing the sidewall insulating layers 307a and 307b in contact with the side surfaces of the semiconductor layer, the coverage of the gate insulating layer at the end portion of the semiconductor layer can be improved. Accordingly, it is possible to prevent defects due to poor coverage of the gate insulating layer at the end portion of the semiconductor layer, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of leakage current, electrostatic breakdown, and the like.

The sidewall insulating layers 304a and 304b can be formed in a self-aligned manner by depositing a silicon oxide film or a silicon nitride film after forming a semiconductor layer and processing it by anisotropic etching. Further, the sidewall insulating layers 304a and 304b can be selectively insulated by oxidizing the end portions of the semiconductor layer. The oxidation treatment can be performed by plasma treatment in an atmosphere containing oxygen. Alternatively, the surface may be oxidized (also referred to as wet oxidation) using an aqueous solution. Plasma treatment may be performed after introducing a halogen such as fluorine or chlorine into the semiconductor layer side end portion before the plasma treatment. When halogen is added, the oxidation rate is high, so that the oxidation proceeds preferentially, and a thick insulating layer can be formed at the semiconductor layer side end.

By sufficiently covering the edge of the semiconductor layer with the gate insulating layer, preferably by increasing the thickness of the region in contact with the side surface of the semiconductor layer, the electric field applied to the edge of the semiconductor layer can be reduced, and leakage current can be reduced. Can be prevented.

In addition, the side wall insulating layers 304a and 304b preferably have a lower dielectric constant than the gate insulating layer 305. By reducing the dielectric constant of the sidewall insulating layers 304a and 304b as compared with the gate insulating layer 305, it is possible to reduce the concentration of the electric field at the end portion of the semiconductor layer, particularly at the corner portion (corner portion). For example, the sidewall insulating layers 304a and 304b may be formed of a low dielectric constant material having a relative dielectric constant of 2.5 or less. As the low dielectric constant material, porous silicon oxide, carbon or fluorine-containing silicon oxide produced by a CVD method can be used. By forming the sidewall insulating layers 304a and 304b with a low dielectric constant material, an effect similar to that obtained when the film thickness is increased can be obtained. It is possible to prevent an excessive electric field from being locally applied to the gate insulating layer and to prevent insulation failure of the gate insulating layer. Accordingly, thin film transistors can be manufactured with high yield, and the reliability of a completed semiconductor device can be improved.

The semiconductor device of this embodiment can be a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented.

As the substrate 300 which is a substrate having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used.

As the insulating layers 301 a and 301 b, the gate insulating layer 305, the insulating film 308, and the insulating layer 309, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used. It may be a structure. Note that in this specification, silicon oxynitride is a substance in which the oxygen content is higher than the nitrogen content, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the nitrogen content is higher than the oxygen content, and can be said to be silicon nitride containing oxygen.

As another material for the insulating layers 301a and 301b, the gate insulating layer 305, the insulating film 308, and the insulating layer 309, aluminum nitride, aluminum oxynitride with an oxygen content higher than the nitrogen content, and nitrogen content with oxygen content It can be formed of a material selected from a material including more aluminum nitride oxide or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon, polysilazane, and other inorganic insulating materials. A material containing siloxane may be used. Note that siloxane corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The insulating layers 301a and 301b, the gate insulating layer 305, the insulating film 308, and the insulating layer 309 are formed by a CVD method (Chemical Vapor) such as a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a plasma CVD method. Deposition), a droplet discharge method that can selectively form a pattern, a printing method that can transfer or depict a pattern (a method that forms a pattern such as screen printing or offset printing), and other coating methods such as spin coating. A dipping method, a dispenser method, or the like can also be used.

As the etching process for processing into a desired shape, either plasma etching (dry etching) or wet etching may be employed. Plasma etching is suitable for processing large area substrates. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

Alternatively, the gate insulating layer 305 may be formed by performing plasma treatment on the semiconductor layer.

As a typical example of the semiconductor layer, the surface of the silicon layer is oxidized by plasma treatment, whereby a dense oxide layer without distortion at the interface can be formed. Further, the oxide layer can be further densified by nitriding the plasma layer by plasma treatment to form a nitride layer by replacing oxygen in the surface layer with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In addition, after forming a substrate, an insulating layer, an interlayer insulating layer, and other insulating layers and conductive layers forming a semiconductor device, the substrate, the insulating layer, and the interlayer are formed by performing oxidation treatment or nitriding treatment using plasma treatment. The surface of the insulating layer may be oxidized or nitrided. When a semiconductor layer or an insulating layer is oxidized or nitrided using plasma treatment, the surface of the insulating layer is modified so that the insulating layer becomes denser than an insulating layer formed by a CVD method or a sputtering method. it can. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved. The plasma treatment as described above can also be performed on a conductive layer such as a gate electrode layer, a source wiring layer, and a drain wiring layer, and the surface and the vicinity of the surface can be nitrided or oxidized.

Silicide is formed by forming a conductive film over the exposed source and drain regions of the semiconductor layer and reacting silicon in the semiconductor layer with the conductive film 766 by heat treatment, a GRTA method, an LRTA method, or the like. As the material of the conductive film, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), tantalum (Ta), vanadium (V ), Neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like. Further, silicide may be formed by laser irradiation or light irradiation with a lamp.

In the present invention, since the sidewall insulating layers 304a and 304b are provided on the side surface of the semiconductor layer, the side surface of the semiconductor layer is not in contact with the conductive film for silicide formation. Therefore, the side surface of the semiconductor layer can be prevented from being etched when the conductive film that has not reacted is removed. Accordingly, it is possible to prevent a defect due to a poor coating of the gate insulating layer at the end of the semiconductor layer, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of a leakage current, electrostatic breakdown, or the like.

With the silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Furthermore, since operation at a low voltage is possible, power consumption can be reduced.

The semiconductor layer is preferably formed using a crystalline semiconductor. For example, a semiconductor layer formed over the entire surface of the substrate can be crystallized and formed on the substrate by a sputtering method, a plasma CVD method, or a low pressure CVD method. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used.

Note that the wiring layers 310a and 310b, the first gate electrode layer 306, and the second gate electrode layer 316 are made of indium tin oxide (ITO), indium oxide mixed with zinc oxide (ZnO), indium zinc oxide (IZO), Conductive material in which silicon oxide (SiO ₂ ) is mixed with indium oxide, organic indium, organic tin, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, and titanium oxide Indium tin oxide or tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) , Nickel (Ni), titanium (Ti), platinum (Pt), aluminum It can be selected from metals such as um (Al), copper (Cu), silver (Ag), alloys thereof, or metal nitrides thereof.

Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed.

Therefore, the semiconductor device of the present invention can be a semiconductor device with low power consumption and high reliability.
(Embodiment 4)
In this embodiment, an example of a nonvolatile semiconductor memory device as a semiconductor device with low power consumption and high reliability will be described with reference to FIGS.

The nonvolatile memory element has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is characterized in that a region capable of accumulating electric charge for a long period is provided on the channel formation region. This charge accumulation region is formed on the insulating layer and is also isolated from the surroundings, so that it is also called a floating gate electrode layer. The floating gate electrode layer is also called a charge storage layer because it has a function of storing charges. In this specification, this charge accumulation region mainly including the floating gate electrode layer is referred to as a charge accumulation layer. A control gate electrode layer is further provided on the floating gate electrode layer through an insulating layer.

The so-called floating gate type nonvolatile semiconductor memory device having such a structure is operated to store and release charges in the charge storage layer by a voltage applied to the control gate electrode layer. In other words, the data is stored by taking in and out the charges held in the charge storage layer. Specifically, injection and extraction of charges from the charge storage layer are performed by applying a high voltage between the semiconductor layer in which the channel formation region is formed and the control gate electrode layer. At this time, it is said that Fowler-Nordheim type (FN type) tunnel current (NAND type) and thermal electrons (NOR type) flow through the insulating layer on the channel formation region. Thus, the insulating layer is also called a tunnel insulating layer.

FIG. 17 illustrates an example of a semiconductor device that is the nonvolatile semiconductor memory device of this embodiment.

A memory element 515 that is a nonvolatile memory element, an insulating film 508 that is an interlayer insulating layer, and an insulating film 509 are formed over a substrate 500 over which insulating layers 501a and 501b that function as base films of a semiconductor layer are formed. The memory element 515 includes a semiconductor layer including impurity regions 512a and 512b having one conductivity type, silicides 513a and 513b, and a channel formation region 511, sidewall insulating layers 504a and 504b, a first insulating layer 520, a charge storage layer 521, 2 insulating layer 505, control gate electrode layer 506, sidewall insulating layers 507a and 507b, and wiring layers 510a and 510b. (See FIG. 17).

In this embodiment mode, the impurity regions 512a and 512b and the silicides 513a and 513b include an impurity element imparting n-type conductivity (such as phosphorus (P) or arsenic (As)) as an impurity element imparting one conductivity type. The impurity regions 512a and 512b and the silicides 513a and 513b are regions functioning as a source and a drain in the memory element. A low concentration impurity region having a lower concentration than the impurity regions 512a and 512b may be provided between the impurity regions 512a and 512b and the channel formation region 511.

A combination of the sizes of the element region, the charge storage layer, and the control gate electrode layer is not limited to FIG. A capacitance stored in the second gate insulating layer between the charge storage layer and the control gate electrode layer, and a first between the charge storage layer and the semiconductor layer, depending on a combination of sizes of the element region, the charge storage layer, and the control gate electrode layer. Since the capacity stored in the insulating layer 520 can be controlled, the voltage value to be applied can also be controlled.

As the insulating films 508 and 509 which are interlayer insulating layers, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers or three layers may be used.

As other materials for the insulating films 508 and 509, aluminum nitride, aluminum oxynitride with an oxygen content higher than the nitrogen content, aluminum nitride oxide or aluminum oxide with a nitrogen content higher than the oxygen content, diamond-like carbon (DLC), nitrogen-containing carbon, polysilazane, and other materials including inorganic insulating materials can be used. A material containing siloxane may be used. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The insulating films 508 and 509 are formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), a CVD method such as a plasma CVD method (Chemical Vapor Deposition), or a liquid that can selectively form a pattern. A droplet discharge method, a printing method capable of transferring or drawing a pattern (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like can also be used.

As the etching process for processing into a desired shape, either plasma etching (dry etching) or wet etching may be employed. Plasma etching is suitable for processing large area substrates. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

The semiconductor layer is preferably formed using a crystalline semiconductor. For example, a semiconductor layer formed over the entire surface of the substrate can be crystallized and formed on the substrate by a sputtering method, a plasma CVD method, or a low pressure CVD method. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used.

A p-type impurity may be implanted into the semiconductor layer. For example, boron is used as the p-type impurity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the semiconductor element, and acts effectively when added to the channel formation region 253.

The first insulating layer 520 may be formed using silicon oxide or a stacked structure of silicon oxide and silicon nitride. The first insulating layer 254 may be formed by depositing an insulating layer by a plasma CVD method or a low pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because an insulating layer formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. Since the first insulating layer 520 is used as a tunnel insulating layer for injecting charges into the charge storage layer 521, such a strong one is preferable. The first insulating layer 520 is preferably formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. For example, when the gate length is 600 nm, the first insulating layer 254 can be formed to a thickness of 3 nm to 6 nm.

In FIG. 17, an example of a suitable first insulating layer 520 formed by plasma treatment is that a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on a semiconductor layer by plasma treatment under an oxidizing atmosphere, and then a nitrogen atmosphere. Below, a nitrogen plasma treatment layer is formed by treating the surface of the silicon oxide layer with nitriding plasma. Specifically, first, a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, a nitrogen plasma processing layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer by subsequently performing plasma processing in a nitrogen atmosphere. Note that the vicinity of the surface means a depth of approximately 0.5 nm to 1.5 nm from the surface of the silicon oxide layer. For example, by performing plasma treatment in a nitrogen atmosphere, a structure containing nitrogen at a ratio of 20 to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer is obtained.

By oxidizing the surface of a silicon layer as a typical example of the semiconductor layer by plasma treatment, a dense oxide layer without distortion at the interface can be formed. Further, the oxide layer can be further densified by nitriding the plasma layer by plasma treatment to form a nitride layer by replacing oxygen in the surface layer with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In any case, the heat formed at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or less is used by using the solid phase oxidation treatment or solid phase nitridation treatment by the plasma treatment as described above. An insulating layer equivalent to the oxide film can be obtained. That is, a highly reliable tunnel insulating layer can be formed as the tunnel insulating layer of the nonvolatile memory element.

The charge storage layer 521 is formed over the first insulating layer 520. The charge storage layer 521 may be a single layer or a stack of a plurality of layers.

The charge storage layer 521 can be a floating gate formed of a layer or particles of a semiconductor material or a conductive material. Examples of semiconductor materials include silicon and silicon germanium. When silicon is used, amorphous silicon or polysilicon can be used. Furthermore, phosphorous doped polysilicon can be used. Examples of the conductive material include an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, and an alloy film combining the elements (typically May be formed of a Mo—W alloy film, a Mo—Ta alloy film), or a silicon film imparted with conductivity. Under the conductive layer made of such a material, tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, nitride such as molybdenum nitride (MoN), tungsten silicide, titanium silicide, molybdenum silicide, etc. Alternatively, the silicide may be formed. Furthermore, a stacked structure of the above semiconductor materials, conductive materials, or a semiconductor material and a conductive material may be employed. For example, a stacked structure of a silicon layer and a germanium layer may be used.

Alternatively, the charge storage layer 521 can be formed using an insulating layer having a trap that holds charge. Typical examples of such a material include a silicon compound and a germanium compound. Examples of the silicon compound include silicon nitride, silicon oxynitride, and silicon oxynitride to which hydrogen is added. Germanium compounds include germanium nitride, germanium nitride to which oxygen is added, germanium oxide to which nitrogen is added, germanium nitride to which oxygen and hydrogen are added, germanium oxide to which nitrogen and hydrogen are added, and the like. .

The second insulating layer 505 includes a single layer of silicon oxide, silicon oxynitride (SiOxNy) (x> y), silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), aluminum oxide (AlxOy), or the like. A plurality of layers are formed by a low pressure CVD method, a plasma CVD method, or the like. Alternatively, plasma treatment may be performed on the charge storage layer 521 to form a nitride film whose surface is nitrided (for example, silicon nitride when silicon is used for the charge storage layer 521). In any case, the first insulating layer 520 and the second insulating layer 505 are formed of a nitride film or a nitrided layer on one or both sides in contact with the charge storage layer 521, so that the charge storage layer 521 Oxidation can be prevented.

The control gate electrode layer 506 is made of a metal selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or these metals as a main component. The alloy material or the compound material is preferably formed. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. In addition, the control gate electrode layer 506 may be formed using a stacked structure of one or more metal nitride layers and the above metal layer. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer, the adhesion of the metal layer can be improved and peeling can be prevented.

The wiring layers 510a and 510b are made of indium tin oxide (ITO), IZO (indium zinc oxide) in which indium oxide is mixed with zinc oxide (ZnO), conductive material in which indium oxide is mixed with silicon oxide (SiO ₂ ), organic indium , Organic tin, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, or tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or other metals or combinations thereof It can be selected from gold or its metal nitride.

In order to inject electrons into the charge storage layer, there are a method using thermal electrons and a method using FN type tunnel current. When thermoelectrons are used, a positive voltage is applied to the control gate electrode layer, and a high voltage is applied to the drain to generate thermoelectrons. Thereby, thermoelectrons can be injected into the charge storage layer. When the FN type tunnel current is used, a positive voltage is applied to the control gate electrode layer and injected from the semiconductor layer into the charge storage layer by the FN type tunnel current.

In the present invention, since the sidewall insulating layers 504a and 504b are provided on the side surface of the semiconductor layer, the side surface of the semiconductor layer is not in contact with the conductive film for silicide formation. Therefore, the side surface of the semiconductor layer can be prevented from being etched when the conductive film that has not reacted is removed. Accordingly, it is possible to prevent a defect due to a poor coating of the gate insulating layer at the end of the semiconductor layer, for example, a short circuit between the semiconductor layer and the gate electrode layer, generation of a leakage current, electrostatic breakdown, or the like.

With the silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Furthermore, since operation at a low voltage is possible, power consumption can be reduced.

Therefore, the semiconductor device of the present invention can be a semiconductor device with low power consumption and high reliability.

(Embodiment 5)
This embodiment shows an example in which an impurity element is added to a semiconductor layer in the semiconductor device described in any of Embodiments 1 to 3. Therefore, repetitive description of the same portion or a portion having a similar function is omitted. A manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS.

An insulating layer 401 is formed as a base film over the substrate 400 (see FIG. 16A).

As the substrate 400 which is a substrate having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used.

As the insulating layer 401, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers may be used.

As other materials for the insulating layer 401, aluminum nitride, aluminum oxynitride having an oxygen content higher than the nitrogen content, aluminum nitride oxide or aluminum oxide having a nitrogen content higher than the oxygen content, diamond-like carbon (DLC) ), Nitrogen-containing carbon, polysilazane, and other materials including inorganic insulating materials. A material containing siloxane may be used.

The insulating layer 401 is formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), a CVD method such as a plasma CVD method (Chemical Vapor Deposition), or a droplet discharge capable of selectively forming a pattern. It is also possible to use a method, a printing method capable of transferring or drawing a pattern (a method of forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like.

A thin film transistor is a switching element that is turned on when a specific voltage (referred to as a threshold voltage or threshold voltage) is applied to a gate electrode, and turned off at a voltage lower than that. Therefore, precise control of the threshold voltage is very important for accurate circuit operation.

However, the threshold voltage of the TFT may move (shift) to the negative side or the positive side due to unspecified factors such as the influence of mobile ions due to contamination, the work function difference around the gate of the TFT, and the influence on the interface charge.

A technique proposed as a solution for such a case is a channel doping method. In the channel doping method, an impurity element (typically P, As, B, etc.) imparting one conductivity to at least a channel formation region of a TFT is added, and the threshold voltage is intentionally shifted and controlled. Technology.

An insulating layer 403 which is a p-type impurity region is formed by adding an impurity element 402 imparting p-type conductivity as an impurity element imparting one conductivity type to the insulating layer 401 (see FIG. 16B).

The impurity element 402 can be introduced (added) by an ion implantation method or an ion doping method. The impurity element 402 is an impurity element imparting p-type conductivity, and boron (B), arsenic (As), or the like can be used. In the case where the impurity element 402 is formed by a doping method, the dose may be approximately 1 × 10 ¹³ atoms / cm ² .

A semiconductor film 404 is formed over the insulating layer 403 which is a p-type impurity region (see FIG. 16C). In this embodiment, an amorphous semiconductor film is formed as the semiconductor film 404. As the semiconductor film material, silicon is preferable. In addition, a silicon germanium semiconductor can be used, and it may be formed by a sputtering method, a plasma CVD method, or a low pressure CVD method.

Heat treatment is performed on the insulating layer 403 and the semiconductor film 404 to crystallize the semiconductor film 404. In this embodiment mode, the insulating layer 403 and the semiconductor film 404 are irradiated with laser light 405 to be crystallized. By this laser light irradiation treatment, the impurity element imparting p-type contained in the insulating layer 403 diffuses into the semiconductor film 404, so that the concentration of the impurity element imparting p-type is lower than that of the insulating layer 403. 404 becomes a semiconductor film 407 including an impurity element imparting p-type conductivity and having crystallinity (see FIG. 16D).

The concentration of the impurity element imparting p-type contained in the semiconductor film 407 may be approximately 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . The addition of the impurity element is for controlling the threshold voltage of the transistor, and effectively acts when added to the channel formation region.

In this manner, by adding an impurity element to the insulating layer that is a base film and indirectly adding the impurity element to the semiconductor film by heat treatment, it is not necessary to add the impurity element directly to the semiconductor film by doping or the like. Defects and the like generated at the time can be prevented, and the crystallinity of the semiconductor film is not affected. Further, the impurity element can be activated by heat treatment for crystallization.

By processing the crystalline semiconductor film 407 thus obtained into a desired shape, it can be used as a semiconductor layer of the semiconductor device in Embodiments 1 to 4.

Therefore, the semiconductor device of the present invention can be a semiconductor device with low power consumption and high reliability.

(Embodiment 6)
The semiconductor device according to the present invention can be applied to an integrated circuit such as a CPU (Central Processing Unit). In this embodiment, an example of a CPU to which the semiconductor device described in any of Embodiments 1 to 5 is applied is described below with reference to drawings.

The CPU 3660 shown in FIG. 9 includes an arithmetic circuit (ALU) 3601, an arithmetic circuit control circuit unit (ALU Controller) 3602, an instruction analysis unit (Instruction Decoder) 3603, an interrupt control unit (Interrupt Controller) on the substrate 3600. 3604, timing controller 3605, register 3606, register controller 3607, bus interface (bus I / F) 3608, rewritable ROM 3609, ROM interface (ROM I / F) 3620 And has mainly. The ROM 3609 and the ROM interface 3620 may be provided in separate chips. Various circuits included in the CPU 3660 can be formed using the thin film transistor described in any of Embodiments 1 to 3, a CMOS circuit in which the thin film transistor is combined, an NMOS circuit, a PMOS circuit, or the like.

Note that the CPU 3660 illustrated in FIG. 9 is merely an example in which the configuration is simplified, and an actual CPU has various configurations depending on the application. Therefore, the configuration of the CPU to which the present invention is applied is not limited to that shown in FIG.

An instruction input to the CPU 3660 via the bus interface 3608 is input to the instruction analysis unit 3603 and decoded, and then is input to the arithmetic circuit control circuit unit 3602, the interrupt control unit 3604, the register control unit 3607, and the timing control unit 3605. Entered.

The arithmetic circuit control circuit portion 3602, the interrupt control portion 3604, the register control portion 3607, and the timing control portion 3605 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control circuit portion 3602 generates a signal for controlling driving of the arithmetic circuit 3601. The interrupt control unit 3604 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the program of the CPU 3660. The register control unit 3607 generates an address of the register 3606, and reads and writes the register 3606 according to the state of the CPU.

In addition, the timing control unit 3605 generates a signal for controlling the driving timing of the arithmetic circuit 3601, the arithmetic circuit control circuit unit 3602, the instruction analysis unit 3603, the interrupt control unit 3604, and the register control unit 3607. For example, the timing control unit 3605 includes an internal clock generation unit that generates an internal clock signal CLK2 (3622) based on the reference clock signal CLK1 (3621), and supplies the clock signal CLK2 to the various circuits.

FIG. 10 illustrates a display device in which a pixel portion, a CPU, and other circuits are formed over the same substrate, a so-called system-on-panel. Over a substrate 3700, a pixel portion 3701, a scan line driver circuit 3702 for selecting a pixel included in the pixel portion 3701, and a signal line driver circuit 3703 for supplying a video signal to the selected pixel are provided. A CPU 3704 and other circuits such as a control circuit 3705 are connected to each other by wiring drawn from the scan line driver circuit 3702 and the signal line driver circuit 3703. The control circuit includes an interface. Then, a connection portion with an FPC terminal is provided at an end portion of the substrate, and exchange with an external signal is performed.

As other circuits, a video signal processing circuit, a power supply circuit, a gradation power supply circuit, a video RAM, a memory (DRAM, SRAM, PROM) and the like can be provided in addition to the control circuit 3705. These circuits may be formed by an IC chip and mounted on a substrate. Further, the scan line driver circuit 3702 and the signal line driver circuit 3703 are not necessarily formed over the same substrate. For example, only the scan line driver circuit 3702 is formed over the same substrate, and the signal line driver circuit 3703 is formed using an IC chip. May be implemented.

Note that although an example in which the semiconductor device according to the present invention is applied to a CPU has been described in this embodiment, the present invention is not particularly limited. For example, the semiconductor device according to the present invention can be applied to a pixel portion, a driver circuit portion, and the like of a display device including an organic light emitting element, an inorganic light emitting element, a liquid crystal element, or the like. In addition, by applying the present invention, a digital camera, a sound reproducing device such as a car audio, a notebook personal computer, a game machine, a portable information terminal (mobile phone, portable game machine, etc.), a home game machine, etc. It is also possible to manufacture an image reproducing device provided with a recording medium.

In the semiconductor device to which the present invention is applied, leakage current can be reduced at the end portion of the semiconductor layer overlapping with the gate electrode. In addition, since the transistor has a structure including silicide and can reduce contact resistance, signal delay and the like can be prevented. Therefore, the operating characteristics are improved, and high-speed circuit driving and low power consumption can be realized. In addition, since leakage current can be reduced, reliability can be improved.

(Embodiment 7)
In this embodiment, an example of usage of the semiconductor device described in the above embodiment is described. Specifically, application examples of a semiconductor device capable of inputting and outputting data without contact will be described below with reference to the drawings. A semiconductor device that can input and output data without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip, depending on the application.

An example of a top structure of the semiconductor device described in this embodiment will be described with reference to FIG. A semiconductor device 2180 illustrated in FIG. 12 includes a thin film integrated circuit 2131 provided with a plurality of elements such as thin film transistors included in a memory portion and a logic portion, and a conductive layer 2132 functioning as an antenna. The conductive layer 2132 functioning as an antenna is electrically connected to the thin film integrated circuit 2131. The thin film transistor according to the present invention described in any of Embodiments 1 to 3 can be applied to the thin film integrated circuit 2131.

FIGS. 12B and 12C are schematic views of the cross section of FIG. The conductive layer 2132 functioning as an antenna may be provided above the elements included in the memory portion and the logic portion. For example, the conductive layer 2132 functions as an antenna via the insulating layer 2130 above the structure described in Embodiment Mode 2. A conductive layer 2132 can be provided (see FIG. 12B). In addition, after the conductive layer 2132 functioning as an antenna is provided over the substrate 2133, the substrate 2133 and the thin film integrated circuit 2131 can be attached to each other so that the conductive layer 2132 is positioned therebetween (FIG. 12). (See (C)). In FIG. 12C, the conductive layer 2136 provided over the insulating layer 2130 and the conductive layer 2132 functioning as an antenna are electrically connected to each other through conductive particles 2134 included in the resin 2135 having adhesiveness. An example is shown.

Note that although an example in which the conductive layer 2132 functioning as an antenna is provided in a coil shape and an electromagnetic induction method or an electromagnetic coupling method is applied is described in this embodiment mode, the semiconductor device of the present invention is not limited thereto, and a microwave method is used. It is also possible to apply. In the case of a microwave method, the shape of the conductive layer 2132 functioning as an antenna may be determined as appropriate depending on the wavelength of the electromagnetic wave used.

For example, when a microwave method (for example, UHF band (860 MHz to 960 MHz band), 2.45 GHz band, or the like) is used as a signal transmission method in the semiconductor device 2180, the wavelength of an electromagnetic wave used for signal transmission is set to The shape such as the length of the conductive layer functioning as an antenna may be appropriately set in consideration. For example, the conductive layer functioning as an antenna has a linear shape (for example, a dipole antenna (see FIG. 13A)), a flat shape (for example, a patch antenna (see FIG. 13B)), or a ribbon shape (see FIG. 13). (See (C) and (D))). In addition, the shape of the conductive layer 2132 functioning as an antenna is not limited to a linear shape, and a curved shape, a meandering shape, or a combination thereof may be provided in consideration of the wavelength of electromagnetic waves.

The conductive layer 2132 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum A metal element such as (Mo) or an alloy material or compound material containing the metal element is used to form a single layer structure or a stacked structure.

For example, when the conductive layer 2132 that functions as an antenna is formed by screen printing, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins that function as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, fine particles having a particle diameter of 1 nm to 100 nm) are used as a conductive paste material, the conductive layer is cured by baking at a temperature range of 150 ° C. to 300 ° C. Can be formed. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

A semiconductor device to which the present invention is applied can achieve low power consumption. Therefore, it is effective in the case of a small semiconductor device capable of inputting / outputting data without contact as shown in this embodiment mode.

(Embodiment 8)
In this embodiment, application examples of a semiconductor device which is formed using the above-described invention and can input / output data without contact will be described below with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 14A). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control the circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND.

As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). The power supply voltage may be supplied to the type.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on a side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on a side surface of the article 3220 (FIG. 14B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by a belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 14C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized. In addition, since the semiconductor device according to the present invention can achieve low power consumption, the semiconductor device provided in the product can be downsized.

As described above, the applicable range of the semiconductor device of the present invention is so wide that the semiconductor device can be used for a wide range of electronic devices.

(Embodiment 9)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The application of the semiconductor device of the present invention is wide-ranging, and can be applied to any product that can be used for production and management by clarifying information such as the history of an object without contact. For example, banknotes, coins, securities, certificate documents, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, foods, clothing, health supplies, daily necessities, chemicals, etc. It can be provided and used in an electronic device or the like. These examples will be described with reference to FIG.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 190 including a processor circuit (see FIG. 11A). The certificate refers to a driver's license, a resident's card, and the like, and a chip 191 including a processor circuit can be provided (see FIG. 11B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 197 including a processor circuit (see FIG. 11C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a chip 193 including a processor circuit (see FIG. 11D). Books refer to books, books, and the like, and can be provided with a chip 194 including a processor circuit (see FIG. 11E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with a chip 195 including a processor circuit (see FIG. 11F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 196 including a processor circuit (see FIG. 11G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

Such a semiconductor device is provided by being attached to the surface of an article or embedded in an article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in an organic resin.

In this way, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. Further, forgery or theft can be prevented by providing a semiconductor device in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding or attaching a semiconductor device equipped with a sensor to a living creature such as livestock, it is possible to easily manage the health state such as body temperature as well as the year of birth, gender or type.

Note that this embodiment mode can be freely combined with any of Embodiment Modes 1 to 8.

6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 1 is a block diagram of a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 6A and 6B illustrate a semiconductor device of the present invention. 4A and 4B illustrate an antenna which can be applied to the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Claims (6)

Form an insulating layer to be the base film,
An impurity element imparting p-type is added to the insulating layer to be the base film,
Forming a semiconductor film on the insulating layer to be the base film;
Heat treatment is performed to crystallize the semiconductor film, and the impurity element is introduced into the semiconductor film.
An island-shaped semiconductor layer is formed by processing the semiconductor film,
A first sidewall insulating layer is formed at the end of the semiconductor layer by performing a plasma treatment after introducing halogen into the end of the semiconductor layer,
Forming a gate insulating layer covering the first sidewall insulating layer and the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions. Form an insulating layer to be the base film,
Forming a semiconductor layer on the insulating layer to be the base film;
Forming a first sidewall insulating layer at an end of the semiconductor layer;
Forming a gate insulating layer covering the first sidewall insulating layer and the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions. Form an insulating layer to be the base film,
An impurity element imparting p-type is added to the insulating layer to be the base film,
Forming a semiconductor film on the insulating layer to be the base film;
Heat treatment is performed to crystallize the semiconductor film, and the impurity element is introduced into the semiconductor film.
An island-shaped semiconductor layer is formed by processing the semiconductor film,
Forming a first sidewall insulating layer at an end of the semiconductor layer;
Forming a gate insulating layer covering the first sidewall insulating layer and the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions. Form an insulating layer to be the base film,
Forming a semiconductor layer on the insulating layer to be the base film;
A first sidewall insulating layer is formed at the end of the semiconductor layer by performing a plasma treatment after introducing halogen into the end of the semiconductor layer,
Forming a gate insulating layer covering the first sidewall insulating layer and the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions. Form an insulating layer to be the base film,
Forming a semiconductor film on the insulating layer to be the base film;
Selectively forming a mask on the semiconductor film;
An island-shaped semiconductor layer is formed by etching the semiconductor film using the mask,
By performing wet oxidation on the end of the semiconductor layer before removing the mask, a first sidewall insulating layer is formed on the end of the semiconductor layer,
Removing the mask and covering the first sidewall insulating layer and the semiconductor layer to form a gate insulating layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions. Form an insulating layer to be the base film,
Forming a semiconductor film on the insulating layer to be the base film;
Forming an insulating layer functioning as a gate insulating layer on the semiconductor film;
A gate insulating layer and an island-shaped semiconductor layer are formed by etching the insulating layer functioning as the gate insulating layer and the semiconductor film using a mask,
By removing the mask and performing plasma treatment on the exposed portion of the semiconductor layer from the surface of the gate insulating layer, the edge of the semiconductor layer and the surface of the semiconductor layer in contact with the gate insulating layer are formed. Forming a first insulating layer;
Forming a gate electrode on the gate insulating layer;
Forming a second sidewall insulating layer on the side surface of the gate electrode;
Etching the gate insulating layer using the second sidewall insulating layer and the gate electrode as a mask to expose a source region and a drain region of the semiconductor layer;
Forming a conductive film on the semiconductor layer and the second sidewall insulating layer;
Subjected to heat treatment, a method for manufacturing a semiconductor device and forming a silicide on the exposed the source region and the drain regions.

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