JP2003069025A - Semiconductor device and mounting method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof capable of suppressing leakage current in device separation of an MOSFET using an SOI substrate. SOLUTION: In the semiconductor device provided with the MOSFET formed on an SOI substrate consisting of a support substrate 1, a first insulating film 2 and a silicon film 3, the side wall of the silicon film 3 selectively formed and used for the MOSFET is formed vertically, and a nitride film 5 is formed at least on the lower part of the side wall as a second insulating film. In this structure, the polycrystalline silicon film 8 is prevented from approaching the side wall of the silicon film 3 at the upper and the lower ends thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS field effect transistor (also referred to as MOSFET in this specification).
Relates to a semiconductor device formed on an SOI substrate having a silicon-on-insulator (also referred to as SOI in this specification) layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device having a MOSFET formed on an SOI substrate, which is a semiconductor substrate having an insulating film (oxide film) and a silicon layer formed on a supporting substrate, has been developed and put into practical use.

This semiconductor device has a MOSF on an SOI substrate.
Since the ET is formed, that is, the insulating film of the SOI substrate is formed below the source region and the drain region of the MOSFET, the parasitic capacitance can be made smaller than that of the normal bulk substrate without the SOI layer. Various researches and developments have been performed because it is advantageous for speeding up each element integrated in a semiconductor device. In addition, this semiconductor device is
By using the I substrate, the lower layer of the above element serves as an insulating film, and the insulating film can be completely separated between the elements. Next, a method of manufacturing the semiconductor device and a structure thereof in each conventional example will be described with reference to the drawings.

(First Conventional Example) FIG. 11 is a schematic sectional view for explaining a method of manufacturing a semiconductor device having a MOSFET formed therein in the first conventional example. First, as shown in FIG. 3A, an SOI substrate 21 in which an oxide film 2 serving as a first insulating film and a silicon film 3 serving as an SOI layer are sequentially formed on a supporting substrate 1 is formed by a thermal oxidation method. An oxide film 4 having a thickness of about 10 nm is formed, and a nitride film 16 having a thickness of about 100 nm is further formed.

Next, as shown in FIG.
6 and the oxide film 4 are selectively patterned by forming a mask such as a resist, and then the silicon film 3 from which the nitride film 16 is removed is thermally oxidized as shown in FIG. It is converted into an oxide film 17 for element isolation. That is,
LOCOS (Local Oxidation ofS)
The insulating isolation by the ilicon) method is applied to the SOI substrate 21.

Next, as shown in FIG. 3D, the nitride film 16 and the oxide film 4 on the silicon film 3 that has escaped oxidation are removed by etching, and an impurity is ion-implanted into the silicon film 3 to be a channel region. And the like, and the gate oxide film 6 is formed by a thermal oxidation method.

Next, as shown in FIG. 1E, a polycrystalline silicon film 8 to be a gate electrode is formed by CVD (Chemical).
Al Vapor Deposition) method, followed by patterning.

Next, as shown in FIG. 2F, an oxide film 9 is formed on the side wall of the polycrystalline silicon film 8, and subsequently, an impurity atom and an oxide film 9 are not formed by an ion implantation method. An SD (source / drain) region 10 is formed by adding it inside the silicon film 3.

Then, a silicide film 11 is selectively formed on a desired region on the SD region 8 and the polycrystalline silicon film 8, and subsequently an insulating film 12 is formed, and further, the insulating film 12 is formed.
Of the MOSFE by a manufacturing method in which an opening is formed in a desired area of the substrate and a metal wiring 13 made of, for example, aluminum is formed in the opening and a predetermined wiring area.
Was producing T100.

Next, the MO manufactured by the above manufacturing method
The structure of the SFET 100 will be described with reference to the drawings. FIG. 12 shows a MOS of a semiconductor device in the first conventional example.
FIG. 3 shows a schematic diagram for explaining the structure of the FET,
(A) is a plan view and (b) is a sectional view taken along line GG. The cross-sectional view of FIG. 11 (f) shows a cross-sectional view taken along the line HH of FIG. 12 (a).

In FIG. 1, a MOSFET 100 is formed with a polycrystalline silicon film 8 serving as a gate electrode across the silicon film 3. That is, by applying the element isolation method by the LOCOS method to the SOI substrate, the MOSFET 100
When manufactured, the MOSFET 100 has a structure in which the polycrystalline silicon film 8 is formed across the silicon film 3.

By the way, when the LOCOS method is used for element isolation of the MOSFET 100, as shown in FIG. 12B, the end portion of the oxide film 17 on the silicon film side has a silicon film tip by the oxidation step of the LOCOS method. The shape becomes a so-called bird's beak, which enters the end face of 3 and becomes thinner toward the end. When the end portion of the oxide film 17 has a bird's beak shape, at the time of channel injection in a later step,
It becomes difficult for channel impurities to enter the ends of the bird's beak-shaped side of the silicon film 3, and channel impurity atoms (especially boron) are generated in a heat treatment process such as a gate oxidation process.
Are taken into the oxide film, the threshold voltage is locally reduced at the end of the silicon film 3 on the bird's beak shape side, and a leak current is generated.

In order to prevent the occurrence of the leak current, a method of introducing a channel impurity into the silicon film 3 before the oxidation by the LOCOS method can be considered.
When the silicon film 3 is oxidized by the OCOS method, channel impurities inside the silicon film 3 are taken into the oxide film 17, and the concentration of the oxide film 17 is reduced, which may cause a leak current.

As described above, in the semiconductor device of the first conventional example, when the MOSFET 100 is formed on the SOI substrate 21, the element isolation of the silicon film 3 which becomes the channel region is LO.
The COS method has a problem that the end portion of the silicon film 3 becomes thin and the impurity concentration at the end portion of the silicon film 3 is lowered, so that a leak current may occur.

Next, a semiconductor device which solves the above problem is
A second conventional example will be described. (Second Conventional Example) FIG. 13 shows a MOS in the second conventional example.
FIG. 3 is a schematic cross-sectional view for explaining the structure of a semiconductor device in which a FET is formed. In the figure, MOSFET
Reference numeral 200 denotes an oxide film 2 as a first insulating film on the supporting substrate 1.
Is formed, a silicon film 3 is formed on the oxide film 2, the side walls are vertical, a gate oxide film 6 is formed on the surface of the silicon film 3, and a gate electrode is formed so as to cover the gate oxide film 6. A polycrystalline silicon film 8 is formed, a silicide film 11 is formed on the upper surface of the polycrystalline silicon film 8, and an oxide film 9 is formed on the side wall of the polycrystalline silicon film 8.
Further, the insulating film 12 has a structure that covers the silicide film 11 and the oxide film 9.

Further, this MOSFET 200 has a LOC
Instead of element isolation by the OS method, the side wall of the silicon film 3 is vertically formed by dry etching. By doing so, the MOSFET 200 becomes the silicon film 3 generated in the MOSFET 100 of the first conventional example.
It is possible to prevent a decrease in the channel impurity concentration at the end of the.

[0017]

However, the MOS
In the FET 200, the upper end portion 18 of the silicon film 3 has a right-angled shape, and the upper end portion 18 is covered with the polycrystalline silicon film 8 serving as a gate electrode. Therefore, the electric field is concentrated on the upper end portion 18, the threshold value is locally lowered, and the leak current is generated.

As measures against the above, a method of rounding the upper end portion 18 to suppress electric field concentration, and the end of the silicon film 3 being thicker than the gate oxide film 6 as disclosed in JP-A-9-64367 and the like. A method of covering with an insulating film has been proposed. However, in order to make the corner shape of the upper end portion 18 round, it is necessary to add a step of oxidizing the corner and then etching this oxide film. Further, in order to cover the corner with a thick insulating film, a thick insulating film is used. It is necessary to add a step of forming and then etching.

On the other hand, when the silicon film 3 becomes thinner,
The oxide film 2 on the lower end portion 19 of the silicon film 3 is removed by overetching in the above-described oxidation step for rounding the corners of the upper end portion 18 of the silicon film 3 and the step of etching this oxide film. There is a case where a cavity is formed between the lower end portion 19 and the oxide film 2, and the polycrystalline silicon film 8 serving as the gate electrode covers the corner of the lower end portion 19 of the silicon film.

When such a cavity is formed, the electric field concentrates on the corner of the silicon film lower end portion 19, and a leak current is generated as shown in FIG. This figure shows the relationship between the drain current and the gate voltage of the MOSFET of the second conventional example, and the normal characteristic curve 120 shows that the drain current due to leakage does not occur at the gate voltage of 0 V, but is abnormal. In the characteristic curve 121, when the electric field is concentrated on the corner of the silicon film 3, a leak current at a gate voltage of 0 V, which is not generated in the normal characteristic curve 120, is generated.

That is, in the semiconductor device of the second conventional example, since the side wall of the silicon film 3 is formed vertically, the upper end portion 18 of the silicon film is exposed, and further the polycrystalline silicon film 8 serving as the gate electrode is formed. Since the structure covers the upper end portion, there is a problem that a leak current is likely to occur due to electric field concentration at a corner. Although a method for solving this problem has been proposed, there is a problem that an additional manufacturing process is required and the manufacturing cost becomes high.

Further, in the semiconductor device of the second conventional example, when the silicon film 3 becomes thinner, the oxide film 2 in contact with the lower end 19 of the silicon film is over-etched and the lower end 19 of the silicon film is etched.
However, there is a problem that the polycrystalline silicon film 8 serving as the gate electrode covers the lower end 19 of the silicon film, and a leak current is generated due to electric field concentration on the corner of the lower end 19.

The present invention has been proposed to solve the above problems, and provides a semiconductor device and a manufacturing method thereof capable of suppressing the generation of a leak current in element isolation of a MOSFET using an SOI substrate. With the goal

[0024]

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention comprises a support substrate and a first substrate.
A semiconductor device comprising a MOSFET formed on an SOI substrate made of an insulating film and a silicon film, comprising:
The sidewall of the silicon film selectively formed for the OSFET is vertically formed, and the second insulating film is formed at least under the sidewall.

In this way, even if the thickness of the silicon film is thin, no cavity is formed between the lower end of the silicon film and the first oxide film, so that a drain current is generated due to leakage at a gate voltage of 0V. Can be prevented.

Further, a semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the second insulating film is formed on the entire surface of the side wall. By doing this, the electric field is concentrated at the upper end of the silicon film,
It is possible to prevent the threshold value from locally decreasing and causing a leak current.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the second insulating film is formed higher than a gate insulating film formed on the silicon film. It is as a configuration. This way,
It is possible to more reliably and effectively prevent the electric field from concentrating on the upper end of the silicon film, locally lowering the threshold value, and causing a leak current.

A semiconductor device according to claim 4 of the present invention is the semiconductor device according to claim 1, wherein the MOSF
The upper end portion of the silicon film selectively formed for ET is chamfered. By doing so, it is possible to effectively suppress the electric field concentration at the end portion of the upper surface of the silicon film, and it is possible to prevent the threshold value from lowering and leak current from occurring.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the second insulating film is a nitride film. In this case, when the second insulating film is an oxide film, impurities inside the silicon film are taken into the oxide film, the concentration of the oxide film is reduced, and there is a risk that a leak current is generated. It can be avoided.

In order to achieve the above object, the method of manufacturing a semiconductor device according to claim 6 of the present invention is the method of manufacturing a supporting substrate,
A method of manufacturing a semiconductor device comprising a MOSFET formed on an SOI substrate made of an insulating film and a silicon film, comprising: forming an insulating film on a silicon film on the SOI substrate; The insulating film and the silicon film are selectively etched by anisotropic etching, a step of forming a second insulating film on the SOI substrate, and the second insulating film is anisotropically etched. A step of leaving the second insulating film at least under the side wall of the silicon film, a step of selectively etching the insulating film on the silicon film, and a gate insulating film formed on the exposed silicon film. And a step of performing.

In this way, the nitride film formed on the side wall of the silicon film protects the side wall of the silicon film until the final step, and the polycrystalline silicon film serving as the gate electrode covers the corner at the lower end of the silicon film. Therefore, it is possible to suppress the generation of leak current due to the electric field concentration at the corners.

A method of manufacturing a semiconductor device according to a seventh aspect of the present invention is the method of manufacturing a semiconductor device according to the sixth aspect, wherein the second insulating film is formed from the silicon film by anisotropic etching. Is also formed, and the exposed silicon film is selectively sacrificial-oxidized by etching, and the chamfering process is performed on the upper end portion of the silicon film. With this configuration, it is possible to effectively suppress the electric field concentration at the upper end portion of the silicon film and easily perform the chamfering process for preventing the generation of the leak current.

In order to achieve the above object, the method of manufacturing a semiconductor device according to claim 8 of the present invention is directed to a support substrate, a first substrate.
A method of manufacturing a semiconductor device comprising a MOSFET formed on an SOI substrate made of an insulating film and a silicon film, comprising: forming an insulating film on a silicon film on the SOI substrate; The step of selectively etching the insulating film and the silicon film by anisotropic etching, the step of forming a second insulating film on the SOI substrate, and the step of anisotropically etching the second insulating film, A step of leaving the second insulating film on at least a lower portion of the side wall of the silicon film, and a step of forming a third insulating film having a wet etching rate substantially the same as that of the insulating film on the silicon film on the SOI substrate. And anisotropically etching the third insulating film to leave the third insulating film on the side wall of the second insulating film, and wet etching the insulating film on the silicon film. Is as a method having a step of forming a gate insulating film on said silicon film exposed.

As described above, when the third insulating film is further formed on the side wall of the second insulating film formed on the side wall of the silicon film, the third insulating film is removed in the step of removing the insulating film on the silicon film. The film can prevent cavities due to overetching under the second insulating film.

A method for manufacturing a semiconductor device according to a ninth aspect of the present invention is the method for manufacturing a semiconductor device according to the eighth aspect, wherein when the insulating film on the silicon film is wet-etched, the third insulating film is formed. This is a method in which the film is not over-etched. By doing so, the oxide film below the end portion of the second insulating film is not etched, it is possible to prevent the formation of a cavity due to the over-etched portion below the second insulating film, and to prevent the generation of leak current. Can be prevented.

A method of manufacturing a semiconductor device according to a tenth aspect of the present invention is the method of manufacturing a semiconductor device according to the ninth aspect, wherein when the insulating film on the silicon film is wet-etched, the third insulating film is formed. The etching rate of the film
The method is slower than or equal to the etching rate of the first insulating film. By doing so, it is possible to more reliably prevent the formation of a cavity due to the over-etched portion below the second insulating film.

A method of manufacturing a semiconductor device according to claim 11 of the present invention is the method of manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the first insulating film and the silicon film are provided. This is a method in which the insulating film and the third insulating film are oxide films. By doing so, each film can be easily formed, and the insulating film on the silicon film and the third insulating film can be etched together.

In order to achieve the above object, the method of manufacturing a semiconductor device according to a twelfth aspect of the present invention comprises a MOSFET formed on an SOI substrate composed of a support substrate, a first insulating film and a silicon film. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film on a silicon film on the SOI substrate; a step of forming a sacrificial layer on the insulating film on the silicon film; A step of selectively etching the insulating film on the film and the silicon film by anisotropic etching; a step of forming a second insulating film on the SOI substrate; and an anisotropic etching of the second insulating film. Then, the step of leaving the second insulating film on the side wall of the silicon film, the insulating film on the silicon film, and the sacrificial layer, the step of selectively etching the sacrificial layer, and the step of insulating the silicon film are performed. There as a method having a step of wet etching the film, forming a gate insulating film on said silicon film exposed, the.

In this way, when anisotropically etching the second insulating film, the insulating film on the silicon film is protected by the sacrificial layer, and the insulating film on the silicon film can be thinned. Since the etching at the time of wet etching the insulating film on the silicon film can be reduced,
It is possible to reduce the size of the cavity formed under the second insulating film due to the over-etched portion and prevent problems due to over-etching.

A method of manufacturing a semiconductor device according to a thirteenth aspect of the present invention is the method of manufacturing a semiconductor device according to the twelfth aspect, wherein the sacrificial layer is a polycrystalline silicon film. In this way, the sacrificial layer can be laminated easily and at low manufacturing cost.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the thirteenth aspect, the second insulating film is thicker than the insulating film on the silicon film. It is as a method of forming. By doing so, it is possible to reliably prevent the formation of a cavity due to the over-etched portion below the second insulating film.

A method of manufacturing a semiconductor device according to a fifteenth aspect of the present invention is the method of manufacturing a semiconductor device according to any one of the sixth to fourteenth aspects, wherein the second insulating film is a nitride film. There is a way. In this case, when the second insulating film is an oxide film, impurities inside the silicon film are taken into the oxide film, the concentration of the oxide film is reduced, and there is a risk that a leak current is generated. It can be avoided.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments and application examples of the present invention will be described below with reference to the drawings. First, each embodiment of the semiconductor device and the manufacturing method thereof according to the present invention will be described.

[First Embodiment] FIG. 1 is a schematic view for explaining a first embodiment of a semiconductor device according to the present invention. (A) is a top view and (b) is AA. A cross-section of the line is shown. In the figure, the MOSF of the semiconductor device
In ET, for example, an oxide film 2 is formed as a first insulating film on a support substrate 1, and a MOSF is formed on the oxide film 2.
The silicon film 3 selectively formed for ET is formed so that the side walls are vertical. In other words, this MOSFE
T is formed on the SOI substrate 21 including the support substrate 1, the oxide film as the first insulating film, and the silicon film 3.

In the MOSFET, the gate oxide film 6 is formed on the silicon film 3, and the nitride film 5 is formed as a second insulating film on the sidewalls of the silicon film 3 and the gate oxide film 6.
A polycrystalline silicon film 8 and a silicide film 11 to be gate electrodes are formed in the upper layer, and an oxide film 9 is formed on the side wall of the polycrystalline silicon film 8 to cover the insulating film 12. is there.

Here, in the MOSFET, the nitride film 5 is formed on at least the lower part of the side wall of the silicon film 3, and by doing so, even if the film thickness of the silicon film 3 becomes thin, the silicon film 3 is formed. Since no cavity is formed between the lower end of the first oxide film 2 and the first oxide film 2, generation of drain current due to leakage can be prevented at a gate voltage of 0V.

Further, the nitride film 5 is preferably formed on the entire side wall of the silicon film 3, and in this case, the silicon film 3 is formed.
It is possible to prevent an electric field from concentrating on the upper end portion of the device, locally lowering the threshold value, and generating a leak current. Further, the nitride film 5 may be formed higher than the gate insulating film 6 formed on the silicon film 3. In this case, the electric field is concentrated on the upper end portion of the silicon film, and the threshold value is locally reduced. It is possible to more effectively prevent the decrease and the generation of the leak current.

Further, this MOSFET has a structure in which the nitride film 5 is a nitride film, and by doing so, when the second insulating film is an oxide film, the impurities inside the silicon film 3 become an oxide film. It is possible to avoid the risk that the concentration of the oxide film will be reduced and the leakage current will be generated.

The oxide film 9 formed on the side wall of the polycrystalline silicon film 8 serving as the gate electrode is not limited to the oxide film, and the side surface of the polycrystalline silicon film 8 may be covered with another material. Alternatively, the structure may be such that the side surface of the polycrystalline silicon film 8 is not covered. Further, the gate electrode is not limited to the polycrystalline silicon film 8 and may be composed of other materials, as a matter of course.

As described above, the MOSFET of this embodiment
Because the side wall of the silicon film 3 is formed vertically and the oxide film 17 (see FIG. 11F) is not in contact with the side wall of the silicon film 3, the impurity concentration generated when the LOCOS method is used. There is no decrease, and the generation of leak current is suppressed.

This MOSFET has a silicon film 3
Since the side wall of the gate electrode is covered with the nitride film 5, the side wall of the upper end portion of the silicon film 3 is not exposed. Further, since the nitride film 5 is formed higher than the gate oxide film 6, It is possible to weaken the electric field in the horizontal direction, and it is possible to suppress the leak current.

Further, this MOSFET has a silicon film 3
Since the nitride film 5 is formed on at least the lower part of the sidewall of the silicon film 3 to protect the silicon film 3, even if the oxide film 2 under the silicon film 3 is etched, the over-etched portion 7 of the oxide film 2 is not covered by the silicon film 3. Therefore, the influence of the electric field due to the polycrystalline silicon film 8 formed in the horizontal direction is reduced, and the leak current can be suppressed.

Next, a first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 2 is a schematic cross-sectional view taken along the line BB for explaining the method of manufacturing the semiconductor device according to the first embodiment. Further, FIG. 3 is a schematic flowchart for explaining the method for manufacturing a semiconductor device according to the first embodiment.

The method of manufacturing the semiconductor device according to the present embodiment uses S
In a method of manufacturing a semiconductor device including a MOSFET formed on an OI substrate, first, as shown in FIG. 2A, an oxide film as a first insulating film is first formed on a support substrate 1 made of, for example, silicon. 2 is formed to have a thickness of about 10 nm to about 10 μm, and a silicon film 3 is further formed on the oxide film 2 to have a thickness of, for example, about 5 nm to about 200 nm to manufacture an SOI substrate 21 (FIG. 3 in step S1: SOI substrate manufacturing process). This SO
The I substrate 21 is a SIMO formed by ion implantation of oxygen.
X (Separation by Implanted)
Oxygen) method or a method of forming by bonding.

Next, as shown in FIG. 2B, an oxide film 4 is formed as an insulating film on the silicon film to a thickness of about 30 nm on the SOI substrate 21 by a thermal oxidation method or a CVD method. (Step S2 in FIG. 3: step of forming insulating film on silicon film). Further, although not shown, the oxide film 4 and the silicon film 3 are selectively etched by anisotropic etching to form a MOSFET (step S3 in FIG. 3: insulating film on silicon film and silicon film). Etching step).

Next, as shown in FIG. 2C, a second layer is formed on the SOI substrate 21 etched in step S3.
The nitride film 5 as an insulating film is formed by LPCVD (low pressure CVD) so as to have a thickness of about 50 nm (FIG. 3).
In step S4: second insulating film laminating step). Here, since the second insulating film is the nitride film 5, when the second insulating film is an oxide film, impurities inside the silicon film are taken into the oxide film, and the concentration of the oxide film decreases. Therefore, it is possible to avoid the risk of leakage current being generated.

Next, RIE (Reactive Ion)
Etching) method is used to anisotropically etch the nitride film 5 so that the nitride film 5 remains at least under the sidewall of the silicon film 3 (step S in FIG. 3).
5: Second insulating film etching step). Here, preferably, as shown in FIG. 2D, it is preferable to form the nitride film 5 so as to remain on the entire sidewalls of the silicon film 3 and the oxide film 4. By doing so, the upper end portion of the silicon film 3 is formed. It is possible to prevent an electric field from concentrating on the surface of the cell, locally lowering the threshold value and causing a leak current.

Next, although not shown, the oxide film 4 is selectively etched, and channel impurities are added to the exposed silicon film 3 by the ion implantation method. Then, the oxide film 4 remaining by the above etching is removed. Etching with hydrofluoric acid (Fig. 3
Step S6: Etching process of insulating film on silicon film).

Next, as shown in FIG. 2E, a gate oxide film 6 is formed on the exposed silicon film 3 by, for example, a thermal oxidation method so as to have a thickness of about 10 nm (in FIG. 3). , Step S7: gate insulating film forming step). In the step of etching the insulating film on the silicon film (step S6), when the oxide film 4 is etched with hydrofluoric acid, the oxide film 2 exposed outside the nitride film 5 is also etched. The over-etched portion 7 is formed at the end portion of.

Next, as shown in FIG. 2F, a polycrystalline silicon film 8 is deposited as a gate electrode by the CVD method and selectively patterned by the RIE method using the photolithography technique (step in FIG. 3). S8: Gate electrode forming step). The RIE (reactive ion etching) in this step is preferably performed under the RIE condition using an etching gas containing SF ₆ , for example, whereby isotropic etching can be performed and the overetched portion 7 can be formed. The deposited polycrystalline silicon film can be completely removed.

Next, as shown in FIG. 2G, an oxide film 9 is deposited by the CVD method so as to have a thickness of, for example, about 100 nm, and then RIE is performed so that it remains on the side wall of the polycrystalline silicon film 8. (Step S9 in FIG. 3: gate electrode protective film forming step). Incidentally, when this step is carried out, the exposed gate oxide film 6 is also removed.

Next, impurity atoms are added to the silicon film 3 by the ion implantation method to form the SD region 10 (step S10 in FIG. 3: SD region forming step).

Next, a silicide film 11 such as cobalt silicide is selectively formed on the exposed silicon film 3 and polycrystalline silicon film 8, and an insulating film such as BPSG (passivation film) is further formed. 12
Is deposited to a thickness of about 500 nm, the surface is flattened by CMP, contact holes are selectively formed, and then metal wirings 13 such as aluminum are selectively formed (FIG. 3). In step S11: wiring step).

As described above, according to the method of manufacturing the semiconductor device of the present embodiment, the side wall of the silicon film 3 can be formed vertically by RIE, and the impurity concentration at the end of the silicon film caused by the separation by the LOCOS method is reduced. Since it does not occur, the leak current can be suppressed.

Further, in the step of etching the insulating film on the silicon film (step S6), the oxide film 4 is wet-etched with hydrofluoric acid, but the nitride film 5 which is not etched by this etching is self-aligned with the side wall of the silicon film 3. The side wall of the silicon film 3 can be protected by the nitride film 5 until the final step by forming the above.

Further, by forming the nitride film 5 to be thicker than the oxide film 4 (see FIG. 2C), the nitride film 5 formed by etching is formed in the lower surface direction of the silicon film 3. Since the thickness t (see FIG. 2E) is formed to be thicker than the thickness of the oxide film 4, even if the over-etched portion 7 occurs during the wet etching of the oxide film 4, the silicon film 3 is not formed.
It is possible to prevent the lower surface of the substrate from being exposed. As described above, since the polycrystalline silicon film 8 serving as the gate electrode does not cover the corners of the upper end portion and the lower end portion of the silicon film 3, it is possible to suppress the generation of leak current due to the electric field concentration at the corners.

Second Embodiment Next, the structure of the second embodiment of the semiconductor device according to the present invention will be described with reference to the drawings. FIG. 4 is a schematic diagram for explaining the structure of the semiconductor device according to the second embodiment,
(A) is a top view, (b) is a schematic sectional view taken along line C-C,
(C) has shown the schematic sectional drawing of the DD line.

In the figure, in the MOSFET of the semiconductor device of the present embodiment, for example, an oxide film 2 is formed as a first insulating film on a support substrate 1, and on this oxide film 2,
Silicon film 3a selectively formed for MOSFET
Are formed so that the side walls are vertical, and the upper end portion of the silicon film 3a is chamfered. In the present specification, “chamfering” means that an arc-shaped curved surface or slope is formed at the upper surface end of a silicon film that is normally formed at a right angle, and the corners of the upper surface end are rounded and smoothed. Processing means.

In the present embodiment, the upper end of the silicon film 3a is chamfered in an arc shape, and by doing so, electric field concentration at the upper end of the silicon film 3a is effectively suppressed. It is possible to prevent the occurrence of leak current by lowering the threshold value.

The nitride film 5a is formed on the side wall of the silicon film 3a so that the upper end of the nitride film 5a is lower than the upper surface of the silicon film 3a. Prevents oxidation of the side wall of the film 3a,
Moreover, the side wall of the silicon film 3a which is not in contact with the nitride film 5a can be sacrificed to be chamfered.

In the MOSFET, the gate oxide film 6a and the polycrystalline silicon film 8 to be the gate electrode are formed on the chamfered silicon film 3a, and the side wall of the polycrystalline silicon film 8 is oxidized. The film 9 is formed, and further the SD region 10 is selectively formed in the silicon film 3a, and the polycrystalline silicon film 8 and the SD region 1 of the silicon film 3a are formed.
0 has a silicide film 11 formed thereon, the upper layer is covered with an insulating film 12, contact holes are selectively formed in the insulating film 12, and a metal wiring 13 is formed. The other structures and operations are the same as those of the semiconductor device of the first embodiment, except for the over-etched portion described later.

As described above, in the semiconductor device of the second embodiment, since the lower end portion of the silicon film 3a is covered with the nitride film 5a, it is possible to prevent the generation of leak current,
Moreover, by chamfering the upper end portion of the silicon film 3a not covered with the nitride film 5a into an arc shape, even if the polycrystalline silicon film 8 is formed in the vicinity of the upper end portion, the leakage current due to the concentration of the electric field is reduced. Occurrence can be prevented.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
In addition, FIG. 5 is a schematic flowchart for explaining the method for manufacturing a semiconductor device according to the second embodiment.

The method of manufacturing the semiconductor device according to the present embodiment uses S
In a method of manufacturing a semiconductor device including a MOSFET formed on an OI substrate, as shown in FIG. 5, first, the SOI substrate manufacturing process of step S1 described above and step S2 are performed.
The step of forming the insulating film on the silicon film, the step of etching the insulating film on the silicon film and the silicon film in step S3, and the step of laminating the second insulating film in step S4 are performed.

Next, the nitride film 5a is anisotropically etched by the RIE method so that the nitride film 5a remains at least under the side wall of the silicon film 3a and is formed lower than the silicon film 3a (FIG. 5). In step S21: Etching step of the second insulating film).

Next, although not shown, the oxide film 4 (see FIG.
(See (d)) is selectively etched around the periphery, and then,
The upper portion of the silicon film 3a exposed by etching is sacrificial-oxidized, and an arc-shaped chamfering process is performed on the upper end portion of the silicon film 3a (step S22 in FIG. 5: silicon film chamfering process).

Here, the upper surface end portion of the silicon film 3a is the upper surface of the silicon film 3a exposed from the opening (not shown) formed around the oxide film 4, and the silicon film not covered by the nitride film 5a. By sacrificing the side wall of 3a,
It can be easily formed in an arc shape. In addition, the nitride film 5
By forming sacrificial oxidation after forming a, the nitride film 5
The side wall of the silicon film 3a in contact with a is not oxidized, and the problem that the threshold voltage of the side wall is lowered and a leak current is generated can be prevented.

Next, the step of etching the insulating film on the silicon film in step S6, the step of forming a gate insulating film in step S7, the step of forming a gate electrode in step S8, the step of forming a protective film for the gate electrode in step S9, and the step S
The SD area forming step 10 and the wiring step S11 are performed. Other steps are similar to those of the method for manufacturing the semiconductor device according to the first embodiment.

As described above, according to the method of manufacturing the semiconductor device of the second embodiment, the chamfering which effectively suppresses the electric field concentration at the upper end portion of the silicon film and prevents the threshold current from lowering and leak current from occurring. Processing can be easily performed. Further, according to this manufacturing method, the RIE of the nitride film 5a is performed.
In the process, even when the position of the upper end of the nitride film 5a cannot be controlled, the electric field concentration is effectively suppressed at the upper end of the silicon film, and the threshold value is lowered to prevent the generation of leak current. can do.

Further, according to this manufacturing method, since the nitride film 5a on the side wall of the silicon film 3a is set lower than the upper surface of the silicon film 3a, the nitride film 5a is formed on the silicon film 3a.
It is possible to obtain a structure in which there is no step difference such that the height becomes higher at the end portion of a, so that the polycrystalline silicon film 8 becomes the nitride film 5a.
It is possible to prevent such a problem that the film thickness locally changes or the film thickness of the upper silicide film 11 changes when it traverses the gate electrode, and fluctuation of the resistance value of the gate electrode can be suppressed.

Third Embodiment Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment. Further, FIG. 7 is a schematic flowchart for explaining the method for manufacturing a semiconductor device according to the third embodiment.

The method of manufacturing the semiconductor device of the present embodiment uses S
In a method of manufacturing a semiconductor device having a MOSFET formed on an OI substrate, as shown in FIG. 7, first, the SOI substrate manufacturing process of step S1 described above and step S2 are performed.
The step of forming an insulating film on a silicon film, the step of etching an insulating film on a silicon film and a silicon film in step S3, the step of laminating a second insulating film in step S4, and the step of etching a second insulating film in step S5. .

Here, the process shown in FIG.
It is the same second insulating film etching step (step S5) as the step shown in (d), and has a thickness of about 30 nm on the silicon film 3 of the SOI substrate 21 including the oxide film 2 and the silicon film 3 on the supporting substrate 1. The oxide film 4 is formed so as to form the silicon film 3 and the oxide film 4 and the nitride film 5 is formed on the side wall.
Are selectively formed.

Next, as shown in FIG. 6B, a third insulating film (oxide film 14) having substantially the same wet etching rate as the insulating film (oxide film 4) on the silicon film is formed on the SOI substrate by the CVD method. It is deposited so as to have a thickness of about 50 nm on 21 (step S31 in FIG. 7: third insulating film forming step). Here, the first insulating film, the insulating film on the silicon film, and the third insulating film may be the oxide films 2, 4, and 14. By doing so, each film can be easily formed, Further, the insulating film on the silicon film and the third insulating film can be etched together.

Next, as shown in FIG. 6C, the oxide film 1
4 is anisotropically etched by RIE so as to remain on the side wall of the nitride film 5 (step S32 in FIG. 7: third insulating film etching step).

Next, as shown in FIG. 6D, after the channel impurities are added to the silicon film 3 by the ion implantation method, the oxide film 4 is wet-etched with hydrofluoric acid (step S6 in FIG. 7, silicon: silicon). Etching process of insulating film on film). In this etching step, the oxide film 14 on the side wall of the nitride film 5 and a part of the exposed oxide film 2 are also etched together.

Next, as also shown in FIG. 6D, the gate oxide film 6 is formed by thermal oxidation, for example, to have a thickness of about 10 nm (S7 in FIG. 7: gate insulating film forming step). . In this process, the oxide film 4 is formed with hydrofluoric acid.
When etching the oxide film, the film thickness and material are set so that the time for etching and removing the oxide film 14 formed on the sidewall of the nitride film 5 is longer than the time for etching the oxide film 4. It is preferable not to perform over-etching after etching 14 and, in this case, the oxide film 2 below the end portion of the nitride film 5 is not etched, and a cavity due to the over-etched portion below the nitride film 5 is formed. Can be prevented.

Further, it is not necessary to remove all oxide film 14, and oxide film 14 may remain on the side wall of nitride film 5. In addition, the etching rate of the oxide film 2 is set to the oxide film 1
It is preferable to set the film quality to be equal to or slower than the etching rate of No. 4, and by doing so, the generation of cavities can be prevented more reliably.

Next, as shown in FIG. 6E, a polycrystalline silicon film 8 is deposited by the CVD method and selectively patterned by the RIE method using the photolithography technique (step S8 in FIG. 7: gate electrode). Forming process).

Next, as shown in FIG. 6 (f), an oxide film 9 is deposited by the CVD method so as to have a thickness of, for example, about 100 nm, and then RIE is performed to carry out the polycrystalline silicon film 8.
So as to remain on the side wall of the gate electrode (S9 in FIG. 7: gate electrode protective film forming step). By this step, the exposed gate oxide film 6 is also removed.

Next, impurity atoms are added to the silicon film 3 by the ion implantation method to form the SD region 10 (S10 in FIG. 7: SD region forming step).

Next, a silicide film 11 such as cobalt silicide is selectively formed on the exposed silicon film 3 and the polycrystalline silicon film 7, and then an insulating film 12 such as BPSG having a thickness of about 500 nm is formed. After depositing so as to have a thickness and performing CMP to planarize the surface, a contact hole is selectively formed, and then a metal wiring 13 such as aluminum is selectively formed (in FIG. 7,
S11: Wiring process).

As described above, according to the method of manufacturing the semiconductor device of the present embodiment, the oxide film 14 is further formed on the side wall of the nitride film 5 on the side wall of the silicon film 3 and the oxide film 4 is removed to the film thickness. In the step of removing the nitride film 5 by setting the film thickness to be removed at least at the same time or to be thicker than that.
It is possible to prevent the formation of cavities due to over-etching of the oxide film 2 underneath.

For example, when the oxide film 4 and the oxide film 13 have the same etching rate by hydrofluoric acid and the oxide film 4 having a thickness of about 50 nm is over-etched by about 20%, the oxide film It is necessary that the film thickness of 14 be about 60 nm or more. By doing so, it is not necessary to add isotropic conditions in the RIE process of the polycrystalline silicon film 8 in the subsequent process, and complete anisotropic RIE is possible. In addition, the gate length can be easily controlled when miniaturized, and stable MOSFET characteristics can be obtained.

In the method of manufacturing the semiconductor device according to the present embodiment, the etching rate of the oxide film 2 with hydrofluoric acid may be slower than or equal to the etching rate of the oxide film 14. By doing so, the nitride film 5 is formed. It is possible to more reliably prevent the formation of voids due to overetching of the oxide film 2 below.

Fourth Embodiment Next, a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 8 is a schematic sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment. In addition, FIG. 9 is a schematic flowchart for explaining the method for manufacturing a semiconductor device according to the fourth embodiment.

The method of manufacturing the semiconductor device of the present embodiment uses S
A method of manufacturing a semiconductor device having a MOSFET formed on an OI substrate, which comprises first forming an oxide film 2 on a support substrate 1 made of, for example, silicon from about 10 nm to about 10 μm.
Of the silicon film 3 is formed to have a thickness of, for example, about 5 nm to about 200 nm (step S1: SOI substrate manufacturing step in FIG. 9).

Next, the oxide film 4 is formed by thermal oxidation or the CVD method so as to have a thickness of about 50 nm (step S2 in FIG. 9: insulating film forming process on silicon film), and then as a sacrifice layer. The polycrystalline silicon film 15 is deposited by the CVD method so as to have a thickness of about 100 nm (step S41 in FIG. 9: sacrificial layer forming step). Here, the sacrificial layer is preferably a polycrystalline silicon film, and in this case, the sacrificial layer can be stacked easily and at low manufacturing cost.

Next, as shown in FIG. 8B, the polycrystalline silicon film 15, the oxide film 4 and the silicon film 3 are selectively patterned by the RIE method (step S42 in FIG. 9: sacrificial layer, silicon). Etching process of insulating film and silicon film on film).

Next, as shown in FIG. 8C, the nitride film 5 is formed.
Is deposited by LPCVD so as to have a thickness of about 50 nm (step S4 in FIG. 9: second insulating film laminating step), and then the RIE method is used to anisotropically etch the silicon film 3 and the nitride film 5. The nitride film 5 is formed so as to remain on the sidewall of the oxide film 4 (step S in FIG. 9).
5: Second insulating film etching step).

Preferably, the oxide film 14 is replaced with C
It is deposited by the VD method (step S31 in FIG. 9:
Third insulating film forming step), followed by etching by RIE so that the oxide film 14 remains on the sidewall of the nitride film 5 (step S32 in FIG. 9: third insulating film etching step). In addition, the deposited film thickness of the oxide film 14 is
It is preferable to make it thicker than this. By doing so, it is possible to reliably prevent the formation of a cavity due to the over-etched portion below the nitride film 5.

Next, as shown in FIG. 8D, the polycrystalline silicon film 15 is selectively removed by etching, and channel impurities are added to the silicon film 3 by an ion implantation method.
The oxide film 4 is etched with hydrofluoric acid (step S6 in FIG. 9: etching process of the insulating film on the silicon film), and then the gate oxide film 6 is thermally oxidized to have a thickness of, for example, about 10 nm. Forming (step S7 in FIG. 9: gate insulating film forming step). In this step, when the oxide film 4 is etched with hydrofluoric acid, the oxide film 13 on the sidewall of the nitride film 5 and the exposed oxide film 2 are also etched.

Next, as shown in FIG. 8E, a polycrystalline silicon film 8 is deposited by the CVD method and selectively patterned by the photolithography technique and the RIE method (step S9 in FIG. 9: gate electrode forming step). ).

Next, as shown in FIG. 8F, an oxide film is deposited by the CVD method so as to have a thickness of, for example, about 100 nm, and then RIE is performed to leave it on the side wall of the polycrystalline silicon film 8. (Step S9 in FIG. 9:
Step of forming gate electrode protective film). By this step, the exposed gate oxide film 6 is also removed.

Next, impurity atoms are added to the silicon film 3 by the ion implantation method to form the SD region 10 (step S10 in FIG. 9: SD region forming step).

Next, a silicide film 11 such as cobalt silicide is selectively formed on the exposed silicon film 3 and the polycrystalline silicon film 8, and then an insulating film 12 such as BPSG is formed to a thickness of about 500 nm. After that, CMP (Chemical Mechanical Polishing) is performed to planarize the surface, and then contact holes are selectively formed and metal wiring 13 such as aluminum is selectively formed (step S11 in FIG. 9). : Wiring process).

As described above, according to the method of manufacturing the semiconductor device of the fourth embodiment, the oxide film 4 on the silicon film 3 is polycrystallized during the RIE process of the nitride film 5 formed on the side wall of the silicon film 3. Since it is protected by the silicon film 14 and is not etched, the oxide film 4 can be thinned.

Therefore, in the step shown in FIG. 8D, the etching of the oxide film 4 exposing the silicon film 3 can be reduced, and the etching of the oxide film 2 can be suppressed to the minimum, that is, Since the over-etched portion can be made small, it is possible to prevent problems due to over-etching without forming the oxide film 14.

Although the present embodiment has been described including the step of forming the oxide film 14 on the side wall of the nitride film 5, the method of not forming the oxide film 14 on the side wall of the nitride film 5 described in the first embodiment. Of course, you can

[Application Example of Semiconductor Device] Next, the structure of an application example of the semiconductor device of the present invention will be described with reference to the drawings. 10A and 10B are schematic views for explaining the structure of a semiconductor device in an application example of the present invention, in which FIG. 10A is a top view, FIG. 10B is a sectional view taken along line EE, and FIG.
(C) has shown sectional drawing of the FF line.

In the figure, a semiconductor device having a MOSFET formed thereon has an insulating film such as an oxide film 2 on a supporting substrate 1.
The silicon film 3 is formed so that the end portions thereof are substantially vertical, the gate oxide film 6 is formed on the silicon film 3, and the nitride film 5 is formed on the sidewalls of the silicon film 3 and the gate oxide film 6. The upper end of the nitride film 5 is higher than the upper surface of the silicon film 3 and lower than the upper surface of the gate oxide film 6.

Further, in this semiconductor device, the polycrystalline silicon film 8 serving as the gate electrode is formed on the gate oxide film 6, and the oxide film 9 is formed on the side wall of the polycrystalline silicon film 8.
The SD region 10 is selectively formed in the silicon film 3, and the SD region 1 of the polycrystalline silicon film 8 and the silicon film 3 is further formed.
0, a silicide film 11 is formed on the insulating film 12 and the upper layer is an insulating film 12.
The contact hole is selectively formed in the insulating film 12 and the metal wiring 13 is formed.

In this semiconductor device, the upper end of the nitride film 5 is formed to be higher than the upper surface of the silicon film 3 and lower than the upper surface of the gate oxide film 6, that is, the nitride film contacting the side wall of the silicon film 3. Since 5 is set to almost the same height as the silicon film 3, the upper end and the lower end of the silicon film 3 are not covered with the polycrystalline silicon film 8 serving as the gate electrode. Unlike the semiconductor devices described in the first, third, and fourth embodiments, the nitride film 5 does not become higher than the silicon film 3 at the end portion of the silicon film 3, so the polycrystalline silicon film 8 and the silicide film 11 are formed. On the other hand, the structure has no step.

By doing so, the MOSF of the semiconductor device is
ET can suppress fluctuations in the resistance value of the gate electrode due to local changes in the film thickness of the polycrystalline silicon film 8 when crossing the nitride film 5 and changes in the film thickness of the upper silicide film 11. it can.

[0115]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, in the semiconductor device including the MOSFET using the SOI substrate, the end portion of the silicon film has a substantially vertical shape, Since the impurity concentration at the end of the silicon film does not decrease due to the separation by the LOCOS method, it is possible to suppress the generation of the leak current due to the partial decrease in the channel concentration.

Further, since the second insulating film is formed at least under the side wall of the silicon film to protect the silicon film, even if the first insulating film under the silicon film is etched, the over-etched portion is removed. It is possible to eliminate the adverse effect of the cavity due to the above, that is, it is possible to prevent local electric field concentration and suppress the generation of leak current.

The method of manufacturing a semiconductor device according to the present invention is
A method of avoiding the adverse effect of the cavity due to the overetched portion, or a second insulating film is formed below the side wall of the silicon film,
It discloses a method of chamfering the upper portion of the side wall, a method of not generating a cavity due to an overetched portion, or a method of reducing the cavity. According to these manufacturing methods, the yield can be improved and the manufacturing cost can be reduced. it can.

[Brief description of drawings]

1A and 1B are schematic views for explaining a first embodiment of a semiconductor device according to the present invention, in which FIG. 1A is a top view and FIG. 1B is a sectional view taken along line AA. Shows.

FIG. 2 is a schematic cross-sectional view taken along the line BB for explaining the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 3 is a schematic flowchart for explaining the method of manufacturing a semiconductor device according to the first embodiment.

FIG. 4 is a schematic diagram for explaining the structure of the semiconductor device according to the second embodiment, FIG.
Is a top view, (b) is a schematic sectional view taken along the line C-C, (c)
Shows a schematic sectional view taken along the line D-D.

FIG. 5 is a schematic flow chart diagram for explaining a method for manufacturing a semiconductor device according to a second embodiment.

FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 7 is a schematic flow chart diagram for explaining a method for manufacturing a semiconductor device according to a third embodiment.

FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 9 is a schematic flow chart diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment.

10A and 10B are schematic views for explaining the structure of a semiconductor device in an application example of the present invention, in which FIG. 10A is a top view and FIG. 10B is a sectional view taken along line EE. To
(C) has shown sectional drawing of the FF line.

FIG. 11 is a schematic diagram of a MOSFE in the first conventional example.
FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device having T formed therein.

12A and 12B are schematic views for explaining the structure of a MOSFET of a semiconductor device in a first conventional example, FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along line GG. Is shown.

FIG. 13 is a diagram showing a MOSFE in a second conventional example.
FIG. 3 is a schematic cross-sectional view for explaining the structure of the semiconductor device having T formed therein.

FIG. 14 is a graph for explaining the relationship between the drain current and the gate voltage of the MOSFET of the second conventional example.

[Explanation of symbols]

1 Support substrate 2 oxide film 3,3a Silicon film 4 oxide film 5,5a Nitride film 6,6a Gate oxide film 7 Over etching part 8 Polycrystalline silicon film 9 Oxide film 10 SD area 11 Silicide film 12 Insulating film 13 Metal wiring 14 Oxide film 15 Polycrystalline silicon film 16 Nitride film 17 Oxide film 18 Silicon film upper end 19 Silicon film bottom 21 SOI substrate 120 Normal characteristic curve 121 Abnormal characteristic curve 100 MOSFET 200 MOSFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yukishige Saito             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company (72) Inventor Lee Zhou Wu             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company F-term (reference) 5F032 AA06 AA07 AA34 AA46 AA49                       AA70 CA17 DA02 DA23 DA25                       DA26 DA28 DA30 DA33 DA71                 5F110 AA06 CC02 DD05 DD13 EE05                       EE09 EE14 EE32 EE45 FF02                       FF23 GG02 GG12 GG22 GG25                       GG41 GG52 HJ13 HK05 HL03                       NN04 NN22 NN62 NN65 QQ04                       QQ17 QQ19

Claims (15)

[Claims] 1. A semiconductor device comprising a MOSFET formed on an SOI substrate composed of a support substrate, a first insulating film and a silicon film, wherein a sidewall of the silicon film selectively formed for the MOSFET. Is formed vertically, and a second insulating film is formed on at least a lower portion of the side wall. 2. The semiconductor device according to claim 1, wherein the second insulating film is formed on the entire surface of the side wall. 3. The semiconductor device according to claim 2, wherein the second insulating film is formed higher than a gate insulating film formed on the silicon film. 4. The semiconductor device according to claim 1, wherein an upper surface end portion of the silicon film selectively formed for the MOSFET is chamfered. 5. The semiconductor device according to claim 1, wherein the second insulating film is a nitride film. 6. A method of manufacturing a semiconductor device comprising a MOSFET formed on an SOI substrate composed of a supporting substrate, a first insulating film and a silicon film, wherein an insulating film on the silicon film is provided on the SOI substrate. A step of forming an insulating film on the silicon film and the silicon film by anisotropic etching selectively; forming a second insulating film on the SOI substrate; Anisotropically etching the second insulating film to leave the second insulating film at least under the side wall of the silicon film; and selectively etching the insulating film on the silicon film. A step of forming a gate insulating film on the silicon film, and a method of manufacturing a semiconductor device. 7. The upper surface of the silicon film, wherein the second insulating film is formed lower than the silicon film by anisotropic etching, and the silicon film exposed by etching is selectively sacrificed and oxidized. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the end portion is chamfered. 8. A method of manufacturing a semiconductor device comprising a MOSFET formed on an SOI substrate composed of a supporting substrate, a first insulating film and a silicon film, wherein an insulating film on the silicon film is provided on the SOI substrate. A step of forming a second insulating film on the SOI substrate; a step of selectively etching the insulating film on the silicon film and the silicon film by anisotropic etching; Anisotropically etching the insulating film to leave the second insulating film at least under the side wall of the silicon film; and a third insulating film having a wet etching rate substantially equal to that of the insulating film on the silicon film. On the SOI substrate; anisotropically etching the third insulating film to leave the third insulating film on a sidewall of the second insulating film; Absence The method of manufacturing a semiconductor device, characterized in that it comprises the step of wet etching the film, forming a gate insulating film on said silicon film exposed, the. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the third insulating film is not over-etched when the insulating film on the silicon film is wet-etched. 10. When the insulating film on the silicon film is wet-etched, the etching rate of the third insulating film is slower than or equal to the etching rate of the first insulating film. The method of manufacturing a semiconductor device according to claim 9, wherein 11. The semiconductor device according to claim 8, wherein the first insulating film, the insulating film on the silicon film and the third insulating film are oxide films. Manufacturing method. 12. A method of manufacturing a semiconductor device comprising a MOSFET formed on a SOI substrate composed of a supporting substrate, a first insulating film and a silicon film, wherein an insulating film on the silicon film is provided on the SOI substrate. A step of forming a sacrificial layer on the insulating film on the silicon film, and a step of selectively etching the sacrificial layer, the insulating film on the silicon film, and the silicon film by anisotropic etching. A step of forming a second insulating film on the SOI substrate, and anisotropically etching the second insulating film to form side walls of the silicon film, the insulating film on the silicon film and the sacrificial layer, A step of leaving the second insulating film, a step of selectively etching the sacrificial layer, a step of wet etching the insulating film on the silicon film, and a gate on the exposed silicon film. The method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a Enmaku, the. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the sacrificial layer is a polycrystalline silicon film. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the second insulating film is formed thicker than the insulating film on the silicon film. 15. The method of manufacturing a semiconductor device according to claim 6, wherein the second insulating film is a nitride film.