JP3150064B2 - Manufacturing method of vertical field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical field effect transistor, and more particularly to a vertical field effect transistor having a gate electrode embedded in a U-shaped trench and a method of manufacturing the same .

[0002]

2. Description of the Related Art A vertical field-effect transistor in which a channel region is provided on the surface of a semiconductor substrate has a low cell density per unit area, and it is not easy to reduce the on-resistance (R _ON ).
As a method for solving these problems, for example, IEE-E-Transactions-Electron-Devices (IEEE-TRANSACTIONS)
-ELECTRON-DEVICES) ED-34 volume,
No. 11 (1987), pp. 2329-2333,
Etch. R. A vertical field effect transistor having a structure in which a channel region is provided on a side surface of a U-shaped trench has been proposed by Chang (HR CHANG) or the like. By adopting such a structure, the cell density and the channel region density increase, and as a result, R _ON can be reduced.

[0003] With respect to an example of a conventional vertical field effect transistor formed based on the report of Chan et al., FIG . 11A is a plan view, and AA line and BB in FIG.
Figure 11 (b) is a sectional view taken along the line will be described with reference to (c). The vertical field effect transistor here is 30
This is an N-channel vertical field effect transistor having a low withstand voltage of about V.

On the surface of an N ⁺ -type silicon substrate 201 having a resistivity of about 0.004 Ω · cm, an N ⁻ -type epitaxial layer 202 having a thickness of about 5 μm and a resistivity of about 0.35 Ω · cm is provided.
Is provided. The N-type drain region includes the N ⁺ -type silicon substrate 201 and the N ⁻ -type epitaxial layer 202. A LOCOS type field oxide film 203 having a thickness of about 800 nm is provided in an element isolation region on the surface of the N ⁻ type epitaxial layer 202. A P-type base region 204 is provided on the surface of the N ⁻ -type epitaxial layer 202 including the element isolation region. The P-type base region 204 is composed of two P-type wells, and the junction depth of the P-type base region 204 immediately below the field oxide film 203 and in the cell portion is about 2.5 μm and about 1.5 μm, respectively. A trench 224 having a lattice-like U-shape is provided in the cell portion. The trench 224 has the upper surface of the P-type base region 204 (the upper surface of the N ⁻ -type epitaxial layer 202) as an upper end and the P-type base region 2
04, the bottom surface of which is N ^- type epitaxial layer 20.
It is in 2. The depth and opening width of the trench 224 are about 2 μm and about 1 μm, respectively, and the minimum pitch and the minimum interval of the trench 224 are 7 μm, respectively.
m and about 6 μm.

A gate electrode 206 made of an N ⁺ type polycrystalline silicon film fills the trench 224 through a gate oxide film 205 having a thickness of about 50 nm, and
5, pass over the surface of the P-type base region 204 and extend on the surface of the field oxide film 203. On the surface of the P-type base region 204, four N ⁺ -type source regions 207 are provided per cell in a self-aligned manner on the side surface of the trench 224. Trench 2 of these N ⁺ type source regions 207
The width from the 24 side surfaces is about 1.875 μm, and the distance between the opposing N ⁺ type source regions 207 in the same cell is 2.2.
The junction depth of the N ⁺ type source region 207 is about 0.4 μm. Field oxide film 203,
The P-type base region 204, the gate electrode 206, and the N ⁺ -type source region 207 are covered with an interlayer insulating film 208 made of a silicon oxide insulating film having a thickness of about 650 nm. A slit-shaped opening is provided in the interlayer insulating film 208 on the field oxide film 203, and the minimum opening width of the interlayer insulating film just above the P-type base region 204 around the cell part and the central part of the cell part is 3. An opening of about 5 μm is provided. N ^{+ having a} width of about 1.25 μm from the side of the trench 224
The surface of the mold source region 207 is directly covered with the interlayer insulating film 208. A P ⁺ -type base contact region 209 having a junction depth of about 1 μm is self-aligned with the opening of the interlayer insulating film 208 on the surface of the P-type base region 204 around the cell portion and at the center of the cell portion. Is provided. Aluminum wiring 21 provided on the surface of interlayer insulating film 208
0 is through an opening provided in the interlayer insulating film 208,
It is directly connected to the N ⁺ type source region 207 and the P ⁺ type base contact region 209. Further, the aluminum wiring 211 provided on the surface of the interlayer insulating film 208 is directly connected to the gate electrode 206 through a slit-shaped opening provided in the interlayer insulating film 208 on the field oxide film 203. .

The outline of the method for manufacturing the vertical field effect transistor shown in FIG . 11 is as follows.

First, an N ⁻ type epitaxial layer 202 is formed on the surface of an N ⁺ type silicon substrate 201 by silicon epitaxial growth. A first P-type well having a junction depth of about 2.5 μm is formed in a region including a region where an element isolation region is to be formed on the surface of the N ⁻ -type epitaxial layer 202. By a known selective oxidation method, a LOCOS type field oxide film 203 is formed on the surface of the N ⁻ type epitaxial layer 202 in a region where an element isolation region is to be formed. Boron ion implantation of about 2 × 10 ¹³ cm ^-2 ,
By hot pressing at 1140 ° C. for about 10 minutes, a second P layer having a junction depth of about 1.5 μm is formed on the surface of the N ⁻ type epitaxial layer 202 in a self-aligned manner with the field oxide film 203.
The mold well is formed, and the formation of the P-type base region 204 including the first and second P-type wells is completed. By the reactive ion etching (RIE) using the first photoresist film as a mask, the trench 22 having the above configuration is formed.
4 are formed. The side surface of the trench 224 and the top surface of the P-type base region 204 are substantially orthogonal, and the side surface and the bottom surface of the trench 224 are also substantially orthogonal.

Next, a gate oxide film 205 is formed on the surface of the P-type base region 204 and the side and bottom surfaces of the trench 224 by thermal oxidation. An N ⁺ type polycrystalline silicon film is formed on the entire surface. Using the second photoresist film as a mask, the N ⁺ -type polycrystalline silicon film is etched back by RIE to form a gate electrode 206. 1 using the third photoresist film as a mask
× 10 ¹⁶ cm ^- by about two ion implantation of arsenic, N ⁺
A mold source region 207 is formed. Interlayer insulating film 2 on the entire surface
08 is formed, and the opening is formed. Boron ion implantation or the like of about 4 × 10 ¹⁵ cm ⁻² is performed using the interlayer insulating film 208 as a mask, and a P ⁺ -type base contact region 209 is formed on the surface of the P-type source region 204. Thereafter, the aluminum wiring 21 is formed by a known manufacturing method.
0,211 are formed.

[0009]

In the above-mentioned conventional vertical field effect transistor, the gate electrode 206 is buried in the U-shaped trench 224, and the channel region composed of the P-type base region 204 is formed on the side surface of the trench 224. Is provided. 12 and 13 which are schematic sectional views,
Referring to FIG. 14 , which is a graph showing the trench (opening) width dependence of the drain-to-drain breakdown voltage (BV _DSS ), two problems related to the shape (and manufacturing method) of the trench 224 of the vertical field effect transistor described above. The points will be described.

The first problem is that the forward admittance (y
_fs ). Since the gate oxide film 205 is formed after the formation of the trench 224, the trench 2
Damage due to RIE for forming the trenches 24 also remains on the side surfaces of the trenches 224 serving as channel regions of the transistor [ FIG. 12 ]. As a result, the carrier mobility in the channel region of the transistor decreases, and the forward admittance y _fs =
_{(W / L) μC OX (} V G -V T) ( where, W: channel width, L: channel length, mu: carrier mobility, C _OX: capacitance per unit area, V _G: gate voltage, ( _VT : threshold voltage) decreases. This is one of the hindrance factors of R _ON reduction.
It is one.

The second problem is a decrease in the source-drain breakdown voltage (BV _DSS ) and the gate breakdown voltage. Since the side surface and the bottom surface of the trench 224 are substantially perpendicular to each other, the electric field intensity increases at the corner formed by the side surface and the bottom surface, and when the (opening) width of the trench 224 becomes 2 μm or less, the portions having the high electric field intensity overlap. Source-drain breakdown voltage (BV
_DSS ) drops from about 43.5 V [ FIGS .
4 ]. For this reason, it becomes difficult to reduce the opening width of the trench 224 to improve the cell density and further improve the _RON . At the upper end of trench 224, the side surface of trench 224 and the upper surface of P-type base region 204 are substantially orthogonal to each other. The thickness of the gate oxide film 205 is smaller than the thickness of the gate oxide film 205 in other portions. Therefore, for example, in the middle of the portion where the gate electrode 206 extends over the surface of the field oxide film 203, will be FN current flows V _G is about 20V, so that the gate breakdown voltage is lowered [13].

Although it is a secondary problem, the vertical field-effect transistor having the above structure is not suitable for a vertical field-effect transistor that requires a high operation speed. This is because the parasitic capacitance between the gate electrode 206 and the N ⁻ -type epitaxial layer 202 becomes large (particularly on the bottom surface of the trench 224) because the gate electrode 206 is buried in the trench 224.

Accordingly, an object of the vertical field effect transistor of the present invention is to reduce the forward admittance (y _fs ) and reduce the source in a vertical field effect transistor having a structure in which a channel region is provided on the side surface of a U-shaped trench. The object of the present invention is to suppress the decrease in the drain-to-drain breakdown voltage (BV _DSS ), facilitate the improvement of the cell density and the reduction of R _ON , and suppress the decrease in the gate breakdown voltage. Further, in a vertical field effect transistor requiring a high operation speed, it is an object to reduce a parasitic capacitance between a gate electrode and a drain region to facilitate high-speed operation.

[0014]

According to the present invention, there is provided a vertical field effect transistor according to the present invention.
The method of manufacturing a transistor is that an N + type silicon substrate is coated with N
Forming an epitaxial layer of the type;
Forming a P-type base region on the surface of the axial layer
And a pad oxide film on the P-type base region by thermal oxidation
And forming the entire surface by vacuum chemical vapor deposition.
A silicon nitride film and use the photoresist film as a mask
The silicon nitride film, the pad oxide film and the base
Base region is sequentially etched by RIE,
An upper end on the upper surface of the base region, and penetrating through the base region.
Forming a trench having a bottom surface in the epitaxial layer
And a selective acid using the silicon nitride film as a mask.
Oxidized silicon covering the bottom and side surfaces of the trench
Forming a silicon film and removing the silicon oxide film
Then, the bottom surface of the trench is made U-shaped, and then
Form gate oxide film to cover side and bottom of trench
And forming the trench through the gate oxide film.
Forming a gate electrode to be filled;
N + type source region on the surface of the base region around the upper end
Forming a step.

[0015]

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a vertical field effect transistor, and FIG. 2 is a sectional view taken along lines AA and BB in FIG.
Referring to (a) and (b), an N-channel vertical field effect transistor having a low withstand voltage of about 30 V according to the first embodiment of the present invention is as follows.

On the surface of an N ⁺ -type silicon substrate 101 having a resistivity of about 0.004 Ω · cm, an N ⁻ -type epitaxial layer 102 having a thickness of about 5 μm and a resistivity of about 0.35 Ω · cm is provided.
Is provided. The N-type drain region includes the N ⁺ -type silicon substrate 101 and the N ^-- type epitaxial layer 102. A LOCOS type field oxide film 103 having a thickness of about 800 nm is provided in an element isolation region on the surface of the N ⁻ type epitaxial layer 102. A P-type base region 104 is provided on the surface of the N ⁻ -type epitaxial layer 102 including the element isolation region. The P-type base region 104 is composed of two P-type wells, and the junction depth of the P-type base region 104 immediately below the field oxide film 103 and in the cell portion is about 2.5 μm and about 1.5 μm, respectively.

A trench 1 having a U-shaped lattice shape
24aa are provided in the cell section. This trench 1
24aa is a P-type base region 10 with the upper surface of the P-type base region 104 (the upper surface of the N ⁻ -type epitaxial layer 102) as the upper end.
4 and its bottom surface is an N ⁻ -type epitaxial layer 102.
Inside. The depth and opening width of the trench 124aa are about 2 μm and about 1 μm, respectively, and the minimum pitch and minimum interval of the trench 124aa are about 7 μm and 6 μm, respectively. In the trench 124aa according to the first embodiment, the trench 124aa
The corner formed by the side surface aa and the top surface of the P-type base region 104 is rounded, and the corner formed by the side surface and bottom surface of the trench 124aa is rounded.

The film thickness just above the field oxide film 103 is 8
The gate electrode 106a made of an N ⁺ -type polycrystalline silicon film of about 00 nm has a thickness of about 50 nm.
The trench 124aa is filled via the gate oxide film 105a, passes over the surface of the P-type base region 104 via the gate oxide film 105a, and extends on the surface of the field oxide film 103. Trench 124aa near field oxide film 103
Also, the corner formed by the side surface of trench 124aa and the upper surface of P-type base region 104 is rounded. Therefore, the thickness of the gate oxide film 105a in this portion is about 50 nm, like the thickness of the gate oxide film 105a in other portions.

On the surface of the P-type base region 104, four N ⁺ -type source regions 107 per cell are provided in a self-aligned manner on the side surface of the trench 124aa. These N ⁺ -type source regions 107 have a width of 1.1 from the side surface of trench 124aa.
Is about 875Myuemu, interval N ⁺ -type source region 107 opposed to each other in the same cell is about 2.25 micrometers, N ⁺
The junction depth of the mold source region 107 is about 0.4 μm. Field oxide film 103, P-type base region 104,
The gate electrode 106a and the N ⁺ type source region 107
It is covered with an interlayer insulating film 108 made of a silicon oxide film having a thickness of about 650 nm. Field oxide film 103
A slit-shaped opening is provided in the upper interlayer insulating film 108, and the minimum opening width is 3.5 μm in the interlayer insulating film just above the P-type base region 104 around the cell part and on the center part of the cell part.
About an opening is provided. The surface of the N ⁺ -type source region 107 having a width of about 1.25 μm from the side surface of the trench 124aa is directly covered with the interlayer insulating film 108. The surface of the P-type base region 104 around the cell portion and at the center of the cell portion is self-aligned with the opening of the interlayer insulating film 108.
A P ⁺ type base contact region 109 having a junction depth of about μm is provided. The aluminum wiring 210 provided on the surface of the interlayer insulating film 108 is directly connected to the N ⁺ -type source region 107 and the P ⁺ -type base contact region 109 through an opening provided in the interlayer insulating film 108. I have. The aluminum wiring 111 provided on the surface of the interlayer insulating film 108 is directly connected to the gate electrode 106a via a slit-shaped opening provided in the interlayer insulating film 108 on the field oxide film 103. .

Referring to FIG. 1, FIG. 2, and FIGS. 3 and 4 which are cross-sectional views of the manufacturing process along the line AA in FIG. 1, an example of the manufacturing method according to the first embodiment is as follows. , As follows.

First, an N ^- type epitaxial layer 102 is formed on the surface of an N ⁺ type silicon substrate 101 by silicon epitaxial growth. A first P-type well 104A having a junction depth of about 2.5 μm is formed in a region including a region where a device isolation region is to be formed on the surface of the N ⁻ -type epitaxial layer 102. By a known selective oxidation method, a LOCOS type field oxide film 1 is formed in a region where an element isolation region is to be formed on the surface of the N ⁻ type epitaxial layer 102.
03 is formed. Subsequently, 70 keV, 2 × 10 ¹³ c
Boron ion implantation of about m ^-2 is performed. photo·
After the resist film 152 is removed, hot pressing is performed at 1140 ° C. for about 10 minutes so that the junction depth becomes 1.5.
A second P-type well 104B of about μm is formed. Thus, the formation of the P-type base region 104 including the P-type well 104A and the P-type well 104B is completed. On the surface of the P-type well 104A, a film thickness of 50 nm is formed by thermal oxidation.
About a pad oxide film 131 is formed. 100n film thickness covering the entire surface by low pressure chemical vapor deposition (LPCVD)
m of silicon nitride film 135 is formed [FIG.
(A)].

Next, using the photo resist film 151 as a mask, the silicon nitride film 135, the pad oxide film 131,
P-type base region 104 and N ^- type epitaxial layer 1
02 are sequentially etched by RIE, and the trench 12
4a is formed. The minimum pitch of the trench 124a is 7
The opening width and the depth of the trench 124a are about 0.8 μm and about 1.9 μm, respectively. At this stage, the shape of the trench 124a is the same as that of the conventional trench [FIG. 3B].

After removing the photo-resist film 151,
Selective oxidation is performed using the silicon nitride film 135 as a mask, and a film thickness 15 covering the side and bottom surfaces of the trench 124a is formed.
A LOCOS type silicon oxide film 141 having a thickness of about 0 nm is formed (FIG. 3C).

Subsequently, the silicon oxide film 141, the silicon nitride film 135,
Pad oxide film 131 is sequentially removed. Next, a gate oxide film 105a having a thickness of about 50 nm is formed by thermal oxidation. In these processes, the trench 124a becomes the trench 124aa. The opening width and depth of the trench 124aa are about 1 μm and about 2 μm, respectively, and the side surface of the trench 124aa and the P-type base region 104
The corner formed by the upper surface of the trench 124aa is rounded, and the corner formed by the side surface and the bottom surface of the trench 124aa is also rounded [FIGS. 1, 2 and 3 (d)].

Next, an N ⁺ -type polycrystalline silicon film having a thickness of about 800 nm is formed on the entire surface. On the surface of this N ⁺ type polycrystalline silicon film, a photoresist film 152 is formed. The photo-resist film 152 covers the field oxide film 103 in such a manner that the photo-resist film 152 covers the field oxide film 103, and further has a shape in which the edge of the photo-resist film 152 hangs over a part of the trench 124 aa provided in the periphery of the cell portion. . Using this photo-resist film as a mask, the N ⁺ -type polycrystalline silicon film is etched back by RIE to form trench 1
24aa is buried, and a gate electrode 106a extending directly above the field oxide film 103 is formed [FIGS. 1, 2 and 4 (a)].

Next, a photoresist film 153 is formed to cover the periphery of the cell including the field oxide film 103 and a portion including the center of each cell. For example, in a square cell portion, a photoresist film 15 covering these central portions is formed.
The pattern width of No. 3 is about 3.5 μm. This photo
Using the resist film 153 as a mask, 50 keV, 1 × 1
Arsenic ion implantation of about 0 ¹⁶ cm ^-2 is performed, and four N ⁺ -type source regions 107 are formed in each cell [FIGS. 1, 2, and 4 (b)].

Next, for example, the N ⁺ type source region 107, P
Gate oxide film 105 exposed on the surface of mold base region 104
After removing a, an interlayer insulating film 108 made of a silicon oxide film having a thickness of about 650 nm is formed by chemical vapor deposition (CVD).
Is formed over the entire surface. This N ⁺ type source region 107
The gate oxide film 105a was not removed until the step of forming the P type source region 1
This is because crystal defects frequently occur when the process is performed directly on the surface of the gate oxide film 104. The removal of the gate oxide film 105a after the formation of the N ⁺ -type source region 107 is performed by arsenic ion implantation.
The gate oxide film 105a is formed by the photo resist film 153.
Is contaminated. The gate oxide film 10
After removing 5a, the exposed surface may be re-oxidized. In this case, the interlayer insulating film 109 can be formed of a BPSG film or a PSG film.

Next, a slit-shaped opening is formed on the field oxide film 103, and the P-type base region 1 around the cell portion is formed.
Photoresist film 1 having an opening with a minimum opening width of about 3.5 μm in the interlayer insulating film immediately above the substrate 04 and on the cell portion.
54 is formed on the surface of interlayer insulating film 109. First, RI using this photoresist film 154 as a mask
E forms an opening in the interlayer insulating film 109. Subsequently, ion implantation of boron difluoride (BF ₂ ) of about 50 keV and about 4 × 10 ¹⁵ cm ⁻² is performed, and the surface of the P-type source region 104 is self-aligned with the opening of the interlayer insulating film 109. Then, a P ⁺ type base contact region 109 is formed (FIGS. 1, 2 and 4C).

Thereafter, an aluminum film having a required thickness is formed on the entire surface, and is patterned to form an aluminum wiring 11.
Thus, the vertical field-effect transistor according to the first embodiment is completed (FIGS. 1 and 2).

The vertical field effect transistor according to the first embodiment
The transistor forms the trench 124a as described above.
After the formation, the LOC is formed on the side and bottom of the trench 124a.
An OS type silicon oxide film 141 is formed.
After the silicon film 141 is removed, the gate oxide film 105a is removed.
Is formed. For this reason, the trench which becomes the channel region
Damage is removed from the side of 124aa. The result
As a result, the vertical field effect transistor according to the first embodiment
The forward admittance (y_fs) Decline is suppressed
Will be. Further, the side surface of the trench 124aa
The corner formed by the upper surface of the P-type base region 104 is rounded,
The corner formed by the side and bottom of the trench 124aa is also rounded
Have been. As a result, as shown in FIG.
Even if the (opening) width of 4aa is reduced to about 0.5 μm,
Source-drain breakdown voltage (BV_DSS ) Is from 43.5V
The source-drain breakdown voltage (BV_DSS)
Is suppressed. Also, the gate breakdown voltage is low.
Is also suppressed, and the gate voltage (V_G)
Is about 40V. Furthermore, from these results,
Density improvement, R_ONReduction is facilitated.

The method for manufacturing the vertical field effect transistor according to the first embodiment is not limited to the method shown in FIGS. Referring to FIG. 6, which is a cross-sectional view of the main manufacturing steps, another manufacturing method of the vertical field-effect transistor according to the first embodiment is as follows.

First, up to the first P-type well 104A is formed by a method similar to the above-described manufacturing method. Then N
^- -type epitaxial layer 102 (and the P-type well 104
A) A pad oxide film 132 is formed on the surface, and a silicon nitride film 136 is formed on the entire surface. Using a photoresist film (not shown) as a mask, the silicon nitride film 136 on the region where the element isolation region is to be formed is removed. After the photo-resist film is removed, a field oxide film 103 is formed by selective oxidation. Then, the second P
The mold well 104B is formed, and the formation of the P-type base region 104 is completed (FIG. 6A). Subsequently, a trench 124a is formed using the photoresist film 151 as a mask. The subsequent manufacturing method is the same as the above manufacturing method.

In the first embodiment, an N-channel vertical field effect transistor has been described as an example. However, the first embodiment is not limited to this. Also applies to vertical field effect transistors. Further, the first embodiment is not limited to the numerical values, materials, device parameters, and process parameters used in the above description.

[0036] and FIG. 7 is a plan view of the vertical field effect transistor, AA line of FIG. 7, FIG. 8 is an enlarged sectional view taken along the BB line (a), the (b), as a reference example of the present invention FIG. 11 is a diagram of a case where the present invention is applied to an N-channel vertical field effect transistor having a low withstand voltage of about 30 V. This embodiment differs from the first embodiment in that an N-type diffusion layer is provided at the bottom of the trench.

The gist of the embodiment of the present invention is as follows. The form and various parameters of the trench 124ba are the same as those of the trench 124aa of the first embodiment. An N-type diffusion layer 122 is provided on the surface of N- type epitaxial layer 102 forming the bottom of trench 124ba. Gate oxide film 105b, gate electrode 106
b is also the gate oxide film 1 of the first embodiment.
05a and the same as the gate electrode 106a.

With reference to FIG. 9, which is an enlarged sectional view of the main manufacturing process taken along the line AA in FIG. 7, a manufacturing method related to the above-described difference of the embodiment of the present invention will be described.

First, the steps up to the formation of the field oxide film 103, the P-type base region 104, the pad oxide film 131, and the silicon nitride film 135 are performed in the same manner as in the first embodiment. Subsequently, the silicon oxide film 14 having a required thickness is formed by atmospheric pressure chemical vapor deposition (APCVD).
5 is formed on the entire surface. Similarly to the first embodiment, using a photoresist film (not shown) as a mask,
The silicon oxide film 145, the silicon nitride film 135, the pad oxide film 131, the P-type base region 104, and the N ⁻ -type epitaxial layer 102 are sequentially etched by RIE, and a trench 124b is formed on the surface of the P-type base region 104 [FIG. 9 (a)]. These trenches 124b
Are the same as those of the trench 124a in the first embodiment.

Subsequently, a silicon oxide film having a thickness of about 50 nm is formed on the entire surface by LPCVD, and the silicon oxide film is etched back by RIE to form an insulating film spacer 146. Thereafter, arsenic (As) ion implantation of about 1 × 10 ¹² cm ⁻² is performed, and trench 1 is formed.
An N-type diffusion layer 122 is formed on the surface of the N ⁻ -type epitaxial layer 102 that forms the bottom surface of 24b (FIG. 9B). Next, the silicon oxide film 145 and the insulating film spacer 14
6. The silicon nitride film 135 and the pad oxide film 131 are sequentially removed by wet etching. Thereafter, through the same steps as in the first embodiment, FIGS.
Is formed as shown in FIG.

The silicon oxide film 145 is formed by APC
The reason for performing the VD and forming the silicon oxide film constituting the insulating film spacer 146 by the LPCVD is to facilitate removal of the silicon oxide film 145, the insulating film spacer 146, the silicon nitride film 135, and the pad oxide film 131. is there. A film forming temperature of about 400 ° C. for the silicon oxide film by APCVD is sufficient. Insulating film spacer 14
If the silicon oxide film constituting 6 is formed by LPCVD, no problem occurs in the step coverage of the trench 124b. In addition, ozone (O ₃ ) and TEOS (Si
If (OC ₂ H ₅ ) ₄ : tetraethoxysilane) is used as a raw material, this LPCVD can be performed at a low film forming temperature. In these cases, in the wet etching of the silicon oxide film, the etching rate of the silicon oxide film 145 and the insulating film spacer 146 can be higher than the etching rate of the pad oxide film 131. Immediately after forming the silicon oxide film by LPCVD, boron (without forming the insulating film spacer 146)
Ion implantation may be performed.

In the embodiment of the present embodiment , BVDSS itself is 34
Although it becomes about V, its dependence on the width of the trench 124ba (opening) has the same tendency as in the first embodiment, and even if the width is reduced, the BVDSS does not decrease. The removal of the damage on the side of the trench 124ba serving as the channel region and the suppression of the reduction of the gate withstand voltage are the same as those in the first embodiment. As shown in FIG. 10 which is a graph of the IV characteristic,
It is increased by about 12% compared to the first embodiment.

Note that the embodiment of the reference example is not limited to the N-channel type vertical field-effect transistor as in the first embodiment, but is also applicable to the P-channel type vertical field-effect transistor. Applied.

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

As described above, the vertical field-effect transistor of the present invention has a structure in which a channel region is provided on the side surface of a U-shaped trench. Region) having an upper end on the top surface, having a bottom surface in the epitaxial layer through the base region, and a base region (source region) at the upper end
It has a rounded angle with the top surface and a rounded angle with the side surface and the bottom surface. This suppresses the decrease in forward admittance and the withstand voltage between the source and drain, thereby reducing cell density. And the reduction of R _ON are facilitated, and a decrease in gate breakdown voltage is suppressed.

In a vertical field effect transistor requiring a higher operation speed, LOCOS is formed on the bottom of the trench.
Providing the silicon oxide film of the type reduces the parasitic capacitance between the gate electrode and the drain region, and facilitates high-speed operation.

[Brief description of the drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment, which is a cross-sectional view taken along line AA and line BB in FIG.

FIG. 3 is a cross-sectional view of the manufacturing process according to the first embodiment, which is a cross-sectional view taken along the line AA in FIG.

FIG. 4 is a cross-sectional view of the manufacturing process of the first embodiment, which is a cross-sectional view of the manufacturing process taken along line AA in FIG.

FIG. 5 is a diagram for explaining the effect of the first embodiment, and is a graph showing the trench width dependence of the source-drain breakdown voltage.

FIG. 6 is a cross-sectional view of another manufacturing process of the first embodiment, which is a cross-sectional view of the manufacturing process along line AA in FIG. 1;

FIG. 7 is a plan view of an embodiment of the present invention .

FIG. 8 is an enlarged sectional view of the embodiment of the reference example , and FIG.
3 is an enlarged sectional view taken along line AA and line BB of FIG.

FIG. 9 is an enlarged cross-sectional view of a main manufacturing process according to the embodiment of the reference example , and is an enlarged cross-sectional view of the main manufacturing process along line AA in FIG. 7;

FIG. 10 is a diagram for explaining an effect of the embodiment of the reference example, and is a graph of an IV characteristic of a drain current with respect to a gate voltage.

FIG. 11 is a plan view of a conventional vertical field effect transistor.
FIG.

FIG. 12 is a problem of the conventional vertical field-effect transistor.
FIG. 4 is a schematic cross-sectional view for explaining points.

FIG. 13 is a problem of the conventional vertical field effect transistor.
FIG. 4 is a schematic cross-sectional view for explaining points.

FIG. 14 is a problem of the conventional vertical field-effect transistor.
It is a diagram for explaining the point, the withstand voltage between the source and drain
5 is a graph showing the trench width dependence of the above.

[Explanation of symbols]

101, 201 N ⁺ type silicon substrate 102, 202 N ⁻ type epitaxial layer 103, 103a, 203 Field oxide film 104, 204 P type base region 105a , 105b , 205 Gate oxide film 106a , 106b , 206 Gate electrode 107, 207 N ⁺ Type source region 108, 208 interlayer insulating film 109, 209 P ⁺ type base contact region 110, 111, 210, 211 aluminum wiring 122 N type diffusion layer 123, 141 , 145 silicon oxide film 124a, 124aa, 124b, 124ba, 224
Trench 131-133 Pad oxide film 135-137 Silicon nitride film 146 Insulating film spacer 151-154 Photo resist film

Continuation of the front page (56) References JP-A-56-58267 (JP, A) JP-A-6-132539 (JP, A) JP-A-1-192174 (JP, A) JP-A-2-51279 (JP) , A) JP-A-1-310576 (JP, A)

Claims (1)

(57) [Claims] And 1. A process for forming an epitaxial layer of N- type on a surface of the N + -type silicon substrate, forming a P-type base region on a surface of the epitaxial layer, the P-type base by thermal oxidation Form pad oxide on the area
Forming a silicon nitride film on the entire surface by a low pressure chemical vapor deposition method , etching the silicon nitride film, the pad oxide film and the base region sequentially by RIE using a photoresist film as a mask, Forming a trench having an upper end on an upper surface of the base region and penetrating the base region and having a bottom surface in the epitaxial layer; and performing selective oxidation using the silicon nitride film as a mask, thereby forming a bottom surface of the trench. And forming a silicon oxide film covering the side surfaces; and removing the silicon oxide film and forming a U-shaped bottom surface of the trench.
Forming a gate oxide film covering the side and bottom surfaces of the trench by thermal oxidation after forming the mold; forming a gate electrode filling the trench via the gate oxide film; N + is applied to the surface of the base region.
Forming a source region of a vertical type.