JPH05235356A - Insulated-gate thin-film semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a structure for decreasing off-state current in an insulated- gate thin-film semiconductor device. CONSTITUTION:An insulated-gate thin-film semiconductor device comprises a channel region 103 under a gate insulator, and a semiconductor region 109 under the channel region. The semiconductor region 9 has a conductivity type opposite to that of source and drain regions to decrease the leakage current between the source and drain regions. In addition, this amorphous semiconductor region shields the channel region from effects of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film insulating gate semiconductor device having a large ratio of ON current and OFF current (ON / OFF ratio) and particularly a small OFF current, and more particularly to a thin film transistor (TFT).

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film channel region on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel of a display device such as a liquid crystal having a matrix structure, and depending on the material and crystal state of the semiconductor to be used,
It is distinguished as an amorphous silicon TFT or a polycrystalline silicon TFT. However, recently, research has also been carried out using a material exhibiting an intermediate state between polycrystalline silicon and amorphous. This is called semi-amorphous, and it is considered that a small crystal floats in an amorphous structure.

Also, in a single crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technology, and this is used as a load transistor in, for example, a highly integrated SRAM. In this case, the amorphous silicon TFT is rarely used.

Generally, a semiconductor in an amorphous state has a low electric field mobility, and therefore TF requiring high speed operation.
Not available for T. Further, since amorphous silicon has a remarkably small P-type electric field mobility, a P-channel type TFT (PTFT) cannot be manufactured. Therefore, in combination with an N-channel type TFT (NTFT), a complementary MOS type is formed. A circuit (CMOS) cannot be formed.

However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, unlike a transistor of a liquid crystal active matrix, such a high-speed operation is not required, and only one conductivity type is sufficient and the charge holding ability is high.
It is used in applications that require FT.

On the other hand, a polycrystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, a TFT using a silicon film recrystallized by laser annealing has a field mobility as high as 300 cm ² / Vs. Considering that the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value, and M on single crystal silicon is large.
While the operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring, there is no such restriction because it is on the insulating substrate, and extremely high speed operation is expected.

Further, since not only NTFT but also PTFT can be obtained with polycrystalline silicon, a CMOS circuit can be formed. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also the active matrix portion can be formed. , Peripheral circuits (drivers, etc.) also CMO
There is known one having a so-called monolithic structure, which is composed of an S polycrystal TFT.

The TFT used in the above-mentioned SRAM also pays attention to this point, and the PMOS is constituted by the TFT,
This is used as a load transistor.

However, in general, a polycrystalline TFT has a larger electric field mobility than an amorphous TFT,
The OFF current was large, and the ability to hold the charge of the pixels of the active matrix was poor. In the past, there was no particular problem because the size of the pixel was several 100 μm square and the pixel capacity was large, but in recent years, the pixel capacity has become smaller and stable because the pixel has become finer with higher definition. Insufficient for static display. Also, when used in SRAM, the power consumption increases when the OFF current is large.

Further, in a normal amorphous TFT, it is difficult to form the source / drain regions by the self-alignment process as used in the single crystal IC technique, and the gate electrodes and the source / drain regions are geometrically shaped. While the parasitic capacitance due to overlap is a problem,
Since the polycrystalline TFT can adopt the self-alignment process, it has a feature that the parasitic capacitance can be significantly suppressed.

That is, as shown in FIG. 2, a conventional polycrystalline TFT has a source region 204, a drain region 202, and a channel region 203 of approximately the same thickness formed on a substrate 201, and is manufactured by employing a self-alignment process. The T
In the FT, the channel region (active layer) 203 was formed in almost the same shape as the gate electrode 205. In the figure, 20
Reference numeral 6 is an interlayer insulator, and 207 and 208 are a drain electrode and a source electrode, respectively.

[0012]

[Problems to be Solved by the Invention] Such a polycrystalline TF
Some problems have been pointed out for the advantage of T. Several solutions have been proposed for the problem of OFF current, which is one of them. One of them is
This is a method of thinning the active region. It has been reported that the OFF current is reduced by doing so. For example, it is known that the OFF current can be 10 ⁻¹³ A or less by setting the thickness of the channel region to 25 nm. However, it is known that it is very difficult to crystallize a thin semiconductor film, and it is not easily crystallized. That is, in order to obtain a sufficient crystallinity and form an activated region (channel region) having a field mobility that can withstand practical use, a method of performing annealing at a high temperature or performing annealing for a long time is required. .. When high temperature annealing is adopted, a heat resistant material such as quartz is required for the substrate. However, the quartz substrate is very expensive, especially if it has a large area, and there is a cost problem. Further, performing annealing for a long time also causes a decrease in throughput, which is also difficult in terms of cost.

On the other hand, thinning the active layer also leads to thinning the source / drain regions. That is, in the usual manufacturing method, both the source / drain and the active region are formed from the semiconductor film manufactured at the same time and have the same thickness. This leads to an increase in the resistance of the source / drain region.

For that purpose, a method of separately forming so as to thicken most of the source / drain regions is adopted, but this is an additional mask process, which is not preferable in terms of yield.

Further, according to the knowledge of the present inventors, the absolute value of the MOS threshold voltage is small in a TFT having an active layer of 50 nm or less, and therefore the CMO in such a TFT is small.
When S is produced, the operation becomes extremely unstable.

On the other hand, the thicker the activation layer is, the larger the OFF current becomes, but the magnitude thereof is not proportional to the thickness of the active layer. Therefore, the OFF current is nonlinearly increased due to some factor. Conceivable. An example of the characteristics of a TFT in which the thickness of the active layer is 100 nm is shown in FIG.
Shown in. The gate oxide film has a thickness of 150 nm, the active layer is formed by low pressure CVD (LPCVD), and annealed at 600 ° C. for 24 hours.
The voltage between the source and the drain is 1V. As shown in the figure, the ON current is large, but the OFF current is also large. Moreover,
When a reverse bias is applied to the gate electrode, it exhibits abnormal characteristics like a bump.

When the active layer is thick, the crystallinity of the active layer is good and a TFT having a large electric field mobility can be obtained. No special high temperatures or long annealing times are required. As a result of the research conducted by the present inventors, it is clear that most of the OFF current of a TFT having a thick active layer flows as a bypass via a portion of the active layer on the substrate side as indicated by an arrow 209 in FIG. I was killed. When the ideal OFF current is I _OFF and the ON current is I _ON , the ON / OFF ratio of the TFT is I _ON.
/ I _OFF . However, if a bypass leakage current I _LK that hardly responds to the gate voltage is flowing, the ON / OFF ratio is (I _ON + I _LK ).
It is represented by / (I _OFF + I _LK ). Actually I _LK is I _OFF
It is estimated to be much larger than I _ON but smaller than I _ON , so the apparent ON / OFF ratio is I
_{Expressed as ON} / I _LK . For this reason, it is considered that the ON / OFF ratio, which is an important index of the characteristics of the TFT, is remarkably reduced.

There are two possible causes for such a leak current. One is that the crystallinity of the active layer on the substrate side is not good. That is, since there are too many grain boundaries, many trap levels are formed there, and the trap levels hop to move charges. Since this trap level exists regardless of the gate voltage, it always acts as an offset current source. This case could be overcome by optimizing the crystal growth conditions, but it is expected to be very difficult.

Another reason is that mobile ions such as sodium enter the active layer from the substrate side to make the portion on the substrate side conductive. This is overcome by increasing the cleanliness of the process.

However, whichever method is used, if the channel layer (active layer) is thick, the OFF current will increase in an ohmic manner. On the other hand, since the thickness of the source / drain is sufficient, the resistance in that portion is sufficiently small.

It is desired that an ideal TFT has a large electric field mobility. In addition, it is desired that the resistance of the source / drain is small. On the other hand, it is desired that the OFF current is small. Of course, introducing complex processes into fabrication should be avoided. In view of such a current situation, the present invention is made to solve some or all of the above problems and provide a TFT close to an ideal TFT.

[0022]

As a method for solving the above problems, in the present invention, the crystallinity of the active layer is not good,
Alternatively, we propose a TFT that does not use a portion on the substrate side, which has poor characteristics, as a channel because, for example, mobile ions remain. To this end, in the present invention, an impurity is added to the active layer portion on the substrate side so as to have conductivity opposite to that of the source / drain regions, so that the portion does not substantially function as a channel.

A conceptual diagram of the TFT according to the present invention is shown in FIG. In FIG. 1, an impurity semiconductor region having a conductivity type opposite to that of the source region 104 and the drain region 102 is formed in the lower region 109 of the active layer region below the gate electrode 105. The upper region 103 of the active layer functions as a channel as before, but the lower region 109 on the substrate 101 side is inferior in characteristics.
Does not function as a channel due to the added impurities. It is sufficient that the concentration of the impurity added to the region 109 is 1/10 to 1/100 of the concentration of the impurity added to the source / drain. This is because the conductivity type of the region 109 required at this time has a conductivity type sufficiently different from that of the channel region 103, or the gap between the conduction band (valence band) at the interface between the channel 103 and the region 109. As long as is large enough. It is known that the level of the conduction (valence electron) band is dramatically changed by adding a very small amount of impurities in a semiconductor containing few impurities. If the concentration of impurities added to the source / drain is 10 ²⁰ cm ⁻³
Therefore, the effective impurity concentration of the channel region 103 is 10 ¹⁶
cm ⁻³ , the impurity concentration of the region 109 is 10 ¹⁸ cm
^-3 is enough. Of course, the conductivity type of impurities added to the region 109 must be selected so as to be opposite to that of the source / drain.

In order to form such a region 109, it is necessary to form two layers of semiconductor films having different impurity concentrations. For that purpose, a method of forming two layers of semiconductor films having different impurity concentrations in a multi-layer manner, or an impurity may be added to the substrate in advance to form the semiconductor film, and then the impurities may be diffused from the substrate. For example, assuming that the impurity concentration of the region 109 is 1/10 of the impurity concentration of the source / drain, when the source / drain is formed by the self-alignment process later, among the films formed earlier. The portion that does not become the region 109 is easily converted into the same conductivity type as the source / drain by the subsequent introduction of impurities. This is because the impurity concentration is low. Therefore, the channel region is thin and the source /
It is possible to obtain the ideal TFT of the present invention in which the drain region is thick.

If the impurity concentration of the region 109 is the source /
If the impurity concentration of the drain is equal to or higher than that of the drain, the conductivity type cannot be changed when the source / drain is formed later.
The drain is also thin. of course,
Even such a shape does not violate the technical idea of the present invention that the active layer on the substrate side having poor characteristics is not used as a channel.

In FIG. 1, it is described that there is a clear boundary between the channel region 103 and the region 109 therebelow, but such a clear boundary exists for the purpose of the present invention. It will be clear that there is no need to have to do so, and it is possible to use a material in which impurities and compositional elements change gently.

Further, in the present invention, when the source / drain regions have uniform electrical characteristics such as resistivity over the thickness direction, the substantial source / drain thickness is smaller than the channel thickness, Is an ideal TFT in which the source / drain resistance (sheet resistance) is large.

In the present invention, it is presumed that the band gap shown in FIG. 3 (B) is formed. That is,
FIG. 3B is a band diagram of the source / drain and the channel of the TFT having the structure described in FIG. 1 and a portion thereunder. In this figure, a PTFT is shown,
The same applies to NTFT. As is clear from such a band diagram, holes in the valence band (electrons in the conduction band in NTFT) are the regions 1 of different conductivity types under the channel.
09 is difficult to enter, and as a result, current rarely leaks through that portion.

The present invention may be applied to a conventional TFT as it is, but it is the invention of the present inventors, Japanese Patent Application No. 3-2.
When it is applied to a TFT having an offset region as described in 31188 or Japanese Patent Application No. 3-238713, a further effect is brought about. Each of the inventions was effective in reducing the OFF current, and in particular, in improving the reverse leakage when a reverse voltage was applied to the gate electrode, but was not effective in reducing the absolute value of the OFF current. However, by using the present invention and these inventions together, it is possible to suppress reverse leakage and
It was possible to reduce the absolute value of the current and thus increase the ON / OFF ratio.

An example of the effect is shown in FIG. In the figure, (c) shows the characteristics of a conventional TFT (NTFT). (B) is the one in which the present invention is applied to a conventional TFT. Specifically, 2 × 10 ¹⁹ cm ⁻³ of boron is added to the channel region as an impurity and the lower portion as an impurity. Formed of weak P-type polycrystalline silicon. The source / drain was made to have a strong N-type by adding phosphorus as an impurity by 1.1 × 10 ²⁰ cm ⁻³ .
That is, it is an NTFT. The gate is a silicon gate. In this case, the OFF current when the gate voltage is 0 is remarkably reduced as compared with the conventional example, but the reverse leakage current is still large. This is because the channel becomes P-type due to the negative gate voltage, and the band structure of the source / drain (N-type) and the channel (P-type) is broken.
It is considered that this is because in a semiconductor having poor crystallinity such as a polycrystalline semiconductor, the hopping current flows through the level existing at this boundary.

Therefore, if the present invention is applied to a TFT (aluminum gate) having an offset region as described in, for example, Japanese Patent Application No. 3-231188, such reverse leakage can be suppressed, as shown in (a). Such good characteristics can be obtained. In this figure, except for the gate electrode, it is the same as that shown in (b) above. Especially, Japanese Patent Application No. 3-2
In the case where the TFT is provided with an offset region as described in 31188 or Japanese Patent Application No. 3-238713, the effect is weak if the characteristics (grain boundaries, etc.) between crystals are not good. This is because the cause of the backward leakage is due to the level existing at the grain boundary as described above, so it does not make much sense to provide an offset region in a semiconductor with poor grain boundary properties. Of.

That is, Japanese Patent Application No. 3-231188,
Alternatively, in order to implement the invention of providing an offset region as described in Japanese Patent Application No. 3-238713, sufficient attention must be paid to the characteristics of the semiconductor.
In that sense, it is synergistic to carry out the method of the present invention such that the portion having poor characteristics (the active layer portion on the substrate side) does not substantially function as a channel.

In the above description, only a TFT having a simple source / drain or an TFT having an offset region is dealt with, but a TFT having a known low-concentration drain (LDD) structure may be used. .. further,
This LDD structure is also manufactured by a normal method, and is also an invention of the present inventors, for example, Japanese Patent Application No. 3-23871.
0 to 3-238712. Hereinafter, the present invention will be described with reference to examples.

[0034]

EXAMPLES Example 1 FIG. 4 shows a CMO using the present invention.
An example of producing S will be described. In this example, a No. 7059 glass substrate manufactured by Corning Inc. was used as the substrate 401.
A silicon nitride film 402 having a thickness of 20 to 100 nm, for example 50 nm, was formed on the substrate 401 by an RF plasma CVD method in order to prevent entry of mobile ions from the substrate. Further, a silicon oxide film 403 having a thickness of 20 to 100 nm, for example 50 nm, was formed on the silicon nitride film by the RF plasma CVD method. The thickness of these films is designed according to the degree of penetration of mobile ions or the influence on the active layer.

For example, if the quality of the silicon nitride film 402 is not good and there are many charge traps, it affects the upper semiconductor layer through the silicon oxide film. In that case, it is necessary to thicken the silicon oxide film. ..

The coatings may be formed not only by the plasma CVD method as described above but also by a method such as a low pressure CVD method or a sputtering method. The selection of these means may be determined in consideration of the scale of investment and mass productivity. Needless to say, these coatings may be continuously formed.

Further, a photoresist 404 was applied, and using this as a mask, a P-type region 406 and an N-type region 405 were formed. Boron is used as the P-type impurity, and it is 5 × 10.
¹² to 1 × 10 ¹⁴ cm ^-2 , for example, 2 × 10 ¹³ cm ^-2 ,
It was implanted by the ion doping method. Accelerating voltage is 10 ke
It was set to V. Further, phosphorus is used as the N-type impurity, and
× 10 ¹² to 1 × 10 ¹⁴ cm ^-2 , for example 5 × 10 ¹³ cm ^-2
Only, it was injected by the ion doping method. Accelerating voltage is 1
It was set to 0 keV. The acceleration voltage and the dose amount are determined in consideration of the film thickness of the silicon oxide film 403, the diffusion coefficient of each impurity due to the subsequent heat treatment, and the like. In this embodiment, since the so-called through implantation is not used, the acceleration voltage may be low. Thus, the state of FIG. 4 (A) was obtained.

After that, a thickness of 20 is obtained by the low pressure CVD method.
An amorphous silicon film having a thickness of 200 nm, for example 100 nm, was formed. Monosilane was used as the raw material, and the substrate temperature was 550 ° C. As a result of studies by the present inventors, it was revealed that the substrate temperature has an important influence on the subsequent crystallization. For example, it was difficult to crystallize a film formed from monosilane as a raw material at 480 ° C. or lower. On the other hand, when the film is formed using disilane as a raw material, the substrate temperature is
Even the film formed at 0 ° C. was sufficiently crystallized by annealing at 600 ° C. The amorphous silicon film thus obtained was thermally annealed at 600 ° C. for 24 hours to be crystallized to obtain crystalline silicon called so-called semi-amorphous silicon. At this time, the impurities (boron, phosphorus) implanted in the silicon oxide film 403 were thermally diffused into the silicon layer. In the research conducted by the present inventors, the above-described annealing formed a diffused impurity region in the lower portion of the crystalline silicon layer at a thickness of about 30 nm.

Further, in order to promote crystallization, it is desirable that the concentration of carbon, nitrogen and oxygen in the silicon film is 7 × 10 ¹⁹ cm ⁻³ or less. In this example, SIMS analysis yields 1 ×.
It was confirmed to be 10 ¹⁷ cm ⁻³ or less.

In the conventional TFT, the silicon oxide film 40 is used.
Since the active layer of the semiconductor film is formed on the surface of No. 3, it has been necessary to be very careful in its production. For example, the presence of mobile ions in the silicon oxide film 403 should never have occurred, but the presence of trap levels was even more fatal. Mobile ion penetration could be solved to some extent by process cleaning, but the trap level problem could not be improved beyond a certain level due to process restrictions. In particular, the interface state density between the silicon oxide film and the semiconductor active layer on it is determined by the TFT
It was an important factor that influences the characteristics of. The level density at the interface between a thermal oxidation gate oxide film (silicon oxide) used in a normal single crystal semiconductor MOSIC and the single crystal semiconductor is 1
Although it was about 0 ¹⁰ cm ^-2 , for example, the plasma CVD method or the atmospheric pressure CVD method (APCVD as in this embodiment).
Method) or low pressure CVD method (LPCVD method), and the interface state density between the silicon oxide film and the polycrystalline silicon film thereon is 10 ¹² cm ⁻² or more, which is not very practical.

That is, when the interface state density is high in this way, various charges are trapped, and the conductivity type of the active layer is determined by these charges without depending on the gate voltage, which increases the leak current. invited. Therefore, conventionally, even such an underlying oxide film has been required to have the same high quality as that of the gate oxide film. For low-temperature processes and medium-temperature processes where the thermal oxidation method cannot be adopted, the sputtering method and the ECR plasma CVD method were adopted, but the level density at the interface obtained by these methods is one digit higher than that of the thermal oxidation method. It was a big one.

However, according to the present invention, in the subsequent process, the portion of the semiconductor film on the silicon oxide film 403 which is in contact with the silicon oxide film has a conductivity type different from that of the source / drain regions due to the addition of impurities. The things that are said to occur rarely occur. That is, no matter what trap level exists in the silicon oxide film 403 and what kind of charge is trapped, impurities are introduced into the semiconductor film and the conductivity type is determined in advance. The conductivity type of the semiconductor film does not depend on the charge trap. According to the study by the present inventors, if the impurity concentration of the impurity region formed by diffusion at the time of thermal annealing is 10 ¹⁸ cm ⁻³ , the interface level between the silicon oxide film 403 and the crystalline silicon film thereabove. The unit density is 5 × 10 ¹² c
It turns out that there is no problem up to about m ^-2 . Silicon oxide film 4
The impurity concentration of the crystalline silicon film formed on the silicon oxide film 03 is determined by the balance with the impurity concentration of the source / drain regions to be formed later.
The higher the impurity concentration of the semiconductor region on 03, the looser the condition for the interface state density. The impurity concentration of the source / drain region is 10 ²⁰
Since it is possible to reach cm ^−3, the impurity concentration of the semiconductor concentration can be up to about 10 ¹⁹ cm ⁻³ . In this case, a calculated interface density of 10 ¹³ cm ^-3 is allowed.

Therefore, the above-described RF plasma CV
The silicon oxide film can be formed by the D method or another simple CVD method. RF plasma CVD method and LPCV
D method and APCVD method are sputtering method and ECR plasma C
It is a method that is superior in mass productivity to the VD method. That is,
Since the batch method cannot be adopted in the sputtering method, mass productivity is poor, and great care must be taken to prevent mobile ions from adhering to the target. Further, the size of the target cannot be unnecessarily increased, which is unsuitable for increasing the area. The ECR plasma CVD method requires a large amount of investment in the apparatus, and also has a large restriction on the number and size of substrates that can be processed at one time.

After the amorphous silicon film is formed into a crystalline silicon film by thermal annealing, the crystalline silicon film is etched into an appropriate pattern to form an island-shaped semiconductor region 408 for NTFT and an island-shaped semiconductor region 407 for PTFT. Form. At this time, the P-type region 41 is formed below each semiconductor region due to the diffusion of impurities during the thermal annealing.
0 and an N-type region 409 are formed. The top of each island semiconductor region was substantially intrinsic.

Then, a gate insulating film (silicon oxide) 411 having a thickness of 100 to 200 nm, for example 150, is formed by a sputtering method targeting silicon oxide in an oxygen atmosphere.
Only nm is formed. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum film having a thickness of 500 nm was formed by a sputtering method, and this was patterned with a mixed acid (phosphoric acid solution containing 5% nitric acid) to form gate electrodes / wirings 413 and 412. The etching rate is 2 when the etching temperature is 40 ° C.
It was 25 nm / min. In this way, the outer shape of the TFT was adjusted. At this time, the size of each channel was 8 μm in length and 20 μm in width. The size of the channel may also be designed according to the operating characteristics of the device. The state at this time is shown in FIG.

Further, aluminum oxide was formed on the surface of the aluminum wiring by the anodic oxidation method. As the method of anodic oxidation, Japanese Patent Application No. 3-23, which is an invention of the present inventors, is used.
The method described in 1188 or Japanese Patent Application No. 3-238713 was used. The detailed mode of implementation may be changed according to the characteristics of the target element, process conditions, investment scale, and the like. In this embodiment, the aluminum oxide films 415 and 41 having a thickness of 350 nm are formed by anodic oxidation.
4 was formed.

After that, an N-type source / drain region 417 and a P-type source / drain region 416 were formed by a known CMOS fabrication technique by an ion implantation method through a gate oxide film. In both cases, the impurity concentration is 8 × 10 ¹⁹ c
It was set to m ^-3 . As the ion source, boron fluoride ions were used for the P type and phosphorus ions for the N type, and the former was implanted at an accelerating voltage of 80 keV and the latter was implanted at an accelerating voltage of 110 keV. The acceleration voltage depends on the thickness of the gate oxide film and the semiconductor region 4.
It is set in consideration of the thicknesses of 07 and 408. An ion doping method may be used instead of the ion implantation method. In the ion implantation method, the implanted ions are separated by mass, so unnecessary ions are not implanted.
The size of the substrate that can be processed by the ion implantation apparatus is limited. On the other hand, the ion doping method has the ability to process a relatively large substrate (for example, a diagonal of 30 inches or more), but since hydrogen ions and other unnecessary ions are simultaneously accelerated and implanted, the substrate is heated. Cheap. In this case, it is difficult to selectively implant impurities using a photoresist as a mask, which is used in the ion implantation method.

In this way, a TFT having an offset region was manufactured. This is shown in FIG. 4 (C). Finally, the source / drain regions were recrystallized by laser annealing using the gate electrode portion as a mask. The conditions of layer annealing are, for example, Japanese Patent Application No. 3-23.
The method described in 1188 or 3-238713 was used. Then, as the interlayer insulator 420, silicon oxide is formed by the RF plasma CVD method, holes for forming electrodes are formed in this, and aluminum wirings 421 to 423 are formed,
The device is completed.

In this embodiment, the impurity region 409 formed by the impurities diffused from the silicon oxide film 403 first,
Although the impurity concentration of 410 is about 10 ¹⁸ cm ⁻³ , the concentration of the impurities injected for the formation of the source / drain was 80 times as high as that, so that the initial impurity region 409 as shown in FIG. , 410 have been converted into the same conductivity type as the source / drain except for the portion under the channel, that is, the regions 418 and 419 in FIG. As a result, the thickness of the source / drain is the island-shaped semiconductor region 40.
8 and 408. However, the substantial channel thickness is about 70
It was thinner than the source / drain region such as nm. As a result, the sheet resistance of the source / drain was small, and the excellent characteristics that the OFF current was small due to the thin channel were able to be exhibited.

Example 2 FIG. 5 shows an NT using the present invention.
An example of manufacturing FT and PTFT will be shown. In this embodiment, a N-0 glass substrate manufactured by Nippon Electric Glass Co., Ltd. is used as the substrate 501. The N-0 glass substrate has a glass transition point higher by about 150 ° C. than Corning 7059 used in Example 1, and is also effective for annealing at 650 ° C. to 750 ° C. However, since the amount of mobile ions contained in the substrate is large, it is necessary to take sufficient measures against it. A silicon nitride film 502 with a thickness of 50 nm is formed on the substrate 501 by RF for the purpose of blocking the entry of mobile ions from the substrate.
It was formed by the plasma CVD method. Further, a 100-nm-thick silicon oxide film 503 was formed over the silicon nitride film by an RF plasma CVD method.

Further, boron is added by the low pressure CVD method.
Amorphous silicon film 5 containing only x10 ¹⁸ cm ^-3
04 was formed to a thickness of 10 to 50 nm, for example, 30 nm. Then, a photoresist 506 was applied, and phosphorus was implanted by, for example, 5 × 10 ¹⁸ cm ^{−2 by an} ion doping method using this as a mask to form an N-type region 505. That is, boron was initially contained in an amount of 2 × 10 ¹⁸ cm ⁻³ , but the effect is canceled by the doping of phosphorus, and the region 505 is converted to N type. The acceleration voltage at this time was 10 keV. In this way, the state of FIG.

After that, a thickness of 10 is obtained by the low pressure CVD method.
An amorphous silicon film containing no impurities of about 150 nm, for example, 10 nm was formed. The substrate temperature was 550 ° C. As was the case with the amorphous silicon film 504, it is necessary to pay sufficient attention to the intrusion of impurities. In any of the amorphous silicon films, it is desirable that the concentration of carbon, nitrogen, and oxygen in the film is 7 × 10 ¹⁹ cm ⁻³ or less, and in this embodiment, it is 1 × 10 ¹⁷ cm ⁻³ or less. did. The two-layer amorphous silicon film thus obtained was thermally annealed at 600 ° C. for 24 hours to be crystallized to obtain crystalline silicon so-called semi-amorphous silicon.

After the amorphous silicon film is formed into a crystalline silicon film by thermal annealing, the crystalline silicon film is etched into an appropriate pattern to form an island-shaped semiconductor region 507 for NTFT and an island-shaped semiconductor region 508 for PTFT. Form. The top of each island semiconductor region was substantially intrinsic.

After that, a gate insulating film (silicon oxide) 509 having a thickness of 150 nm was formed by a sputtering method targeting silicon oxide in an oxygen atmosphere. This thickness is determined by the operating conditions of the TFT and the like.

Next, phosphorus was added to 1.2 by the low pressure CVD method.
A silicon film containing x 10 ²⁰ cm ^{-3 is} formed to a thickness of 500 nm and is patterned to form a gate electrode / wiring 5
10 and 511 were formed. In this way, the TFT
The outer shape of At this time, the size of each channel was 8 μm in length and 20 μm in width. The state at this time is shown in FIG.

Thereafter, as shown in FIG. 5C, boron was implanted by an ion implantation method through a gate oxide film. The acceleration voltage at this time was 100 keV, and the boron concentration was 5 × 10 ¹⁹ cm ^-2 . Thus, the source / drain regions 512 of the PTFT on the left side of the drawing were formed. At this time, at the same time, the channel region 514 and the N-type region 515 thereunder are also formed. On the other hand, NT on the right side of the figure
Boron is doped into the FT and the source / drain.
However, at this stage, an impurity region that functions as a TFT is not formed.

Further, a photoresist 513 is applied,
This selectively covers only the PTFT (see FIG.
(D)), and phosphorus was ion-implanted in this state. The acceleration voltage was 100 keV. In this way NTF
A T source / drain region 516 was formed. The phosphorus concentration was set to 1.1 × 10 ²⁰ cm ⁻³ . At the same time, the channel region 517 and the P-type region 518 thereunder are also formed.

After that, annealing was performed at 600 ° C. for 24 hours to recover the damage given by the ion implantation. In the TFT thus obtained, for example, focusing on how the region 505 of the PTFT changed after that, although it was initially N type because it contained 5 × 10 ¹⁸ cm ⁻³ of phosphorus. , Then one more digit than that,
Since boron was injected, it was converted to P type. On the other hand, NTF
Focusing on the area under the channel of T, initially 2 × 10
It was a P type containing ¹⁸ cm ^-3 of boron. After that, by further implanting boron as shown in FIG. 5C, the concentration of boron was increased to 5 × 10 ¹⁹ cm ⁻³ . However, FIG.
By the phosphorus injection of (D), phosphorus was injected at a concentration more than double the concentration of boron and converted to N type. In this example, as is apparent from the figure, the thickness of the source / drain was 40 nm, while the thickness of the channel portion was 10 nm. Further, the impurity regions 515 and 518 do not function as channels. Therefore, an ideal TFT could be formed.

Further, in the present embodiment, the number of masks used is four for forming the region 505, forming the island regions 507 and 508, forming the gate electrodes / wirings 510 and 511, and patterning the photoresist 513. , Then a further mask is used to form the metal wiring.

On the other hand, in the method of the first embodiment, the number of masks used at the same stage as that of this embodiment, that is, up to the formation of the source / drain regions is as follows. Formation of 407 and 408,
Six masks are required to form the gate electrodes / wirings 412 and 413, the source / drain 416 (or 417), and the source / drain 417 (or 416). As described above, this embodiment is effective in simplifying the process and improving the yield accordingly.

[Embodiment 3] This embodiment shows an example in which the present invention is applied to a TFT formed on a semiconductor integrated circuit formed on a single crystal semiconductor substrate. With the high integration of semiconductor integrated circuits, three-dimensional integrated circuits (three-dimensional integrated circuits) have been developed in which not only the circuits are conventionally developed on the plane of the semiconductor substrate but also the circuits are developed vertically. It was At present, what has been put into practical use is limited to a two-layer transistor structure in which only PMOS is used as a TFT among the transistors of a flip-flop circuit such as a complete CMOS type SRAM. As the degree of integration of integrated circuits has advanced, more multilayer structures have been used. At the same time, TFTs are required to have improved characteristics.

In this embodiment, a case where a first transistor (NMOS) is formed on a single crystal silicon substrate and a second transistor (PMOS) is formed thereon by a TFT will be described.

FIG. 6A shows a semiconductor circuit having such a structure. For simplicity, metal wiring is not shown in the figure. In the figure, a source region 602 and a drain region 603 (both N-type) are provided on a substrate 601, and a gate electrode 604 of the first transistor is further formed. In addition, the interlayer insulator 60 is provided so as to cover these.
5 is formed. Conventionally, a glass material having a relatively low melting point such as phosphorus glass or phosphorus boron glass is used as the interlayer insulator, and by reflowing,
It has been performed to reduce the unevenness caused by the formation of the wiring.

The TFT is formed on such an interlayer insulator. That is, a polycrystalline silicon film having a source region (P type) 606, a drain region (P type) 607, and a channel region 608 is formed on the interlayer insulator 605.
Further, a gate insulating film is formed on this polycrystalline silicon film, and a gate electrode 609 of the second transistor is formed. Finally, the entire element is covered with the insulating film 610.

In the TFT having such a structure, if
When the interlayer insulator is made of a conventional material such as phosphorus glass or phosphorus boron glass, the interlayer insulator 6 is formed by the voltage applied to the gate electrode 604 of the first transistor.
There is a possibility that charge may be trapped in 05 or the interlayer insulator may be polarized. For example, if the charges 612 are trapped on the upper surface of the first gate electrode 604 and the lower surface of the channel region 608 by such an effect, a P-type inversion layer 611 is formed below the channel region 608, and A leak current flows from the source to the drain through the portion.

Therefore, it was necessary to avoid directly forming the channel region on a material such as phosphorus glass or phosphorus boron glass. Ideally, it was required to form an interlayer insulator with a pure silicon oxide film and further form a high-quality silicon oxide film thereon by thermal oxidation.
However, in that case, since silicon oxide, which is a high melting point material, is used as an interlayer insulator, reflow is difficult. Therefore, it is required to form an interlayer insulator using a glass material suitable for performing reflow and to form an oxide film thereon by a low temperature film forming technique such as a sputtering method or an ECR plasma CVD method. Whichever method is adopted, the number of film forming steps is doubled, which leads to a decrease in throughput. In particular, low-grade silicon oxide, phosphorus glass, and the like are formed by the low pressure CVD method, which has good mass productivity, but the sputtering method and the ECR plasma CVD method are inferior in mass productivity. In particular, in order to sufficiently reduce the influence of the electric charge of the lower insulator, the thickness of the high-quality silicon oxide film is 300 n.
m or more is necessary. It takes a very long time to form a silicon oxide film having such a thickness by a sputtering method or an ECR plasma CVD method.

By applying the invention, this problem is solved. An example of the present invention is shown in FIG.
In the figure, a source region 652 and a drain region 653 (both N-type) are provided on a substrate 651, and the first region
The gate electrode 654 of the transistor is formed.
An interlayer insulator 655 is formed so as to cover them. This may be low grade silicon oxide or a material such as phosphorus glass or phosphorus boron glass.

The TFT is formed on such an interlayer insulator. That is, the source region (P type) 656 and the drain region (P type) 657 are formed on the interlayer insulator 655. Although a channel region was conventionally formed between the source / drain, in the present invention, an N-type region 661 is formed on the lower side and a channel region 658 is formed thereon.
Is formed. All of these are polycrystalline silicon coatings. Further, a gate insulating film is formed on this polycrystalline silicon film, and a gate electrode 659 of the second transistor is formed. Finally, the entire element is covered with the insulating film 660.

Whether the material of the interlayer insulator 655 is silicon oxide having excellent heat resistance or the glass material capable of reflowing must be selected according to the characteristics of the element. That is, when a glass-based material is used, it is difficult to form the gate oxide film of the second transistor by thermal oxidation. Therefore, the characteristics are not very good.

The impurity concentration of the N-type region 661, which is a feature of the present invention, is determined in consideration of the impurity concentration of the source / drain, the impurity concentration of the channel region, the characteristics of the underlying interlayer insulator, etc. 1 × 10 ^{17 to} 5 × 1
It is 0 ¹⁹ cm ^-3 . For example, the channel region has 3 × 10
^The source / drain is doped with N-type impurities of ¹⁶ cm ⁻³ , the source / drain is doped with P-type impurities of 6 × 10 ¹⁹ cm ⁻³ , and the interface state density of the interlayer insulator is 2 × 10 ¹² cm ^{−. In} the case of ² , 1 × 10 ^{18 to} 3 × 10 ¹⁹ cm ⁻³ is suitable.

The thickness of the N-type region 661 is determined in consideration of the impurity concentration and the characteristics of the underlying interlayer insulator (in particular, interface state density). Since the electric charge existing in the channel is shielded, it may be thinner than in the case where the channel is directly formed on the interlayer insulating material as described above. There is typically no problem if the thickness is 10 nm or more. For example, the impurity concentration of the N-type region 661 is 3 × 10 ^19.
A thickness of 7 nm is sufficient if a charge of 2 × 10 ¹² cm ⁻² is trapped on the surface of the interlayer insulator at cm ⁻³ . However, if it is too thin, the reliability decreases due to other factors such as nonuniformity of the film thickness.

On the other hand, if it is too thick, the film formation will take a long time. Considering the above, 10 to 100 nm
Is appropriate. In forming such a region, it is desirable to adopt the method shown in the second embodiment.

That is, an N type silicon film is formed on the inter-layer insulator 655, and then an I type or N ⁻ type silicon film is formed. This film formation may be continuously performed by a so-called multi-chamber method. Then, a gate insulating film and a gate electrode are formed, and a source 606 and a drain 607 are formed by a self-alignment process.

[0075]

According to the present invention, a good TFT having an extremely small OFF current when a reverse voltage is applied to the gate.
Was able to be manufactured. The present invention is even more effective when combined with other inventions. For example, as shown in the examples, Japanese Patent Application No. 3-2311, which is the invention of the present inventors.
88 and the Japanese Patent Application No. 3-238713 show further effects. Further, in the present invention, as shown in the embodiments, the thickness of the source / drain can be increased to reduce the sheet resistance thereof. As a result, high speed operation of the TFT circuit could be realized.

Conventionally, the polycrystalline TFT is ON / O for the purpose such as an active matrix of a liquid crystal display device.
Although the FF ratio was low, there were various difficulties in putting it to practical use.
The present invention appears to have largely solved such problems. Further, as shown in Example 3, the present invention can be applied to the three-dimensionalization of a single crystal semiconductor integrated circuit. Thus, the present invention is considered to be an extremely useful invention in industry.

[Brief description of drawings]

FIG. 1 shows a conceptual diagram of a TFT of the present invention.

FIG. 2 shows a conceptual diagram of a conventional TFT.

FIG. 3 shows an example of the characteristics of a TFT of the invention and a conventional TFT, and an expected energy band diagram of the TFT of the invention.

FIG. 4 shows a manufacturing process of a TFT of the present invention.

FIG. 5 shows a manufacturing process of a TFT of the present invention.

FIG. 6 shows an application example of the present invention.

[Explanation of symbols]

 101 ... Substrate 102 ... Drain region 103 ... Channel region 104 ... Source region 105 ... Gate electrode 106 ... Interlayer insulator 107 ... Drain electrode / wiring 108 ... Source electrode・ Wiring 109 ... Impurity region

Claims (12)

[Claims] 1. A source region and a drain region formed on an insulating substrate and having a first conductivity type, and the source / drain region.
An insulating gate type semiconductor device comprising: a channel region sandwiched between drain regions; and a region below the channel region and having a second conductivity type different from the first conductivity type. 2. The insulating gate type semiconductor device according to claim 1, wherein the region under the channel is in close contact with an insulating film containing an impurity of the same kind as the impurity added to the region. 3. The channel region according to claim 1, wherein silicon is a main material, and the concentration of carbon, nitrogen and oxygen is 7 × 10.
An insulated gate type semiconductor device characterized by being ¹⁹ cm ⁻³ or less. 4. A step of forming an insulating coating containing phosphorus or boroso on an insulating substrate, a step of forming a semiconductor coating on the insulating coating having a heat treatment step of at least 500 ° C., and then a gate. A method of manufacturing an insulating gate type semiconductor device, comprising the step of providing an electrode. 5. An N-type or P-type first layer on an insulating substrate.
And a step of forming a second semiconductor film having a substantially intrinsic conductivity type, and then a step of providing a gate electrode. Manufacturing method. 6. A source region, a drain region and the source / drain region.
A thin film insulating gate type semiconductor device having a semiconductor region sandwiched between drain regions, the semiconductor region being composed of at least two semiconductor layers having different electrical characteristics. 7. The semiconductor layer according to claim 6, wherein the one semiconductor layer forming the semiconductor region is made of a semiconductor having a conductivity type different from that of the source / drain regions, and the other semiconductor layer is substantially intrinsic. An insulating gate type semiconductor device characterized by comprising a semiconductor having the above conductivity type. 8. The semiconductor region according to claim 6,
An insulating gate type semiconductor device, characterized in that the source / drain regions sandwiching it have substantially the same thickness. 9. The insulated gate semiconductor device according to claim 6, wherein at least a part of the source / drain regions sandwiching the semiconductor region is activated by laser irradiation. 10. The thickness of the source / drain regions sandwiching the semiconductor region is larger than the thickness of a semiconductor layer of the semiconductor layers forming the semiconductor region, which is in contact with the gate insulating film. Gate type semiconductor device. 11. A semiconductor device having a source region, a drain region, and a semiconductor region sandwiched between the source / drain regions, wherein an impurity concentration in an upper portion of the semiconductor region is lower than an impurity concentration in a lower portion of the semiconductor region, and A thin film insulating gate type semiconductor device characterized in that the conductivity type of the lower part is different from the conductivity type of the source / drain. 12. A silicon oxide film formed by a CVD method, an N-type or P-type crystalline first semiconductor layer on the silicon oxide film, and a substantially intrinsic intrinsic semiconductor on the first semiconductor layer. An insulating gate type semiconductor device having a crystalline second semiconductor layer, a gate oxide film on the second semiconductor layer, and a gate electrode on the gate oxide film.