JPH08167722A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To enhance switching characteristics of an active matrix circuit and to make the high speed operation of a peripheral logic circuit compatible by forming a gate insulating film and a gate electrode on a semiconductor region, and doping first conductivity type impurity of low concentration. CONSTITUTION: A polycrystalline silicon film is formed on the entire substrate, and etched to form gate electrodes 107 to 109. Thereafter, N-type regions 110 to 112 which are weak in a self-alignment manner are formed at all insular active layers by an ion doping method with the gate electrodes as masks. Then, a mask 114 covering from the mask 113 covering a P-channel TFT and the end of the electrode 109 of the active layer of a pixel TFT to the part isolated 3μm from the end of the electrode 109 is formed. Again, strong N-type regions 115, 116 are formed by an ion doping method. A region 117 covered with the pixel mask 14 is not injected with phosphorus by this doping, hence remains as a weak N-type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an integrated circuit in which a large number of insulating gate type semiconductor devices are formed on an insulating substrate with high yield. In particular, the present invention relates to an active matrix in a broad sense (a circuit in which wirings are arranged in a matrix form and one or more switching transistors for signal selection are provided at the intersections thereof) and for driving the same. The present invention relates to an integrated semiconductor integrated circuit (monolithic active matrix circuit) having peripheral circuits on the same substrate. The application example of the present invention is specifically a monolithic active matrix liquid crystal display (A
M-LCD), DRAM, SRAM, EPROM, E
A semiconductor integrated circuit such as an EPROM or a mask ROM, which is formed on an insulating substrate.

[0002]

2. Description of the Related Art Recently, much research has been done on forming an insulating gate type semiconductor device (MISFET) on an insulating substrate. Forming the semiconductor integrated circuit on the insulating substrate in this manner is advantageous for high-speed driving of the circuit. Because
This is because the speed of the conventional semiconductor integrated circuit is limited mainly by the capacitance (stray capacitance) between the wiring and the substrate, but such stray capacitance does not exist on the insulating substrate. The MISFET formed on the insulating substrate and having the thin film-like active layer is called a thin film transistor (TFT).

In particular, recently, a product requiring the formation of a semiconductor integrated circuit on a transparent substrate has appeared. For example, an optical device such as a liquid crystal display. A TFT is also used here. In particular, since these circuits are required to be formed in a large area, it is required to lower the temperature of the TFT manufacturing process. Furthermore, it has been proposed to form peripheral logic circuits for driving the active matrix circuit monolithically on the same insulating substrate.

However, in a normal TFT,
Due to a large leak current in the off state, it can be used as a switching transistor of an active matrix circuit or a driver TFT (switching transistor) provided to connect a peripheral logic circuit and an active matrix circuit in a monolithic active matrix circuit. Was pointed out to have problems with reliability. Against this background, Japanese Patent Publication No. 3875
As shown in FIG. 5, it was reported that the leak current can be reduced by providing a low-concentration region adjacent to the source / drain. This is an LD used in semiconductor integrated circuit technology.
It was described as equivalent to D.

[0005]

However, the TFT
Since a non-single crystal semiconductor having much more defects than a single crystal semiconductor is used, the LDD of a semiconductor integrated circuit is used.
It is not appropriate to use On the other hand, in the above invention, the optimum width of the low concentration impurity region is not described. Further, in particular, in manufacturing a monolithic active matrix circuit, no whole process is shown, and the peripheral logic circuit has a TFT of any structure.
It also lacked a description as to whether or not it is preferable to configure with.

For example, according to the research conducted by the present inventor, in a peripheral logic circuit that requires high-speed response, the provision of a low-concentration impurity region functioning as a series resistor inserted between the source / drain increases the operating speed. There was a failure in point. The present invention has been made to solve the above problems, and an object thereof is to provide a manufacturing method for obtaining a preferable circuit configuration.

[0007]

The present invention basically has the following steps. That is, (1) a step of forming a plurality of island-shaped semiconductor regions for active matrix circuits and peripheral logic circuits (2) a step of forming a gate insulating film and a gate electrode on the semiconductor regions (3) all of the above Step of doping a semiconductor region with an impurity of a first conductivity type at a low concentration (4) A TFT of a second conductivity type in the semiconductor region
Of the first conductivity type is formed by covering a part of the active matrix circuit and a part of the active matrix circuit (pixel TFT in AM-LCD) and a part adjacent to the channel of the driver TFT. (5) First conductivity type TFT in the semiconductor region
And a mask is formed so as to cover the portion constituting
Is a P-type if the conductivity type is N-type, and N-type if the conductivity type is P-type).

In the steps (3) to (5), bare doping (a method of exposing the semiconductor region and performing doping) is carried out even by through doping (a method of doping while the semiconductor region is covered with a gate insulating film). But it's okay. Further, in the step (4), the width of the mask formed to cover the TFT constituting the active matrix circuit and the portion adjacent to the gate electrode of the driver TFT is preferably 1 to 5 μm.

The impurity concentration of the first conductivity type region formed in the step (3) is the same as that of the first conductivity type region formed in the step (4).
So that it is lower than the impurity concentration of the conductivity type region of
Further, it is desirable that the impurity concentration of the first conductivity type region formed in the step (3) be lower than the impurity concentration of the second conductivity type region formed in the step (5). . The order of steps (4) and (5) may be interchanged.

[0010]

The steps (1) and (2) are steps for manufacturing a general top gate type TFT. By the step (3),
Using the gate electrode as a mask, low-concentration impurity regions are formed in all semiconductor regions in a self-aligned manner. In the step (4), the source / drain of the first conductivity type TFT is formed. At that time, in the TFT and the driver TFT forming the active matrix circuit, the mask between the source / drain and the channel is formed. Since the doped region is not doped, the low concentration impurity region formed in step (3) is maintained. That is, a low concentration impurity region can be provided adjacent to the source / drain, and the leak current can be reduced in these TFTs.

According to the study by the present inventor, the width of the low concentration impurity region is 1 to 5 μm, typically 3 μm,
A sufficient leakage current suppressing effect could be obtained. Below that, the leak current was large, and above that, the current in the ON state was small, which hindered the TFT operation. According to the research conducted by the present inventor, a sufficient leakage current suppressing effect can be obtained when the width of the low concentration impurity region is 1 to 5 μm, typically 3 μm. Below that,
The leakage current was large, and above that, the current in the ON state was small, which hindered the TFT operation.

On the other hand, in other TFTs, that is, in the TFTs forming the peripheral logic circuit, the low concentration impurity region is not formed. Therefore, although these TFTs have a large amount of leak current, they also have a large amount of on-current and were suitable for high-speed operation. Since these TFTs mainly perform a digital operation, they do not enter the off state, and therefore the leak current in the off state does not pose any problem.

In step (5), an impurity of a second conductivity type opposite to the first conductivity type is doped. At this time, the second
The conductivity type is inverted from the first conductivity type to the second conductivity type by increasing the conductivity type doping amount (dose amount) of the first conductivity type in the step (3). The second conductivity type TFT is limited to the TFT in the peripheral logic circuit area.
The second conductivity type TFT does not have a low concentration impurity region. As a result, the leak current is large, but there is no problem when it is used for the peripheral logic circuit, as described above.

[0014]

【Example】

[Embodiment 1] This embodiment relates to a method of manufacturing a liquid crystal display substrate using a monolithic active matrix circuit. Hereinafter, a manufacturing process for obtaining the monolithic active matrix circuit of this embodiment will be described with reference to FIGS. The left side of the drawing shows the manufacturing process of the TFT of the peripheral logic circuit, and the right side shows the manufacturing process of the TFT of the active matrix circuit. First, a silicon oxide film having a thickness of 1000 to 3000 Å was formed as a base oxide film 102 on a quartz substrate 101. As a method of forming this silicon oxide film, a sputtering method in an oxygen atmosphere or a plasma CVD method may be used.

After that, an amorphous or polycrystalline silicon film is formed by plasma CVD or LPCVD.
It was formed in the range of 00 to 1500Å, preferably 500 to 1000Å. And 500 degreeC or more, Preferably it is 800-9.
Thermal annealing was performed at a temperature of 50 ° C. to crystallize the silicon film or enhance the crystallinity. After crystallizing by thermal annealing, optical annealing is performed,
Further, the crystallinity may be increased. In addition, when crystallizing by thermal annealing, Japanese Patent Laid-Open Nos. 6-244103 and 6-244
As described in 104, an element (catalyst element) that promotes crystallization of silicon such as nickel may be added.

Next, the silicon film is etched to form an active layer 103 (P-channel T-channel) of the TFT of the island-shaped peripheral drive circuit.
FT), 104 (for N-channel type TFT) and active layers 105 of TFTs (pixel TFTs) of the matrix circuit were formed. Further, a gate insulating film 106 of silicon oxide having a thickness of 500 to 2000 Å is formed by a sputtering method in an oxygen atmosphere.
Was formed. A plasma CVD method may be used as a method for forming the gate insulating film. When the silicon oxide film is formed by the plasma CVD method, it is preferable to use dinitrogen monoxide (N ₂ O) or oxygen (O ₂ ) and monsilane (SiH ₄ ) as the source gas.

After that, a polycrystalline silicon film having a thickness of 2000 Å to 5 μm, preferably 2000 to 6000 Å (containing a trace amount of phosphorus for enhancing conductivity) was formed on the entire surface of the substrate by the LPCVD method. Then, this was etched to form gate electrodes 107, 108, and 109.
(FIG. 1 (A)) After that, phosphorus was injected into all the island-like active layers by ion doping in a self-aligning manner using phosphine (PH ₃ ) as a doping gas with the gate electrode as a mask.
The dose amount was set to 1 × 10 ^{12 to} 5 × 10 ¹³ atoms / cm ² . As a result, weak N-type regions 110, 111, 112 were formed. (Fig. 1 (B))

Next, the active layer 103 of the P-channel type TFT.
Mask 113 of the photoresist covering the pixel T and the pixel T
A photoresist mask 114 was formed to cover the active layer 105 of the FT in parallel with the gate electrode up to a portion 3 μm away from the end of the gate electrode 109. Then, again, phosphorus was injected by the ion doping method using phosphine as a doping gas. Dose amount is 1 × 10 ^{14 to} 5 ×
It was set to 10 ¹⁵ atoms / cm ² . As a result, strong N-type regions (source / drain) 115 and 116 were formed. Of the weak N-type region 112 of the active layer 105 of the pixel TFT,
The region 117 covered with the mask 114 remained weak N-type because phosphorus was not implanted in this doping. (Fig. 1 (C))

Next, the active layer 10 of the N-channel type TFT.
4, 105 were covered with a photoresist mask 118, and boron was implanted into the island region 103 by an ion doping method using diborane (B ₂ H ₆ ) as a doping gas.
The dose amount was 5 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² . In this doping, the dose amount of boron is as shown in FIG.
Since the dose amount of phosphorus in the above was exceeded, the weak N-type region 110 previously formed was inverted to the strong P-type region 119. By the above doping, a strong N-type region (source /
Drains) 115 and 116, strong P-type regions (source / drain) 119, weak N-type regions (low concentration impurity regions) 1
17 is formed, and in this embodiment, the low concentration impurity region 11 is formed.
The width x of 7 was about 3 μm larger than the size of the photoresist mask 114. (Fig. 1 (D))

Thereafter, thermal annealing was performed at 450 to 850 ° C. for 0.5 to 3 hours to recover the damage caused by the doping, activate the doping impurities, and recover the crystallinity of silicon. After that, a silicon oxide film having a thickness of 3000 to 6000 Å was formed on the entire surface as an interlayer insulator 120 by a plasma CVD method. This may be a silicon nitride film or a multilayer film of a silicon oxide film and a silicon nitride film. Then, the interlayer insulator 120 was etched by a wet etching method to form contact holes in the source / drain.

Then, a thickness of 200 is obtained by the sputtering method.
A titanium film of 0 to 6000 Å was formed, and this was etched to form electrodes / wirings 121, 122, 123 of the peripheral circuit and electrodes / wirings 124, 125 of the pixel TFT. Further, by the plasma CVD method, the thickness of 1000
A silicon nitride film 126 of up to 3000 Å was formed as a passivation film, and this was etched to form a contact hole reaching the electrode 125 of the pixel TFT. Finally, the I film having a thickness of 500 to 1500 Å was formed by the sputtering method.
The TO (indium tin oxide) film was etched to form the pixel electrode 127. In this way, the peripheral logic circuit and the active matrix circuit could be integrally formed. (Fig. 1 (E))

[Embodiment 2] This embodiment also relates to a liquid crystal display substrate using a monolithic active matrix circuit. Hereinafter, a manufacturing process for obtaining the monolithic active matrix circuit of this embodiment will be described with reference to FIGS. First, the substrate (Corning 7059) 101
As the underlying oxide film 102, a 2000 Å-thick silicon oxide film and a 500 Å-thick amorphous silicon film were continuously formed by plasma CVD. Then, the silicon film was crystallized by a method of irradiating a laser or strong light equivalent thereto (optical annealing method). In this embodiment, a KrF excimer laser (wavelength 24
8 nm) was used. The optimum energy density of the laser was 350 to 550 mJ / cm ² .

Next, the silicon film is etched to form the active layer 203 (P-channel type TF) of the TFT of the peripheral drive circuit.
T), 204 (N-channel type TFT) and the active layer 205 of the pixel TFT of the matrix circuit. Further, as raw material gas, dinitrogen monoxide (N ₂ O) or oxygen (O 2
₂ ) and plasma CVD using monsilane (SiH ₄ )
The gate insulating film 206 was formed by a thermal CVD method or a thermal CVD method.

Thereafter, an aluminum film (0.1 to 5 .mu.m thick, preferably 2000 to 6000 .mu.m) (0.1 to 5 .mu.m) is formed.
0.5% by weight of scandium) was formed on the entire surface of the substrate by the sputtering method. Then, this was etched to form gate electrodes 207, 208, and 209. (Fig. 2 (A))

Then, the substrate was placed in an electrolytic solution, and an electric current was applied to each gate electrode to anodize the gate electrode. As the anodizing conditions, the conditions shown in JP-A-5-267667 were used. As a result, the gate electrodes 207 to 20
9 on the top and side surfaces of anodic oxide coatings 210, 211,
212 was obtained. Although the thickness of the anodic oxide depends on the applied voltage, it is 2000 Å in this embodiment.

Thus, the anodic oxide obtained by anodic oxidation in a substantially neutral solution is dense and hard and has a high withstand voltage.
The breakdown voltage is 70% or more of the maximum voltage applied during anodic oxidation. Such an anodic oxide is called a barrier type anodic oxide. After that, phosphorus was injected into all the island-like active layers by ion doping in a self-aligning manner with phosphine as a doping gas, using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask. The dose amount was 1 × 10 ¹³ atoms / cm ² . As a result, weak N-type regions 213, 214, and 215 were formed. (FIG. 2 (B))

Next, the active layer 203 of the P-channel type TFT.
Mask 216 of photoresist covering the pixel T and the pixel T
A photoresist mask 217 was formed so as to cover the active layer 205 of the FT in parallel with the gate electrode up to a portion 2 μm away from the end of the gate electrode 209. Then, again, phosphorus was injected by the ion doping method using phosphine as a doping gas. Dose amount is 5 × 10 ¹⁴ atoms /
It was set to cm ² . As a result, strong N-type regions (source / drain) 218 and 219 were formed. Of the weak N-type region 215 of the active layer 205 of the pixel TFT, the region 220 covered by the mask 217 remained weak N-type because phosphorus was not implanted in this doping. (Fig. 2
(C))

Next, the active layer 20 of the N-channel type TFT.
4, 205 were covered with a photoresist mask 221, and boron was implanted into the island region 203 by an ion doping method using diborane as a doping gas. Dose amount is 1
It was set at × 10 ¹⁵ atoms / cm ² . In this doping, since the dose amount of boron exceeds the dose amount of phosphorus in FIG. 2C, the weak N-type region 213 previously formed is inverted into the strong P-type region 222.

By the above doping, strong N-type regions (source / drain) 218, 219, strong P-type regions (source / drain) 222, and weak N-type region (low-concentration impurity region) 220 are formed. Then, the width y of the low-concentration impurity region 220 is determined by the mask 11 of the photoresist.
It was about 2 μm from the size of No. 4. In the present embodiment, the source / drain (in the case of the pixel TFT, the low concentration impurity region 22) is formed by the thickness z (≈2000Å) of the anodic oxide.
0) and the gate electrode are separated from each other in an offset structure. (Fig. 2 (D))

After that, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to introduce the above-mentioned impurity region to improve the crystallinity of the portion where the crystallinity was deteriorated. Laser energy density is 200
To 400 mJ / cm ² , preferably 250 to 300 mJ
/ Cm ² . As a result, the N-type and P-type regions were activated. The sheet resistance of these areas is 200-800.
It was Ω / □. Then, a silicon oxide film having a thickness of 300 is formed on the entire surface as an interlayer insulator 223 by a plasma CVD method.
0-6000Å formed. Then, the interlayer insulator 223 was etched by a wet etching method to form contact holes in the source / drain.

Then, a thickness of 200 is obtained by the sputtering method.
A chrome film of 0 to 6000 Å was formed, and this was etched to form electrodes / wirings 224, 225, 226 of the peripheral circuit and electrodes / wirings 227, 228 of the pixel TFT. Further, by the plasma CVD method, the thickness of 1000
A silicon nitride film 229 of ˜3000 Å was formed as a passivation film, and this was etched to form a contact hole reaching the electrode 228 of the pixel TFT. Finally, the I film having a thickness of 500 to 1500 Å was formed by the sputtering method.
The TO (indium tin oxide) film was etched to form the pixel electrode 230. In this way, the peripheral logic circuit and the active matrix circuit could be integrally formed. (Fig. 2 (E))

In the TFT of this embodiment, an anodic oxide is formed on the upper surface and the side surface of the gate electrode and wiring (not shown in the figure) in the same plane as the gate electrode. With such a structure, the gate electrode and the source / drain can have an offset gate structure, and the leak current between the source / drain can be reduced. (JP-A-5-114724 and JP-A-5-267667)

Further, by forming an anodic oxide (particularly a barrier type anodic oxide) on the upper surface of the gate electrode, the insulation between layers is strengthened, and it has become possible to remarkably reduce the short circuit at the wiring intersection. That is, since the barrier type anodic oxide coating has few pinholes and has a very high withstand voltage (7 MV / cm or more), it is possible to reliably insulate the interlayer between the gate wiring and the wiring thereabove. By actually adopting the technology of Japanese Patent Laid-Open No. 5-114724 or 5-267667, it was possible to significantly reduce defects due to short circuits between wirings. In the active matrix region, it is particularly important because there are so many intersections of wiring.

In the case of anodizing the gate electrode as in this embodiment, as the material thereof, in addition to aluminum, a material containing tantalum, titanium or the like as a main component can be used. Further, when aluminum is used as the gate electrode material, if scandium is contained as in the present embodiment, or if yttrium is contained in an amount of 0.1 to 0.5% by weight, anodic oxidation proceeds gently. Is desirable.

[Embodiment 3] This embodiment is also a monolithic active matrix circuit for a liquid crystal display. The manufacturing process of this embodiment is shown in FIGS. First, plasma CV is applied to the substrate (Corning 1737) 301.
A base silicon oxide film 302 having a thickness of 2000 Å was formed by the D method. After that, a thickness of 50 is formed by plasma CVD.
A 0Å amorphous silicon film was formed. Furthermore, an extremely thin (estimated to be 40 to 100 Å) silicon oxide film was formed on the surface of the amorphous silicon film by thermal annealing at 550 ° C. for 1 hour in an oxidizing atmosphere. Then, an extremely thin film of nickel acetate was formed by spin coating. Here, 1-100p
A pm nickel acetate aqueous solution was used. The thin silicon oxide film was first formed on the surface of the amorphous silicon film so that the aqueous solution can be uniformly spread on the surface of the amorphous silicon film.

Next, thermal annealing was performed at 550 ° C. for 4 hours in a nitrogen atmosphere. Nickel acetate decomposes into nickel at about 400 ° C., but since the nickel acetate thin film is in close contact with the amorphous silicon film, nickel penetrates into the amorphous silicon by this thermal annealing process and crystallizes it. It became a crystalline silicon region. Then, the silicon film was irradiated with XeCl excimer laser light (wavelength 308 nm). In this embodiment, the energy density of the laser is 250 to 300 mJ /
It was set to cm ² . As a result, the crystallinity of crystalline silicon was further improved.

Further, in order to alleviate the stress strain due to laser irradiation, thermal annealing was performed again. In this embodiment, thermal annealing is performed at 550 ° C. for 4 hours. Then, the silicon film is etched to form an island-shaped active layer 303.
(Peripheral circuit P-channel TFT), 304 (Peripheral circuit N-channel TFT), and 305 (Pixel TFT) were formed. Then, by the sputtering method, the thickness is 1200Å
Was formed as a gate insulating film.

Further, the thickness is 4000 by the sputtering method.
An aluminum film of Å (containing 0.2 to 0.3% by weight of scandium) was formed. Then, the surface thereof was anodized to form an aluminum oxide film (not shown) having a thickness of 100 to 300Å. Due to the presence of the aluminum oxide film, the adhesion to the photoresist is good, and by suppressing the leakage of current from the photoresist, it is possible to form the porous anodic oxide only on the side surface in the subsequent anodic oxidation process. Was effective in. Then, a photoresist (for example, OFPR800 /
30 cp) was formed by spin coating. This is patterned and etched to form gate electrodes 307 and 3
08 and 309 were formed. The photoresist masks 310, 311, and 312 used for etching were left as they were. (Fig. 3 (A))

Next, a porous anodic oxide 313 was formed on the side surface of the gate electrode 309 by passing an electric current only through the gate electrode 309 of the pixel TFT with the photoresist mask attached to carry out a porous anodic oxidation. Anodization is 3-2
It may be performed by using an acidic aqueous solution of 0% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 10 to 30 V may be applied to the gate electrode. In this embodiment, p
The voltage was set to 10 V in an oxalic acid solution (30 ° C.) with H = 0.9 to 1.0, and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. When anodic oxidation is performed in such an acidic solution, a porous anodic oxide is produced. In this example, the thickness of the porous anodic oxide was 3000 Å to 5 μm, for example, 1 μm. (Fig. 3
(B))

Further, this time, the photoresist mask is removed, and the gate electrodes 307 to 309 are formed as in the second embodiment.
A barrier type anodic oxidation is performed by applying a current to the gate electrode to form a dense barrier type anodic oxide film 31 on the side surface and the upper surface of the gate electrode.
4, 315 and 316 were formed to a thickness of 1200Å. (Fig. 3
(C) Next, the silicon oxide film 306 was etched by dry etching using the porous anodic oxide 313 and the barrier type anodic oxides 314 to 316 as masks to form gate insulating films 317, 318, and 319. In this etching, even in the plasma mode of isotropic etching,
Alternatively, a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being excessively etched by sufficiently increasing the selection ratio of silicon to silicon oxide. For example, if CF ₄ is used as the etching gas, the anodic oxide is not etched, but only the silicon oxide film 306 is etched. (Fig. 3 (D))

Further, only the porous anodic oxide 313 was etched using a mixed solution of phosphoric acid, acetic acid and nitric acid (aluminum mixed acid). Aluminum mixed acid etches porous anodic oxide, but barely etches barrier type anodic oxide coatings 314-316. Since the porous anodic oxide has a problem in electrical reliability, it needs to be removed.
Although it can be easily etched with aluminum mixed acid as described above, since aluminum mixed acid is also an etchant for aluminum, it is effective to form a barrier type anodic oxide film and cover the aluminum wiring.

Then, using this gate insulating film, phosphorus was introduced into the active layer by an ion doping method. In this example, two-step doping was performed as follows.
First, 5 × 1 with a relatively low acceleration voltage of 10 to 30 keV.
Phosphorus ions were implanted at a low dose of 0 ^{12 to} 5 × 10 ¹³ atoms / cm ² . At this time, because the acceleration voltage is low,
Phosphorus was implanted around the regions 320, 321, and 322 where the ion penetration depth is shallow and silicon is exposed.

Then, phosphorus ions were implanted at a relatively high acceleration voltage of 60 to 95 keV and at an extremely low dose of 1 × 10 ^{12 to} 5 × 10 ¹² atoms / cm ² . At this time, since the acceleration voltage is high, the ions penetrate deeply, and phosphorus is also implanted into the region 323 covered with the gate insulating film. As a result, low concentration phosphorus doped regions (low concentration impurity regions) 320 to 322 and low concentration phosphorus doped regions (extreme low concentration impurity regions) 323 were formed. That is, the pixel TFT could have a so-called double drain structure. (Fig. 3 (E))

Next, the active layer 303 of the P-channel TFT
Mask 324 of the photoresist covering the pixel T and the pixel T
A photoresist mask 325 covering the part of the active layer 305 of the FT parallel to the gate electrode up to a portion 4 μm away from the end of the gate electrode 309 was formed. Then, again, phosphorus was injected by the ion doping method using phosphine as a doping gas. Dose amount is 5 × 10 ¹⁴ atoms /
It was set to cm ² . As a result, in the peripheral logic circuit TFT,
The low-concentration impurity region 321 becomes a strong N-type region (source / drain) 326. Even in the low-concentration impurity region 322 of the active layer 305 of the pixel TFT, the region which is not covered with the mask 325 becomes a strong N-type region 327 by this doping. (Fig. 4 (A))

Next, the active layer 30 of the N-channel type TFT.
4, 305 were covered with a photoresist mask 328, and boron was implanted into the island region 303 by an ion doping method using diborane as a doping gas. Dose amount is 1
It was set at × 10 ¹⁵ atoms / cm ² . A P-type region 329 was formed by this doping.

By the above doping, strong N-type regions (source / drain) 326 and 327, strong P-type regions (source / drain) 329, and low concentration impurity region 32.
2. An extremely low concentration impurity region 323 was formed. Pixel TF
An enlarged view of the impurity region of T is shown in FIG. In this embodiment, the width w of the low concentration impurity region 322 is about 3 times larger than the width of the photoresist mask 325 and the porous anodic oxide.
μm. Similarly, the width of the extremely low-concentration impurity region was determined mainly by the width of the porous anodic oxide and was about 1 μm. Further, in this embodiment, the thickness z of the anodic oxide z (≈1
It should have an offset gate structure of only 200 Å), but it is unclear strictly in this range that there is a wraparound during doping. (Fig. 4 (B))

After that, as a first interlayer insulating film, a silicon nitride film having a thickness of 200 Å and a thickness of 4 are formed by a plasma CVD method.
A multilayer film 330 of a silicon oxide film having a thickness of 000 Å was deposited, and this was etched by a dry etching method to form a contact hole. Then, by the sputtering method, titanium 500Å / aluminum 4000Å / titanium 500
A three-layer metal film of Å was deposited and this was etched to form electrodes / wirings 331, 332, 333, 334, 335.

Further, as a second interlayer insulator, a silicon oxide film 336 having a thickness of 2000 Å is formed by a plasma CVD method.
Was deposited, a contact hole was formed in the drain side electrode 335 of the pixel TFT, and a pixel electrode 337 made of ITO was formed. In this way, a monolithic active matrix circuit could be formed. (Fig. 4
(C))

[0049]

As described above, according to the present invention, it is possible to form a monolithic active matrix circuit in which the switching characteristics of the active matrix circuit and the driver circuit are enhanced and the high speed operation of the peripheral logic circuit is compatible. As described above, the present invention is industrially useful.

[Brief description of drawings]

1 shows a manufacturing process of Example 1. FIG.

FIG. 2 shows a manufacturing process of Example 2.

FIG. 3 shows a manufacturing process of a third embodiment.

FIG. 4 shows a manufacturing process of a third embodiment.

[Explanation of symbols]

 Reference Signs List 101 substrate 102 base film (silicon oxide) 103 to 105 active layer (silicon) 106 gate insulating film (silicon oxide) 107 to 109 gate electrode / gate line 110 to 112 weak N type region 113, 114 photoresist mask 115, 116 Strong N-type region (source / drain) 117 Low concentration impurity region 118 Photoresist mask 119 Strong P-type region (source / drain) 120 Interlayer insulator (silicon oxide) 121 to 125 Metal wiring / electrode 126 Passivation film (silicon nitride) ) 127 pixel electrode (ITO)

Claims (3)

[Claims] 1. An active matrix circuit composed of a first conductivity type thin film transistor (TFT) and first and second conductivity type TFTs on an insulating substrate, and drives the active matrix circuit. And a peripheral logic circuit for the purpose of forming a semiconductor integrated circuit having a driver TFT of the first conductivity type, which is provided to connect the peripheral logic circuit and the active matrix circuit. Forming a plurality of island-shaped semiconductor regions for the matrix circuit and the peripheral logic circuit; (2) forming a gate insulating film and a gate electrode on the semiconductor region; and (3) all the semiconductor regions. And (4) forming a second conductivity type TFT in the semiconductor region. A portion that, over a portion adjacent to the channel of the TFT and the driver TFT constituting the active matrix circuit, a mask,
Doping a first conductivity type impurity, and (5)
A step of forming a mask to cover a portion of the semiconductor region that constitutes the first conductivity type TFT, and doping an impurity of the second conductivity type, the step (3)
The method for manufacturing a semiconductor integrated circuit, wherein the impurity concentration of the first conductivity type region formed in step (4) is lower than the impurity concentration of the first conductivity type region formed in step (4). 2. An active matrix circuit composed of a first conductive type thin film transistor (TFT) and first and second conductive type TFTs on an insulating substrate to drive the active matrix circuit. And a driver TFT which is provided for connecting the peripheral logic circuit and the active matrix circuit, and which constitutes the active matrix circuit. Relates to a method for forming a semiconductor integrated circuit having a region of a first conductivity type having a concentration lower than that of a source / drain, adjacent to the source / drain, and (1) for an active matrix circuit and a peripheral logic circuit. Forming a plurality of island-shaped semiconductor regions, and (2) a gate insulating film and a gate electrode on the semiconductor regions. Forming, (3) to all of the semiconductor region and the step of doping the first conductivity type impurity at a low concentration, (4) of the semiconductor region,
A step of forming a mask to cover a portion of the first conductivity type TFT and doping an impurity of the second conductivity type with the first conductivity type formed in the step (3). A method of manufacturing a semiconductor integrated circuit, wherein the impurity concentration of the type region is lower than the impurity concentration of the second conductivity type region formed in the step (4). 3. The width of the first conductivity type region of claim 2, which is adjacent to the source / drain provided in the TFT and the driver TFT forming the active matrix circuit and has a concentration lower than that of the source / drain. Is 1 to 5 μm. A method of manufacturing a semiconductor integrated circuit, comprising: