CN104241374A - Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof - Google Patents
Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof Download PDFInfo
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- CN104241374A CN104241374A CN201410438265.XA CN201410438265A CN104241374A CN 104241374 A CN104241374 A CN 104241374A CN 201410438265 A CN201410438265 A CN 201410438265A CN 104241374 A CN104241374 A CN 104241374A
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- 239000012535 impurity Substances 0.000 title claims abstract description 114
- 230000005641 tunneling Effects 0.000 title claims abstract description 59
- 230000005669 field effect Effects 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 12
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- 238000001259 photo etching Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
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- 239000007924 injection Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 6
- 238000011161 development Methods 0.000 description 5
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- 230000004048 modification Effects 0.000 description 3
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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Abstract
The invention discloses a deep-energy-level impurity tunneling field-effect transistor (TFET) and a preparation method of the deep-energy-level impurity TFET. The deep-energy-level impurity TFET comprises a tunneling source region, a deep-energy-level impurity doping region, a channel region, a drain region and a control grid. The control grid is located on the channel region. The deep-energy-level impurity doping region is located at the interface between the tunneling source region and the channel region. The doping type of deep-energy-level impurities is different from that of the tunneling source region. The deep-energy-level impurity TFET can be an N-type device or a P-type device; the device structure of the deep-energy-level impurity TFET can remarkably increase on-state currents of the tunneling transistor while maintaining the TFET at a steep subthreshold slope; moreover, the preparation process is simple, the preparation method is completely based on the standard CMOS IC process, a TFET device can be effectively integrated in a CMOS integrated circuit, the production cost is greatly lowered, and the technological process is simplified.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), be specifically related to a kind of deep-level impurity doping tunneling field-effect transistor and preparation method thereof.
Background technology
Since integrated circuit is born, microelectronics integrated technology is always according to " Moore's Law " development, and dimensions of semiconductor devices constantly reduces.Along with semiconductor device enters deep sub-micron range, existing MOSFET element limit owing to being subject to self spreading the conduction mechanism drifted about, and sub-threshold slope is subject to the restriction of thermoelectric potential kT/q and synchronously cannot reduces along with reducing of device size.This just causes MOSFET element leakage current to reduce the requirement that cannot reach device dimensions shrink, and the energy consumption of whole chip constantly rises, and chip power-consumption density sharply increases, and seriously hinders the development that chip system is integrated.In order to adapt to the development trend of integrated circuit, the R and D work of Novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor (TFET, Tunneling Field-Effect Transistor) adopt the new conduction mechanism of band-to-band-tunneling (BTBT), be a kind of Novel low power consumption device being suitable for system integration application development having very much development potentiality.TFET controls the tunnelling width of source and raceway groove interface place tunnel junctions by gate electrode, makes source valence-band electrons be tunneling to channel conduction band (or raceway groove valence-band electrons is tunneling to source conduction band) and forms tunnelling current.This novel conduction mechanism breaks through the restriction of thermoelectric potential kT/q in conventional MOS FET sub-threshold slope theoretical limit, can realize the super steep sub-threshold slope lower than 60mV/dec, reduces device static leakage current and then reduces device quiescent dissipation.
But because semiconductor tape band tunneling efficiency is on the low side, the ON state current of TFET is lower compared with existing MOSFET, the requirement in system integration application can not be met.Therefore, while the sub-threshold slope that maintenance is more steep, improving TFET ON state current, is the very important problem needing in TFET device application to solve.
Summary of the invention
The object of the present invention is to provide a kind of deep-level impurity tunneling field-effect transistor.While the sub-threshold slope that this device architecture can keep tunneling field-effect transistor more steep, significantly improve the ON state current of tunneling transistor.
Deep-level impurity tunneling field-effect transistor provided by the invention, its structure as shown in Figure 1.This tunneling field-effect transistor comprises tunnelling source region, deep-level impurity doped region, channel region, drain region and control gate; Control gate is positioned at the top of channel region; Deep-level impurity doped region is at tunnelling source region and interface place, channel region, and the doping type of this deep-level impurity doped region is contrary with the doping type in tunnelling source region.If the doping type in tunnelling source region is the doping of P type, then the doping type of deep-level impurity doped region is N-type; If the doping type in tunnelling source region is N-type doping, then the doping type of deep energy level doped region is P type;
Above-mentioned deep-level impurity tunneling field-effect transistor can be N-type device or P type device.In an embodiment of the present invention, for N-type device, tunnelling source region is the heavy doping of P type, and concentration is about 1E19cm
-3-1E21cm
-3; Drain region is N-type heavy doping, and concentration is about 1E18cm
-3-1E19cm
-3; Channel region is P type light dope, and concentration is about 1E13cm
-3-1E15cm
-3; Deep-level impurity doped region is N-type doping, and adopt donor-type deep-level impurity, concentration is about 1E16cm
-3-1E18cm
-3.And for P type device, tunnelling source region is N-type heavy doping, concentration is about 1E19cm
-3-1E21cm
-3; , drain region is the heavy doping of P type, and concentration is about 1E18cm
-3-1E19cm
-3; Channel region is N-type light dope, and concentration is about 1E13cm
-3-1E15cm
-3; Deep-level impurity doped region is the doping of P type, and adopt acceptor's moldeed depth level impurities, concentration is about 1E16cm
-3-1E18cm
-3.
Above-mentioned deep-level impurity can ionize out the alms giver of electronics or ionize out acceptor's deep-level impurity in hole under high electric field, and this electric field is 10
4the order of magnitude of V/cm.This deep-level impurity can adopt ion implantation mode to introduce, and the substrate with deep-level impurity also can be adopted to design.
For silica-based N-type deep-level impurity tunneling transistor, the donor-type deep-level impurity of corresponding doping can be deep energy level donor impurity gold or silver-colored.
For silica-based P moldeed depth level impurities tunneling transistor, acceptor's moldeed depth level impurities of corresponding doping can be deep energy level acceptor impurity nickel or zinc.
Deep-level impurity tunneling field-effect transistor provided by the invention can be applied to Si or Ge semi-conducting material, also can be applied to Group III-V compound semiconductor material.
The preparation method of above-mentioned deep-level impurity TFET device architecture, specifically comprises the following steps:
1) initial thermal oxidation on a semiconductor substrate, and deposit one deck nitride;
2) carry out shallow trench isolation after photoetching from (Shallow Trench Isolation, STI) etching, and deposit isolated material carries out chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) after filling deep hole;
3) regrow gate dielectric layer, deposit grid material, by carrying out photoetching and etching formation gate figure;
4) with photoresist and grid material for mask, form drain region by ion implantation;
5) with photoresist and grid material for mask, form tunnelling source region by ion implantation;
6) to be annealed activator impurity by quick high-temp;
7) formation deep-level impurity doped region is injected by angle-tilt ion;
8) by later process, comprise deposit passivation layer, opening contact hole and metallization, deep-level impurity tunneling field-effect transistor can be obtained.
In the preparation method of above-mentioned deep-level impurity TFET device architecture, step 1) in Semiconductor substrate be light dope or unadulterated Semiconductor substrate; The material of Semiconductor substrate can be selected from the one in the germanium GOI on Si, Ge, SiGe, GaAs, the binary of other II-VI, III-V or IV-IV races or ternary semiconductor, isolate supports SOI or insulator.Step 3) in the material of gate dielectric layer be selected from SiO
2, Si
3n
4with the one in high-K gate dielectric material; The method of gate dielectric layer of wherein regrowing is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.Step 3) in grid material be doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or the silicide of metallic nickel.
Step 4) form drain region by ion implantation, the concentration injecting ion is about 1E18cm
-3-1E19cm
-3; Step 5) form tunnelling source region by ion implantation, the concentration injecting ion is about 1E19cm
-3-1E21cm
-3; Step 7) inject formation deep-level impurity doped region by angle-tilt ion, the concentration injecting ion is about 1E16cm
-3-1E18cm
-3.
Advantageous Effects of the present invention is:
Compared with existing TFET, the device architecture of deep-level impurity tunneling field-effect transistor provided by the invention can effective increased device On current, keeps steep sub-threshold slope simultaneously.For N-type device, knot place, tunnelling source has the donor-type deep-level impurity doped region contrary with tunnelling source region doping type, and this deep-level impurity energy level is positioned at below forbidden band, channel region central authorities, close to the top of valence band of channel region.When device is in OFF state, the shallow level impurity that these deep-level impurities do not ionize or are introduced into compensates.When gate electrode adds positive voltage, raceway groove can be with drop-down, knot place, tunnelling source electric-field enhancing, raw band-to-band-tunneling of binding up one's hair in tunnelling source, and device is opened.When grid voltage is less, main generation source region valence-band electrons, to the band-to-band-tunneling of the empty electronic state of channel conduction band, has more steep subthreshold swing; Along with grid voltage increases, knot place, tunnelling source electric-field enhancing is to the ionization critical electric field of deep-level impurity, electronics in deep energy level in deep-level impurity doped region is ionized instantaneously, at deep-level impurity energy level, place forms sky electronic state, thus there is the band-to-band-tunneling of the empty electronic state from tunnelling source region valence-band electrons to deep-level impurity energy level, and the electronics be tunneling on deep-level impurity energy level is ionized instantaneously again to channel conduction band and forms extra supplementary tunnelling current, thus effectively improve the ON state current of tunneling transistor.
Deep-level impurity tunneling field-effect transistor preparation technology provided by the invention is simple, the complete measured CMOS IC technique of preparation method, can integrated TFET device in CMOS integrated circuit effectively, significantly reduces production cost, simplifies technological process.
Accompanying drawing explanation
Fig. 1 is the structural representation of deep-level impurity tunneling field-effect transistor of the present invention;
Fig. 2 is the device profile map after removing nitride after forming STI isolation on a semiconductor substrate;
Fig. 3 is by photoetching and etches the device profile map after forming grid material;
Fig. 4 exposes the drain region of TFET device by photoetching and forms the device profile map behind drain region by ion implantation;
Fig. 5 exposes TFET device tunnelling source region by photoetching and forms the device profile map behind tunnelling source region by ion implantation;
Fig. 6 injects the device profile map after forming deep-level impurity doped region by angle-tilt ion;
In Fig. 1 ~ Fig. 6,1-Semiconductor substrate; 2-STI separator; 3-gate dielectric layer; 4-grid material; 5-photoresist; 6-drain region; 7-tunnelling source region; 8-deep-level impurity doped region; The passivation layer of 9-later process; The metal of 10-later process.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, the present invention is described further.
Deep-level impurity tunneling field-effect transistor provided by the invention, its structure as shown in Figure 1.This tunneling field-effect transistor comprises tunnelling source region, channel region, drain region and control gate; Wherein, control gate is positioned at the top of channel region; Also comprise a deep-level impurity doped region in tunnelling source region and interface place, channel region, and the doping type of deep-level impurity is contrary with the doping type in tunnelling source region.For N-type device, tunnelling source region is P type heavy doping (about 1E19cm
-3-1E21cm
-3), drain region is N-type heavy doping (about 1E18cm
-3-1E19cm
-3), channel region is P type light dope (about 1E13cm
-3-1E15cm
-3); Deep-level impurity doped region is N-type doping, adopts donor-type deep-level impurity (about 1E16cm
-3-1E18cm
-3).And for P type device, tunnelling source region is N-type heavy doping (about 1E19cm
-3-1E21cm
-3), drain region is P type heavy doping (about 1E18cm
-3-1E19cm
-3), channel region is N-type light dope (about 1E13cm
-3-1E15cm
-3); Deep-level impurity doped region is the doping of P type, adopts acceptor's moldeed depth level impurities (about 1E16cm
-3-1E18cm
-3).
Above-mentioned deep-level impurity can ionize out the alms giver of electronics or ionize out acceptor's deep-level impurity in hole under High-Field, and this electric field is 10
4the order of magnitude of V/cm.This deep-level impurity can adopt ion implantation mode to introduce, and the substrate with deep-level impurity also can be adopted to design.
For silica-based N-type deep-level impurity tunneling transistor, the donor-type deep-level impurity of corresponding doping can be deep energy level donor impurity gold or silver-colored.
For silica-based P moldeed depth level impurities tunneling transistor, acceptor's moldeed depth level impurities of corresponding doping can be deep energy level acceptor impurity nickel or zinc.
Deep-level impurity tunneling field-effect transistor provided by the invention can be applied to Si or Ge semi-conducting material, also can be applied to Group III-V compound semiconductor material.
Below for N-type device, the preparation method of above-mentioned deep-level impurity tunneling field-effect transistor is described, the preparation of P moldeed depth level impurities tunneling field-effect transistor device is similar with it.The implementation step of the preparation method of above-mentioned deep-level impurity tunneling field-effect transistor is as shown in Fig. 2 ~ Fig. 6, and as shown in Figure 1, concrete steps comprise the structure of the N-type deep-level impurity tunneling field-effect transistor prepared:
1) substrate doping be light dope, crystal orientation be <100> silicon substrate 1 on initial thermal oxidation layer of silicon dioxide, thickness is about 10nm, and deposit one deck silicon nitride (Si
3n
4), thickness is about 100nm, adopts shallow-trench isolation fabrication techniques active area STI separator 2 afterwards, then carries out CMP, as shown in Figure 2;
2) silicon dioxide of surperficial initial growth is removed in drift, then heat growth one deck gate dielectric layer 3, and gate dielectric layer is SiO
2, thickness is 1 ~ 5nm; Adopt LPCVD deposit grid material 4, grid material is doped polysilicon layer, and thickness is 50 ~ 200nm.Make gate figure by lithography, etch grid material 4 until gate dielectric layer 3, as shown in Figure 3;
3) with photoresist 5 and grid 4 for mask, (As, dosage is 1E14/cm to carry out drain region 6 ion implantation
-2, energy is 40keV, injects ion concentration and is about 3E18/cm
-3) as shown in Figure 4;
4) with photoresist 5 and grid 4 for mask, carry out tunnelling source region 7 ion implantation (BF
2, dosage is 1E15/cm
-2, energy is 20keV, injects ion concentration and is about 2E20/cm
-3), as shown in Figure 5.Carry out a quick high-temp annealing, and implanted dopant is activated (temperature is 1050 DEG C, and the time is 10s);
5) with grid 4 for mask, the about 30 ° of angles that tilt carry out donor-type deep-level impurity doped region 8 ion implantation, and (Au, dosage is 1E12/cm
-2, energy is 90keV, injects ion concentration and is about 1E17/cm
-3), as shown in Figure 6;
6) finally enter conventional later process, comprise deposit passivation layer 9, opening contact hole and metallization 10 etc., the structure of the above-mentioned N-type deep-level impurity tunneling field-effect transistor prepared based on standard CMOS IC technique as shown in Figure 1.
For above-mentioned preparation method, in step 1) in, substrate can be light dope or unadulterated Semiconductor substrate; The material of Semiconductor substrate can be the germanium (GOI) on Si, Ge, SiGe, GaAs, the binary of other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports (SOI) or insulator.Step 2) in the material of gate dielectric layer can be selected from SiO
2, Si
3n
4with the one in high-K gate dielectric material; The method of gate dielectric layer of wherein regrowing is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.Step 2) in grid material can be doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or the silicide of metallic nickel.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (13)
1. a deep-level impurity tunneling field-effect transistor, is characterized in that, comprises tunnelling source region, deep-level impurity doped region, channel region, drain region and control gate; Described control gate is positioned at the top of described channel region; Described deep-level impurity doped region is at tunnelling source region and interface place, channel region, and the doping type of described deep-level impurity doped region is contrary with the doping type in described tunnelling source region.
2. deep-level impurity tunneling field-effect transistor as claimed in claim 1, it is characterized in that, described deep-level impurity tunneling field-effect transistor is N-type device or P type device.
3. deep-level impurity tunneling field-effect transistor as claimed in claim 1, it is characterized in that, described deep-level impurity tunneling field-effect transistor is N-type device, described tunnelling source region is the heavy doping of P type, described drain region is N-type heavy doping, described channel region is P type light dope, and described deep-level impurity doped region is N-type doping.
4. deep-level impurity tunneling field-effect transistor as claimed in claim 3, it is characterized in that, described deep-level impurity tunneling field-effect transistor is silica-based N-type deep-level impurity tunneling transistor, and the deep-level impurity of described deep-level impurity doped region is donor-type deep-level impurity gold or silver-colored.
5. deep-level impurity tunneling field-effect transistor as claimed in claim 1, it is characterized in that, described deep-level impurity tunneling field-effect transistor is P type device, described tunnelling source region is N-type heavy doping, described drain region is the heavy doping of P type, described channel region is N-type light dope, and described deep-level impurity doped region is the doping of P type.
6. deep-level impurity tunneling field-effect transistor as claimed in claim 5, it is characterized in that, described deep-level impurity tunneling field-effect transistor is silica-based P moldeed depth level impurities tunneling transistor, and the deep-level impurity of described deep-level impurity doped region is acceptor's moldeed depth level impurities nickel or zinc.
7. deep-level impurity tunneling field-effect transistor as claimed in claim 1, is characterized in that, described deep-level impurity is obtained for being introduced by ion injection method, or by adopting the substrate with deep-level impurity to obtain.
8. described in claim 1, deep-level impurity tunneling field-effect transistor is applied to Si or Ge semi-conducting material, or the purposes of Group III-V compound semiconductor material.
9. the preparation method of deep-level impurity tunneling field-effect transistor described in claim 1, comprises the following steps:
1) initial thermal oxidation on a semiconductor substrate, and deposit one deck nitride;
2) carry out shallow groove isolation etching after photoetching, and deposit isolated material carries out chemical-mechanical planarization after filling deep hole;
3) regrow gate dielectric layer, deposit grid material, by carrying out photoetching and etching formation gate figure;
4) with photoresist and grid material for mask, form drain region by ion implantation;
5) with photoresist and grid material for mask, form tunnelling source region by ion implantation;
6) to be annealed activator impurity by quick high-temp;
7) formation deep-level impurity doped region is injected by angle-tilt ion;
8) by later process, comprise deposit passivation layer, opening contact hole and metallization, deep-level impurity tunneling field-effect transistor can be obtained.
10. the preparation method of deep-level impurity tunneling field-effect transistor as claimed in claim 9, is characterized in that, step 1) described Semiconductor substrate is light dope or unadulterated Semiconductor substrate; The material of described Semiconductor substrate is the one in the germanium on the binary of Si, Ge, SiGe, GaAs, II-VI, III-V or IV-IV race or ternary semiconductor, isolate supports or insulator.
The preparation method of 11. deep-level impurity tunneling field-effect transistors as claimed in claim 9, is characterized in that, step 3) material of described gate dielectric layer is SiO
2, Si
3n
4with the one in high-K gate dielectric material; The method of the described gate dielectric layer that regrows is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
The preparation method of 12. deep-level impurity tunneling field-effect transistors as claimed in claim 9, is characterized in that, step 3) in grid material be doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or the silicide of metallic nickel.
The preparation method of 13. deep-level impurity tunneling field-effect transistors as claimed in claim 9, is characterized in that, step 4) form drain region by ion implantation, concentration is 1E18cm
-3~ 1E19cm
-3; Step 5) form tunnelling source region by ion implantation, concentration is 1E19cm
-3~ 1E21cm
-3; Step 7) inject formation deep-level impurity doped region by angle-tilt ion, concentration is 1E16cm
-3~ 1E18cm
-3.
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