CN102779840A - Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer - Google Patents
Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer Download PDFInfo
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Abstract
The invention discloses an insulated gate bipolar translator (IGBT) with a terminal deep energy level impurity layer, and belongs to the technical field of semiconductor power devices. Based on the conventional Planar field stop-insulated gate bipolar translator (FS-IGBT), a deep energy level impurity layer (15) is injected into a terminal drift area (14); according to the deep energy level impurity layer (15), the degree of ionization of the deep energy level impurities is raised along with the raise of the temperature of the device, and the concentration of the impurities is greatly increased; when the IGBT is turned off, the hole emission efficiency of a P+ current collection area in a terminal area is effectively reduced by carrier concentration added in the terminal drift area is effectively reduced, and alpha PNP (plug-and-play) of a parasitic PNP transistor is reduced, so that high-temperature leakage current of a device is effectively reduced; and electronic concentration added in the drift area and a hole injected into the P+ current collection area are quickly compounded, and the deep energy level impurities serves as a compounding center, so that the compounding of the electronic hole is quickened, the on/off property is effectively improved, and the reliability of the IGBT is improved.
Description
Technical field
The invention belongs to the semiconductor power device technology field, relate to insulated gate bipolar transistor (IGBT).
Background technology
The advantage that the input impedance of the existing MOSFET of IGBT is high, power controlling is little, drive circuit is simple, switching speed is high has the advantage that current density is big, saturation pressure reduces, current handling capability is strong of bipolar power article body pipe again.So three big characteristics of IGBT power device are exactly high pressure, big electric current, at a high speed, this is that other power device can not be compared.So it is the very desirable switching device of field of power electronics; The IGBT product has been gathered high frequency, high pressure, big electric current three big technical advantages; IGBT can realize energy-saving and emission-reduction simultaneously; Have good environmental protection benefit, IGBT is widely used in tradition and emerging fields such as power domain, consumer electronics, automotive electronics, new forms of energy, and market prospects are boundless.The IGBT biggest advantage is no matter can bear rush of current in conducting state or in short-circuit condition; Its weak point is that the high pressure IGBT internal resistance is big; Cause conduction loss big; Be applied to height (in) when pressing the field, need a plurality of series connection usually, and overvoltage, overheated, shock resistance, holding capacity such as anti-interference are lower.
When the IGBT forward conduction; Positive grid voltage makes raceway groove open; The emitter electronics flows to the drift region through raceway groove, because the collector electrode forward bias, the collector region hole pours in the drift region; With a large amount of electronics generation conductivity modulation effects of drift region, thereby can make IGBT little a lot of than the conduction voltage drop of VDMOS; When IGBT turn-offed, grid voltage was negative voltage or no-voltage, and the emitter electronics suddenly disappears, and current collection is high voltage very, and the drift region is continued to pour in a large amount of holes, forms big hole current, and this moment, IGBT was in reverse blocking state, because parasitic PNP pipe α
PNPAlong with temperature raises and sharply rising, make the leakage current of IGBT significantly raise along with the rising of temperature, high temperature, big leakage current are easy to cause the avalanche breakdown of device and even burn.And a large amount of holes of pouring into the drift region are except being extracted by anode and negative electrode respectively with an electronics part fast, thus another part compound generation hangover electric current in the drift region, bottom that does not exhaust, and than VDMOS, the IGBT turn-off time is much bigger; Though IGBT has many performance advantages, reduces high-temperature current leakage, improve the turn-off characteristic of IGBT, the reliability that improves IGBT is focus, difficult point and the emphasis of IGBT research always.
Summary of the invention
The present invention provides a kind of IGBT with terminal deep-level impurity layer; Be on conventional P lanar FS-IGBT basis; In the drift region, terminal, inject one deck deep-level impurity layer, said termination environment deep-level impurity layer is along with temperature rising degree of ionization increases, and the termination environment impurity concentration increases; When IGBT turn-offs, can reduce PNP pipe α
PNP, effectively reduce high-temperature current leakage, and then can prevent the avalanche breakdown that high temperature, high pressure, high-current leading rise.And deep-level impurity itself is exactly the complex centre, can effectively improve the IGBT turn-off characteristic, improves the reliability of IGBT.
Technical scheme of the present invention is following:
A kind of IGBT with terminal deep-level impurity layer; Its cellular structure is as shown in Figure 2; Comprise that the active emitter of metal 1, polygate electrodes 2, metal collector 3, gate oxide 4, N+ active area 5, P type base 6, P type equipotential ring 7, polysilicon field plate 8, metallic aluminium field plate 9, termination environment oxide layer 10, terminal polysilicon field plate 11, P type field limiting ring 12, N+ electric field are by ring 13, N-drift region 14, N+ electric field stop layer 15, P+ collector region 16;
Device up is metal collector 3, P+ collector region 16, N+ electric field stop layer 15, N-drift region 14 from bottom successively; P type base 6 is positioned at 14 tops, N-drift region; Has N+ active area 5 in the P type base 6; What unit's cellular surface contacted with P type base 6 with N+ active area 5 respectively is the active emitter 1 of metal; What unit's cellular surface contacted with N-drift region 8 with N+ active area 5, P type base 6 respectively is silicon dioxide gate oxide 4, and silicon dioxide gate oxide 4 surfaces are polygate electrodes 2, fill dielectric between the active emitter 1 of polygate electrodes 2 and metal;
Position near P type base 6 in the N-drift region 14 of device terminal part has P type equipotential ring 7, and P type equipotential ring 7 tops have polysilicon field plate 8; Position away from P type base 6 in the N-drift region 14 of device terminal part has the N+ electric field by ring 13, and the N+ electric field has the second terminal polysilicon field plate 11 by ring 13 tops; P type equipotential ring 7 and N+ electric field have Series P-type field limiting ring 12 in the N-drift region 14 between the ring 13; The device terminal end surface also has the first metallic aluminium field plate 9 that links to each other with polysilicon field plate 8 respectively; The terminal polysilicon field plate 11 that links to each other with Series P-type field limiting ring 12 and the second metallic aluminium field plate (9), the 3rd metallic aluminium field plate 9 that links to each other with the second terminal polysilicon field plate 11;
The terminal part of said N-drift region 14 has also injected one deck deep-level impurity layer 17; Said deep-level impurity layer 17 is in 14 terminal areas, N-drift region; The back side is N+ electric field stop layer 15, directly over be P type equipotential ring 7, P type field limiting ring 12 and N+ electric field by ring 13.
What need further specify is that drift region, described terminal deep-level impurity layer (15) doped chemical comprises sulphur, selenium, tellurium, gold, platinum etc.; And position, length, the width-adjustable of drift region, terminal deep-level impurity layer.Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon replace body silicon when making device.
Operation principle of the present invention is following:
IGBT with terminal deep-level impurity layer provided by the invention because the deep-level impurity layer of drift region, terminal can obviously reduce high-temperature current leakage, effectively prevents the avalanche breakdown that causes because of high voltage, big electric current, high temperature.And can effectively improve turn-off characteristic, existing with Fig. 2, mixing element sulphur is example, and its operation principle is described.
IGBT with terminal deep-level impurity layer provided by the present invention; On conventional P lanar FS-IGBT basis; Inject one deck deep-level impurity layer 15 in the drift region, terminal area, degree of ionization increases the performance that this beneficial characteristics is improved IGBT along with the temperature rising to utilize deep-level impurity.IGBT with terminal deep-level impurity layer of the present invention is the same with conventional I GBT, as IGBT during at forward conduction, because described termination environment deep-level impurity layer does not influence the forward conduction characteristic of IGBT, so to the not influence of forward conduction characteristic of device; When IGBT turn-offed, the emission of emitter electronics stopped suddenly, hole current moment increase, and IGBT is in reverse blocking state, and conventional I GBT structure P type this moment base as shown in Figure 1 is significantly expanded to the drift region, terminal, because the α of parasitic PNP pipe
PNPBe positive temperature coefficient, thereby the terminal has produced the anode leakage current of lasting increase, this moment IGBT high electric current, high voltage, high temperature are easy to cause that the dynamic avalanche of device punctures.But New IGBT of the present invention is as shown in Figure 2; When IGBT turn-offs; Because one deck deep-level impurity layer structure injected in the drift region, terminal, device temperature raises, and drift region, terminal deep-level impurity degree of ionization raises; The electron concentration of sulphur ionization significantly rises, and the carrier concentration of increase can obviously reduce the α of PNP pipe
PNP, effectively reduce high-temperature current leakage, thereby can prevent effectively that the dynamic avalanche that causes because of the high temperature under the blocking state, high voltage, high electric current from puncturing.It is compound that the electron concentration that the drift region increases and P+ emitter region injected holes quicken, and deep-level impurity itself is exactly the complex centre, and further accelerated electron hole compound can effectively be improved the turn-off characteristic of IGBT, greatly improves the reliability of IGBT.
In sum; IGBT with terminal deep-level impurity layer proposed by the invention can effectively reduce IGBT terminal part high-temperature current leakage, thereby effectively prevents Yin Gaowen, high electric current, high voltage and the avalanche breakdown that causes; Effectively improve the device turn-off characteristic, improve the reliability of IGBT.
Description of drawings
Fig. 1 is a conventional P lanar FS-IGBT structural representation.
Fig. 2 is the IGBT structural representation with terminal deep-level impurity layer provided by the invention.
Hole-recombination and extraction process sketch map when Fig. 3 is the shutoff of conventional P lanar FS-IGBT structure.
Fig. 4 is the IGBT with terminal deep-level impurity layer provided by the invention hole-recombination and extraction process sketch map when turn-offing.
Among Fig. 1 to Fig. 4: the 1st, the active emitter of metal, the 2nd, polygate electrodes, the 3rd, metal collector, the 4th, gate oxide; The 5th, N+ active area, the 6th, P type base, the 7th, P type equipotential ring, the 8th, polysilicon field plate on the equipotential ring; The 9th, metallic aluminium field plate, the 10th, termination environment oxide layer, the 11st, terminal polysilicon field plate, the 12nd, P type field limiting ring; The 13rd, N+ ends ring, and the 14th, N-drift region, the 15th, N+ electric field stop layer, the 16th, P+ collector region.Among Fig. 3 to Fig. 4 :+symbolic representation hole ,-symbolic representation electronics, arrow are represented the carrier moving direction.
Specific embodiments
A kind of IGBT with terminal deep-level impurity layer; Its cellular structure is as shown in Figure 2; Comprise that the active emitter of metal 1, polygate electrodes 2, metal collector 3, gate oxide 4, N+ active area 5, P type base 6, P type equipotential ring 7, polysilicon field plate 8, metallic aluminium field plate 9, termination environment oxide layer 10, terminal polysilicon field plate 11, P type field limiting ring 12, N+ electric field are by ring 13, N-drift region 14, N+ electric field stop layer 15, P+ collector region 16;
Device up is metal collector 3, P+ collector region 16, N+ electric field stop layer 15, N-drift region 14 from bottom successively; P type base 6 is positioned at 14 tops, N-drift region; Has N+ active area 5 in the P type base 6; What unit's cellular surface contacted with P type base 6 with N+ active area 5 respectively is the active emitter 1 of metal; What unit's cellular surface contacted with N-drift region 8 with N+ active area 5, P type base 6 respectively is silicon dioxide gate oxide 4, and silicon dioxide gate oxide 4 surfaces are polygate electrodes 2, fill dielectric between the active emitter 1 of polygate electrodes 2 and metal;
Position near P type base 6 in the N-drift region 14 of device terminal part has P type equipotential ring 7, and P type equipotential ring 7 tops have polysilicon field plate 8; Position away from P type base 6 in the N-drift region 14 of device terminal part has the N+ electric field by ring 13, and the N+ electric field has the second terminal polysilicon field plate 11 by ring 13 tops; P type equipotential ring 7 and N+ electric field have Series P-type field limiting ring 12 in the N-drift region 14 between the ring 13; The device terminal end surface also has the first metallic aluminium field plate 9 that links to each other with polysilicon field plate 8 respectively; The terminal polysilicon field plate 11 that links to each other with Series P-type field limiting ring 12 and the second metallic aluminium field plate (9), the 3rd metallic aluminium field plate 9 that links to each other with the second terminal polysilicon field plate 11;
The terminal part of said N-drift region 14 has also injected one deck deep-level impurity layer 17; Said deep-level impurity layer 17 is in 14 terminal areas, N-drift region; The back side is N+ electric field stop layer 15, directly over be P type equipotential ring 7, P type field limiting ring 12 and N+ electric field by ring 13.
What need further specify is that drift region, described terminal deep-level impurity layer (15) doped chemical comprises sulphur, selenium, tellurium, gold, platinum etc.; And position, length, the width-adjustable of drift region, terminal deep-level impurity layer.Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon replace body silicon when making device.
A kind of terminal has the IGBT of deep-level impurity layer, and its concrete implementation method is following, increases a mask plate when deep-level impurity layer is injected at the back side on conventional P lanar FS-IGBT architecture basics, chooses the N type<100>Crystal orientation zone melting single-crystal liner, the deep-level impurity layer is injected at the back side, and the FS layer is injected at the back side, an oxidation, field limiting ring photoetching of P type and injection, the photoetching active area, gate oxidation, the deposit polysilicon, photoetching polysilicon, P type base inject and annealing, and the P+ tagma is injected, N
+Source region photoetching and injection, deposited oxide layer is carved fairlead, the deposition emitter metal, emitter metal exposure and etching, back side transparent collector injects and annealing, back face metalization, passivation or the like.
Claims (4)
1. IGBT with terminal deep-level impurity layer; Its cellular structure comprises that the active emitter of metal (1), polygate electrodes (2), metal collector (3), gate oxide (4), N+ active area (5), P type base (6), P type equipotential ring (7), polysilicon field plate (8), metallic aluminium field plate (9), termination environment oxide layer (10), terminal polysilicon field plate (11), P type field limiting ring (12), N+ electric field are by ring (13), N-drift region (14), N+ electric field stop layer (15), P+ collector region (16);
Device up is metal collector (3), P+ collector region (16), N+ electric field stop layer (15), N-drift region (14) from bottom successively; P type base (6) is positioned at top, N-drift region (14); Has N+ active area (5) in the P type base (6); What unit's cellular surface contacted with P type base (6) with N+ active area (5) respectively is the active emitter of metal (1); What unit's cellular surface contacted with N-drift region (8) with N+ active area (5), P type base (6) respectively is silicon dioxide gate oxide (4); Silicon dioxide gate oxide (4) surface is polygate electrodes (2), fills dielectric between polygate electrodes (2) and the active emitter of metal (1);
Position near P type base (6) in the N-drift region (14) of device terminal part has P type equipotential ring (7), and P type equipotential ring (7) top has polysilicon field plate (8); Position away from P type base (6) in the N-drift region (14) of device terminal part has the N+ electric field by ring (13), and the N+ electric field has the second terminal polysilicon field plate (11) by ring (13) top; P type equipotential ring (7) and N+ electric field have Series P-type field limiting ring (12) in the N-drift region (14) between the ring (13); The device terminal end surface also has the first metallic aluminium field plate (9) that links to each other with polysilicon field plate (8) respectively; The terminal polysilicon field plate (11) that links to each other with Series P-type field limiting ring (12) and the second metallic aluminium field plate (9), the 3rd metallic aluminium field plate (9) that links to each other with the second terminal polysilicon field plate (11);
The terminal part of said N-drift region (14) has also injected one deck deep-level impurity layer (17); Said deep-level impurity layer (17) is in terminal area, N-drift region (14); The back side is N+ electric field stop layer (15), directly over be P type equipotential ring (7), P type field limiting ring (12) and N+ electric field by ring (13).
2. the IGBT with terminal deep-level impurity layer according to claim 1 is characterized in that, the doped chemical of said deep-level impurity layer (15) comprises sulphur, selenium, tellurium, gold or platinum.
3. the IGBT with terminal deep-level impurity layer according to claim 1 is characterized in that, vertical width of said deep-level impurity layer (15), lateral length and the adjustable positions in the drift region.
4. a kind of terminal according to claim 1 has the New IGBT of deep-level impurity layer; It is characterized in that this structure is not only applicable to Planar-IGBT, and be applicable to Trench-IGBT; Be not only applicable to FS-IGBT, and be applicable to NPT-IGBT and PT-IGBT.
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| WO2014117492A1 (en) * | 2013-01-30 | 2014-08-07 | 华为技术有限公司 | Insulated gate bipolar transistor |
| US8907374B2 (en) | 2013-01-30 | 2014-12-09 | Hauwei Technologies Co., Ltd. | Insulated gate bipolar transistor |
| CN104332491A (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | Terminal unit structure with metal extending and polycrystal stopping field plates and method for manufacturing terminal unit structure |
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| WO2014117492A1 (en) * | 2013-01-30 | 2014-08-07 | 华为技术有限公司 | Insulated gate bipolar transistor |
| US8907374B2 (en) | 2013-01-30 | 2014-12-09 | Hauwei Technologies Co., Ltd. | Insulated gate bipolar transistor |
| CN104779160A (en) * | 2014-01-13 | 2015-07-15 | 无锡华润上华半导体有限公司 | Semiconductor manufacturing method |
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| CN104332491A (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | Terminal unit structure with metal extending and polycrystal stopping field plates and method for manufacturing terminal unit structure |
| CN104409479A (en) * | 2014-11-05 | 2015-03-11 | 中国东方电气集团有限公司 | Terminal unit structure of power electronic semiconductor chip and manufacturing method of terminal unit structure |
| CN105185829B (en) * | 2015-08-28 | 2019-02-12 | 深圳深爱半导体股份有限公司 | Power transistor and preparation method thereof |
| CN105185829A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and manufacturing method thereof |
| CN105185830A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and junction termination structure thereof |
| CN105185830B (en) * | 2015-08-28 | 2019-04-19 | 深圳深爱半导体股份有限公司 | Power transistor and its junction termination structures |
| CN106847835A (en) * | 2017-04-01 | 2017-06-13 | 厦门天马微电子有限公司 | The preparation method and display device of a kind of display panel, display panel |
| CN106847835B (en) * | 2017-04-01 | 2019-12-27 | 厦门天马微电子有限公司 | Display panel, preparation method of display panel and display device |
| CN107425054A (en) * | 2017-08-07 | 2017-12-01 | 电子科技大学 | A kind of terminal structure of power semiconductor |
| CN107403834A (en) * | 2017-09-14 | 2017-11-28 | 全球能源互联网研究院 | FS type IGBT devices with soft switching characteristic |
| CN107910356A (en) * | 2017-10-24 | 2018-04-13 | 全球能源互联网研究院 | A kind of efficient terminal structure of vertical-type high voltage power device and preparation method thereof |
| CN110808245A (en) * | 2020-01-07 | 2020-02-18 | 四川立泰电子有限公司 | Low electromagnetic interference power device terminal structure |
| CN110808245B (en) * | 2020-01-07 | 2020-04-21 | 四川立泰电子有限公司 | Low electromagnetic interference power device terminal structure |
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