CN104409479A - Terminal unit structure of power electronic semiconductor chip and manufacturing method of terminal unit structure - Google Patents
Terminal unit structure of power electronic semiconductor chip and manufacturing method of terminal unit structure Download PDFInfo
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- CN104409479A CN104409479A CN201410614988.0A CN201410614988A CN104409479A CN 104409479 A CN104409479 A CN 104409479A CN 201410614988 A CN201410614988 A CN 201410614988A CN 104409479 A CN104409479 A CN 104409479A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 230000004888 barrier function Effects 0.000 claims description 94
- 238000000034 method Methods 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 229910019213 POCl3 Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 38
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000005685 electric field effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the power electronic technical field and relates to a semiconductor device, in particular, a terminal unit structure of a power electronic semiconductor chip and a manufacturing method of the terminal unit structure. The terminal unit structure comprises a first conductivity type substrate; a second conductivity type field limiting ring is arranged in a first main surface of the first conductivity type substrate; a first insulating layer is arranged on the first main surface of the first conductivity type substrate; two field plates are arranged on the first insulating layer and are located at two sides of the second conductivity type field limiting ring respectively; the field plates are provided with second insulating layers; the second insulating layers are provided with a metal field plate; the bottom of the metal field plate contacts with the second conductivity type field limiting ring; and the metal field plate covers the area of the second conductivity type field limiting ring and two sides of the second conductivity type field limiting ring. According to the terminal unit structure of the invention, structural improvement of the field plate is emphasized; and the field plates are connected with the second conductivity type field limiting ring, wherein the cut-off field plate can compress an electric field, and the stretching field plate can stretch the electric field, and therefore, so that the electric field can be distributed newly, and the electric field effect of the field limiting ring can be decreased.
Description
Technical field
The semiconductor device relating to electric and electronic technical field of the present invention, is specially a kind of terminal unit architecture and manufacture method thereof of power electronic semiconductor chip.
Background technology
In the manufacturing and designing of power electronic device, terminal is an indispensable part, and it can make device inside depletion region become level and smooth when device bears high-tension, thus allows device bear higher voltage.The terminal of traditional power electronic device is generally and sinks to the bottom by injecting and advancing at low-doped, prepares field limiting ring; Also have and add that field plate is to realize the level and smooth further of electric field laterally on field limiting ring.
Relative to independent field limiting ring structure; the structure of field limiting ring+field plate can better level and smooth depletion region; therefore on the Terminal Design of identical pressure-bearing; the number of the ring that the design of field limiting ring+field plate needs than the design of independent field limiting ring is few; simultaneously field plate can the terminal of protect IC not by outside contamination, therefore there is better breakdown characteristics and device stability.
In addition, in the manufacture process of power electronic device, active region determines the important electrical characteristic of device, the part although terminal is absolutely necessary, but only affect puncture voltage and the stability of device, do not contribute the conduction voltage drop of device and turn-off time, therefore terminal is on the basis meeting the pressure-bearing required by device, and the area of terminal is the smaller the better.
The more than total junction device problem of two kinds of Terminal Designs, can be summed up as:
The structure of field plate protection device terminal can exempt from pollution, therefore needs the area increasing field plate as far as possible; And the area of terminal needs little as much as possible, increases the area of active region.And the area increasing field plate refers under the terminal prerequisite of certain size, increase field plate and cover the ratio of terminal, because the ratio that field plate covers terminal is larger, the ratio that terminal comes out is less, do not expose like this be exactly be not easy contaminated.
Existing Patents has: the patent No. is CN201010246809.4, the applying date is 2010-08-06, name is called the patent of invention of " a kind of edge termination structure of high voltage power semiconductor device ", its technology contents is: the edge termination structure that the invention discloses a kind of high voltage power semiconductor device, comprise several by power semiconductor around, with substrate, there is the field limiting ring of films of opposite conductivity, at each field limiting ring, one-sided or both sides are provided with identical with field limiting ring conduction type, doping content is less than the doped region of field limiting ring, field limiting ring is covered with field plate, silicon dioxide layer interval is used between field limiting ring and field plate.The material of field plate can be selected from copper, aluminium, polysilicon or oxygen-doped polysilicon etc.
For another example the patent No. is CN201010246816.4, the applying date is 2010-08-06, name is called the patent of invention of " a kind of edge termination structure of high voltage power semiconductor device ", its technology contents is: the edge termination structure that the invention discloses a kind of high voltage power semiconductor device, comprise several by power semiconductor around, with substrate, there is the field limiting ring of films of opposite conductivity, be provided with identical with field limiting ring conduction type around field limiting ring, doping content is less than the doped region of field limiting ring, field limiting ring wraps up by this doped region, field limiting ring is covered with field plate, silicon dioxide layer interval is used between field limiting ring and field plate.The material of field plate can be selected from copper, aluminium, polysilicon or oxygen-doped polysilicon etc.
Wherein CN201010246809.4 with CN201010246816.4 is identical with the object that this patent is protected; it is all a kind of semiconductor device itself " terminal structure "; but at the design of terminal structure and terminal structure functionally; both are different; these two patents above-mentioned are all reduce the electric field at field limiting ring place by the design of different field limiting rings and puncture voltage can be increased; be disjunct between their field plate and field limiting ring, field plate does not play the effect reducing electric field.
Summary of the invention
In order to overcome the problems referred to above that existing semiconductor chip terminal unit architecture exists, special terminal unit architecture and the manufacture method thereof proposing a kind of power electronic semiconductor chip now, this design has larger field plate area coverage, can increase the stability of device; And have employed the design of cut-off field plate, the area of terminal can be reduced further.
Concrete scheme of the present invention is as follows:
A kind of terminal unit architecture of power electronic semiconductor chip, it is characterized in that: comprise the first conductivity type substrate, be provided with the second conduction type field limiting ring in first interarea of described first conductivity type substrate, on the primary principal plane of described first conductivity type substrate, be provided with the first insulating barrier; On described first insulating barrier and the both sides being positioned at the second conduction type field limiting ring are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier, and described second insulating barrier is provided with Metal field plate; The bottom of described Metal field plate contacts with the second conduction type field limiting ring, and described Metal field plate covers region and the both sides thereof of the second conduction type field limiting ring;
Described two blocks of field plates to be positioned at above the first insulating barrier and to cover the both sides of the second conduction type field limiting ring, and the field plate wherein near side, active region is cut-off field plate, and the field plate near device edge side is for extending field plate.
Further, described second insulating barrier is positioned at above field plate, covers whole field plate.
Further, described Metal field plate is positioned at above the second insulating barrier, and cover the region of whole second conduction type field circulation, described Metal field plate is connected with the second conduction type field limiting ring.
Further, described Metal field plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate.
Further, described Metal field plate is connected by the electrode contact hole on the second insulating barrier with field plate.
Further, the second interarea place of described first conductivity type substrate, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
Further, the first conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate is silicon substrate, and the first interarea of the first conductivity type substrate is its front, and the second interarea of the first conductivity type substrate is its back side.
Further, the diffusion depth of described second conduction type field limiting ring is 1um-10um; Described first insulating barrier is silicon dioxide layer, and thickness is 0.5um ~ 5um; Cut-off field plate width in described field plate is 0 um ~ 30um; Extension field plate width in field plate is 0 um ~ 50um.
A manufacture method for the terminal unit architecture of power electronic semiconductor chip, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate, the first insulating barrier is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and cut-off field plate and extend field plate;
G. deposit the second insulating barrier by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate, make metal level by evaporating or sputtering, and form Metal field plate by photoetching, wet etching.
Further, described second conduction type field limiting ring doping content is higher than the doping content of the first conductivity type substrate; Described second insulating barrier is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
The invention has the advantages that:
1, the terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring, and cut-off field plate can compress electric field, extends field plate and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
2, the application introduce cut-off field plate, cut-off field plate is set simultaneously and extends field plate for the design of traditional field limiting ring+field plate, under limited area, increase the area that device field plate covers, and can ensure that the width of terminal is in very among a small circle.
3, the field plate of the application is large due to the ratio covering terminal, can play the not contaminated effect of protection terminal.
4, compared to traditional field limiting ring+field plate termination structure, the application adds cut-off field plate, on the basis keeping total area constant, makes the area coverage of field plate larger, decreases the pollution of outer bound pair terminal, the stability of device is got a promotion.
5, the application is compared to traditional field limiting ring+field plate termination structure, present invention adds cut-off field plate, and the area of whole terminal is reduced, and so just relatively expands the active area of device, the electrology characteristic of device is improved further.
Accompanying drawing explanation
Fig. 1 is the application's overall structure schematic diagram.
The corresponding technique A of Fig. 2.
Fig. 3 corresponding technique B, C.
Fig. 4 corresponding technique D, E.
The corresponding technique F of Fig. 5.
Fig. 6,7 corresponding technique G.
Fig. 8,9 corresponding technique I.
110: the first conductivity type substrate in accompanying drawing; 120: the second conduction type field limiting rings; 130: the first insulating barriers; 141: cut-off field plate; 142: extend field plate; 150: the second insulating barriers; 160: Metal field plate.
Embodiment
Embodiment 1
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120; Every block field plate contacts with metal field 160 plate or does not contact.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
Embodiment 2
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
Embodiment 3
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um-10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um ~ 5um; Cut-off field plate 141 width in described field plate is 0 um ~ 30um; Extension field plate 142 width in field plate is 0 um ~ 50um.
Embodiment 4
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um; Cut-off field plate 141 width in described field plate is 30um; Extension field plate 142 width in field plate is 50um.
Embodiment 5
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 5um; Cut-off field plate 141 width in described field plate is 10um; Extension field plate 142 width in field plate is 20um.
Embodiment 6
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 4um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 3.1um; Cut-off field plate 141 width in described field plate is 20um; Extension field plate 142 width in field plate is 35um.
Embodiment 7
A manufacture method for the terminal unit architecture of power electronic semiconductor chip, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate 110, the first insulating barrier 130 is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier 130 is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring 120;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and cut-off field plate 141 and extend field plate 142;
G. deposit the second insulating barrier 150 by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate 110, make metal level by evaporating or sputtering, and form metal field 160 plate by photoetching, wet etching.
Described second conduction type field limiting ring 120 doping content is higher than the doping content of the first conductivity type substrate 110; Described second insulating barrier 150 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
Embodiment 8
A kind of terminal unit architecture of power electronic semiconductor chip comprises the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with metal field 160 plate; The bottom of described metal field 160 plate contacts with the second conduction type field limiting ring 120, and described metal field 160 plate covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, and the field plate wherein near side, active region is cut-off field plate 141, and the field plate near device edge side is for extending field plate 142.Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described metal field 160 plate is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described metal field 160 plate is connected with the second conduction type field limiting ring 120.
Described metal field 160 plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate or does not establish electrode contact hole.
Described metal field 160 plate is connected by the electrode contact hole on the second insulating barrier 150 with field plate, or metal field 160 plate is not connected with field plate.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and cut-off field plate 141 can compress electric field, extends field plate 142 and can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um-10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um ~ 5um; Cut-off field plate 141 width in described field plate is 0 um ~ 30um; Extension field plate 142 width in field plate is 0 um ~ 50um.
A manufacture method for the terminal unit architecture of power electronic semiconductor chip, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate 110, the first insulating barrier 130 is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier 130 is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring 120;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and cut-off field plate 141 and extend field plate 142;
G. deposit the second insulating barrier 150 by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate 110, make metal level by evaporating or sputtering, and form metal field 160 plate by photoetching, wet etching.
Further, described second conduction type field limiting ring 120 doping content is higher than the doping content of the first conductivity type substrate 110; Described second insulating barrier 150 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
Claims (10)
1. the terminal unit architecture of a power electronic semiconductor chip, it is characterized in that: comprise the first conductivity type substrate (110), the second conduction type field limiting ring (120) is provided with in first interarea of described first conductivity type substrate (110), on the primary principal plane of described first conductivity type substrate (110), be provided with the first insulating barrier (130); Described first insulating barrier (130) is upper and the both sides being positioned at the second conduction type field limiting ring (120) are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier (150), and described second insulating barrier (150) is provided with metal field (160) plate; The bottom of described metal field (160) plate contacts with the second conduction type field limiting ring (120), and described metal field (160) plate covers region and the both sides thereof of the second conduction type field limiting ring (120);
Described two blocks of field plates to be positioned at above the first insulating barrier (130) and to cover the both sides of the second conduction type field limiting ring (120), field plate wherein near side, active region is cut-off field plate (141), and the field plate near device edge side is for extending field plate (142).
2. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 1, is characterized in that: described second insulating barrier (150) is positioned at above field plate, covers whole field plate.
3. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 2, it is characterized in that: described metal field (160) plate is positioned at above the second insulating barrier (150), cover the region of whole second conduction type field circulation, described metal field (160) plate is connected with the second conduction type field limiting ring (120).
4. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 3, is characterized in that: described metal field (160) plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate.
5. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 4, is characterized in that: described metal field (160) plate is connected by the electrode contact hole on the second insulating barrier (150) with field plate.
6. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 1-5 any one is characterized in that: the second interarea place of described first conductivity type substrate (110), is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
7. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 6, it is characterized in that: the first conduction type is N-type, second conduction type is P type, described first conductivity type substrate (110) is silicon substrate, first interarea of the first conductivity type substrate (110) is its front, and the second interarea of the first conductivity type substrate (110) is its back side.
8. the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 7, is characterized in that: the diffusion depth of described second conduction type field limiting ring (120) is 1um-10um; Described first insulating barrier (130) is silicon dioxide layer, and thickness is 0.5um ~ 5um; Cut-off field plate (141) width in described field plate is 0 um ~ 30um; Extension field plate (142) width in field plate is 0 um ~ 50um.
9. the manufacture method of the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 1, it is characterized in that: a kind of manufacture method of terminal unit architecture of power electronic semiconductor chip, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate (110), the first insulating barrier (130) is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier (130) is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring (120);
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and cut-off field plate (141) and extend field plate (142);
G. deposit the second insulating barrier (150) by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate (110), make metal level by evaporating or sputtering, and form metal field (160) plate by photoetching, wet etching.
10. the manufacture method of the terminal unit architecture of a kind of power electronic semiconductor chip according to claim 9, is characterized in that: described second conduction type field limiting ring (120) doping content is higher than the doping content of the first conductivity type substrate (110); Described second insulating barrier (150) is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
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