CN117116974A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN117116974A CN117116974A CN202311118361.1A CN202311118361A CN117116974A CN 117116974 A CN117116974 A CN 117116974A CN 202311118361 A CN202311118361 A CN 202311118361A CN 117116974 A CN117116974 A CN 117116974A
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- field plate
- via hole
- semiconductor device
- voltage
- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 63
- 230000007704 transition Effects 0.000 claims description 12
- 239000011148 porous material Substances 0.000 claims description 3
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a semiconductor device, which comprises: a drift layer; a pressure ring; the polycrystalline silicon field plate is arranged above the surface of the compression ring and provided with a first via hole; the first dielectric layer is arranged above the surface of the polysilicon field plate, the first dielectric layer is provided with a second via hole and a third via hole, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are arranged on the surface of the first dielectric layer at intervals; the metal field plate is arranged above the surface of the first dielectric layer, the metal field plate is provided with a first electric connection bulge and a second electric connection bulge, the first electric connection bulge sequentially penetrates through the second through hole and the first through hole and is electrically connected with the pressure-resistant ring, and the second electric connection bulge penetrates through the third through hole and is electrically connected with the polysilicon field plate. Therefore, the voltage resistance ring, the polysilicon field plate and the metal field plate can be equipotential, so that the voltage resistance capability and the reliability of the semiconductor device are improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device.
Background
For the semiconductor device, the PN junction at the edge of the chip is a curved surface, the electric field lines are relatively concentrated at the position, the field strength of the electric field is strong, the voltage born by unit length is large, and voltage breakdown is easy to occur at the position. In order to improve the situation, terminal structures are designed at the edges of the chip, so that electric field distribution is optimized, and breakdown voltage is improved. Furthermore, a metal field plate can be designed at the last pressure-resistant ring to improve the electric field distribution at the cut-off ring, and the pressure resistance and the reliability of the device are improved.
In the related art, for the terminal of the structure of the polysilicon field plate, a dielectric layer exists between the polysilicon field plate and the metal field plate at the last pressure-resistant ring, and the dielectric layer separates the metal field plate from the polysilicon field plate, so that the metal field plate and the polysilicon field plate are not contacted with each other, and the potentials of the metal field plate and the polysilicon field plate are different; or when the field oxide exists above the terminal well region, the polysilicon field plate, the metal field plate and the well region are not contacted with each other, so that a floating electric field is formed, the electric field distribution of the region is affected, and the reliability is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to propose a semiconductor device which is higher in withstand voltage capability and reliability.
The semiconductor device according to an embodiment of the present invention includes: a drift layer of the first conductivity type; a second conductivity type voltage-resistant ring provided at a portion of the drift layer corresponding to a terminal region of the semiconductor device; the polycrystalline silicon field plate is arranged above the surface of the pressure-resistant ring and is electrically connected with the pressure-resistant ring, and the polycrystalline silicon field plate is provided with a first via hole; the first dielectric layer is arranged above the surface of the polysilicon field plate, a second via hole and a third via hole are formed in the first dielectric layer, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are arranged on the surface of the first dielectric layer at intervals; the metal field plate is arranged above the surface of the first dielectric layer, the metal field plate is provided with a first electric connection bulge and a second electric connection bulge, the first electric connection bulge sequentially penetrates through the second through hole and the first through hole and is electrically connected with the pressure-resistant ring, and the second electric connection bulge penetrates through the third through hole and is electrically connected with the polysilicon field plate.
Therefore, the first electric connection bulge sequentially penetrates through the second through hole and the first through hole and is electrically connected with the voltage-resistant ring, the second electric connection bulge penetrates through the third through hole and is electrically connected with the polysilicon field plate, and the voltage-resistant ring, the polysilicon field plate and the metal field plate can be equipotential, so that the voltage-resistant capability and the reliability of the semiconductor device are improved.
In some examples of the present invention, the second via and the first via are disposed above within two side boundaries of the voltage-resistant ring, and two sides of the metal field plate and the polysilicon field plate respectively extend out of two side boundaries of the voltage-resistant ring.
In some examples of the invention, the first via has a larger pore size than the second via.
In some examples of the present invention, the first electrical connection protrusion is circumferentially spaced from the polysilicon field plate corresponding to an inner wall of the first via.
In some examples of the present invention, the plurality of first vias are arranged at intervals on the surface of the polysilicon field plate, the plurality of first electrical connection protrusions are arranged, and the plurality of first electrical connection protrusions and the plurality of first vias are in one-to-one correspondence.
In some examples of the present invention, the semiconductor device further includes a field oxide layer disposed above the surface of the pressure-resistant ring and between the polysilicon field plate and the pressure-resistant ring, the field oxide layer being provided with a fourth via hole corresponding to the first via hole and the second via hole, the first electrical connection protrusion penetrating through the second via hole, the first via hole and the fourth via hole in order and being electrically connected to the pressure-resistant ring.
In some examples of the invention, the aperture of the fourth via is equal to the aperture of the second via.
In some examples of the present invention, the semiconductor device further includes an active region and a transition region, the transition region is disposed between the active region and the terminal region, the number of the voltage-resistant rings is plural, the polysilicon field plate and the metal field plate are disposed above one of the voltage-resistant rings, which is far from the transition region, correspondingly.
In some examples of the present invention, the number of the pressure-resistant rings is a plurality, the pressure-resistant rings are arranged at intervals, and the polysilicon field plate and the metal field plate are correspondingly arranged above at least one of the pressure-resistant rings.
In some examples of the present invention, the polysilicon field plates are plural, the plural polysilicon field plates are disposed at intervals, the plural polysilicon field plates are each provided with a first via hole, a second dielectric layer is disposed between two adjacent polysilicon field plates, the first via holes on the plural polysilicon field plates correspond to each other, the second dielectric layer is provided with a fifth via hole, the fifth via hole corresponds to the first via hole, and the first electrical connection protrusion penetrates through the fifth via hole, the first via hole, the second via hole, and is electrically connected with the voltage-resistant ring.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a partial cross-sectional view of another location of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;
fig. 5 is a partial schematic view of a polysilicon field plate in accordance with an embodiment of the present invention.
Reference numerals:
100. a semiconductor device; 101. a termination region; 102. an active region; 103. a transition zone;
10. a drift layer;
20. a pressure ring;
30. a polysilicon field plate; 31. a first via;
40. a first dielectric layer; 41. a second via; 42. a third via;
50. a metal field plate; 51. A first electrical connection protrusion; 52. A second electrical connection protrusion;
60. a field oxide layer; 61. A fourth via;
70. a field stop layer; 80. a collector layer; 90. a collector metal layer.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device 100 according to an embodiment of the present invention is described below with reference to fig. 1 to 5. The semiconductor device 100 is, for example, an IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor). In the following description, N and P denote conductivity types of semiconductors, and in the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type.
As shown in connection with fig. 1, a semiconductor device 100 according to the present invention may mainly include: a drift layer 10 of a first conductivity type, a voltage-resistant ring 20 of a second conductivity type, a polysilicon field plate 30, a first dielectric layer 40 and a metal field plate 50.
Specifically, the first conductive type field stop layer 70 is disposed under the first conductive type drift layer 10, the second conductive type collector layer 80 is disposed under the field stop layer 70, and the collector metal layer 90 is disposed under the collector layer 80, so that a basic structure of a semiconductor structure can be formed, and normal operation of the semiconductor device 100 is ensured.
In view of the fact that the field strength of the electric field in the termination region 101 of the semiconductor device 100 is high, the voltage applied per unit length is high, and voltage breakdown is relatively likely to occur there, the voltage resistance ring 20 is provided on the surface of the drift layer 10 at a portion corresponding to the termination region 101 of the semiconductor device, so that the voltage resistance ring 20 can optimize the electric field distribution in the termination region 101 and improve the voltage resistance capability of the termination region 101.
Further, as shown in fig. 1 and 3, the polysilicon field plate 30 is disposed above the surface of the pressure ring 20 and is electrically connected with the pressure ring 20 correspondingly, the polysilicon field plate 30 is provided with a first via hole 31, the first dielectric layer 40 is disposed above the surface of the polysilicon field plate 30, the first dielectric layer 40 is provided with a second via hole 41 and a third via hole 42, the second via hole 41 corresponds to the first via hole 31, the third via hole 42 and the second via hole 41 are disposed at intervals on the surface of the first dielectric layer 40, the metal field plate 50 is provided with a first electrical connection protrusion 51 and a second electrical connection protrusion 52, the first electrical connection protrusion 51 sequentially penetrates through the second via hole 41 and the first via hole 31 and is electrically connected with the pressure ring 20, and the second electrical connection protrusion 52 penetrates through the third via hole 42 and is electrically connected with the polysilicon field plate 30.
Specifically, considering that there is a curved surface at the normal PN junction, since the electric field at the curved junction is greater, the semiconductor device 100 is liable to break down at these places, by disposing the polysilicon field plate 30 above the surface of the voltage-resistant ring 20, disposing the first dielectric layer 40 above the surface of the polysilicon field plate 30, and disposing the metal field plate 50 above the surface of the first dielectric layer 40, the main junction depletion region can be effectively widened outwards, the electric field concentration phenomenon can be avoided, and the breakdown voltage can be improved, so that the voltage-resistant capability of the termination region 101 and thus the semiconductor device 100 can be further improved.
Further, by providing the first via hole 31 in the polysilicon field plate 30, providing the second via hole 41 in the first dielectric layer 40, the first via hole 31 corresponds to the second via hole 41, and providing the first electrical connection protrusion 51 in the metal field plate 50, the first electrical connection protrusion 51 may sequentially penetrate through the second via hole 41 and the first via hole 31, and the first electrical connection protrusion 51 may be electrically connected with the voltage-resistant ring 20 in a contact manner, so that electrical connection between the metal field plate 50 and the voltage-resistant ring 20 may be realized, and the metal field plate 50 and the voltage-resistant ring 20 may be equipotential.
Further, by providing the third via hole 42 in the first dielectric layer 40 and correspondingly providing the second electrical connection protrusion 52 in the metal field plate 50, only the second electrical connection protrusion 52 needs to be penetrated through the third via hole 42, and the second electrical connection protrusion 52 can be in contact electrical connection with the polysilicon field plate 30, so that electrical connection between the metal field plate 50 and the polysilicon field plate 30 can be realized, and the metal field plate 50 and the polysilicon field plate 30 can be equipotential.
In a specific embodiment of the present invention, the third via hole 42 and the second via hole 41 are disposed at intervals on the surface of the first dielectric layer 40, and thus the lengths of the polysilicon field plate 30 in the left-right direction need to be correspondingly extended, so that the polysilicon field plate 30 can be corresponding to the second via hole 41 and the third via hole 42, and further the area of the polysilicon field plate 30 can be increased, the electric field modulation capability of the polysilicon field plate 30 to the terminal area 101 can be improved, the electric field concentration can be avoided, the electric field distribution of the terminal area 101 is more uniform, and further the breakdown voltage of the semiconductor device 100 is further improved, and the voltage withstanding capability of the semiconductor device 100 is improved.
And, third via hole 42 and second via hole 41 set up at the surface interval of first dielectric layer 40, first electric connection protruding 51 and second electric connection protruding 52 also correspond the interval setting on metal field plate 50, so not only make things convenient for second via hole 41 and first via hole 31 to set up on first dielectric layer 40, and make things convenient for first electric connection protruding 51 and second electric connection protruding 52 to set up on metal field plate 50, can reduce the manufacturing degree of difficulty, and can make first electric connection protruding 51 wear to establish first via hole 31 and second via hole 41, wear to establish third via hole 42 with second electric connection protruding 52 and go on simultaneously, can improve assembly efficiency.
In this way, the equipotential of the voltage-resistant ring 20, the polysilicon field plate 30 and the metal field plate 50 can be realized, so that the floating electric field caused by the non-interconnection of a certain structure can be avoided, the problem that the voltage resistance and the reliability are reduced due to the uneven electric field distribution of the terminal area 101 caused by the external interference of the floating electric field when the semiconductor device 100 works can be avoided, the voltage-resistant capability of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.
Accordingly, the first electrical connection bump 51 is electrically connected to the voltage-resistant ring 20 by penetrating the second via 41 and the first via 31 in this order, and the second electrical connection bump 52 is electrically connected to the polysilicon field plate 30 by penetrating the third via 42, so that the voltage-resistant ring 20, the polysilicon field plate 30, and the metal field plate 50 are equipotential, thereby improving the voltage-resistant capability and reliability of the semiconductor device 100.
As shown in fig. 1-4, the second via 41 and the first via 31 are disposed above the two side boundaries of the voltage-resistant ring 20, and two sides of the metal field plate 50 and the polysilicon field plate 30 respectively extend out of the two side boundaries of the voltage-resistant ring 20.
Specifically, by arranging the second via hole 41 and the first via hole 31 above the boundaries of the two sides of the pressure-resistant ring 20, after the first electrical connection protrusion 51 on the metal field plate 50 sequentially penetrates through the second via hole 41 and the first via hole 31, the metal field plate 50 can be directly in contact electrical connection with the pressure-resistant ring 20, and the end part of the first electrical connection protrusion 51 can be ensured to be in full contact with the pressure-resistant ring 20, so that not only can the realization of the electrical connection between the metal field plate 50 and the pressure-resistant ring 20 be simpler, but also the sufficient contact area between the metal field plate 50 and the pressure-resistant ring 20 can be ensured, the stability of the electrical connection between the metal field plate 50 and the pressure-resistant ring 20 can be ensured, and the equipotential between the metal field plate 50 and the pressure-resistant ring 20 can be ensured more stably and reliably.
Further, the two sides of the metal field plate 50 and the polysilicon field plate 30 respectively extend out of the two side boundaries of the voltage-resistant ring 20, so that the electric field modulation capability of the metal field plate 50 and the polysilicon field plate 30 to the termination region 101 can be improved, the electric field concentration can be avoided, the electric field distribution of the termination region 101 is more uniform, the breakdown voltage of the semiconductor device 100 can be further improved, and the voltage-resistant capability of the semiconductor device 100 can be improved.
As shown in fig. 3 and 4, the aperture of the first via hole 31 is larger than the aperture of the second via hole 41. Specifically, the polysilicon field plate 30 is located below the first dielectric layer 40, in the production process, the first via hole 31 may be first formed in the polysilicon field plate 30, then the first dielectric layer 40 is disposed on the polysilicon field plate 30, and then the second via hole 41 is correspondingly formed in the first dielectric layer 40, and by setting the aperture of the first via hole 31 to be larger than the aperture of the second via hole 41, the influence on the shape and size of the first via hole 31 when the second via hole 41 is formed can be avoided, so that the reliability of the polysilicon field plate 30 and the semiconductor device 100 can be ensured.
Further, as shown in fig. 3, the first electrical connection protrusions 51 are circumferentially spaced from the polysilicon field plate 30 corresponding to the inner walls of the first via holes 31. Specifically, the first electrical connection protrusion 51 sequentially penetrates through the first through hole and the second through hole, and the first electrical connection protrusion 51 and the polysilicon are circumferentially arranged at intervals corresponding to the inner wall of the first via hole 31, so that the first electrical connection protrusion 51 can be conveniently penetrated through the first via hole 31, damage to the inner wall of the polysilicon field plate 30 corresponding to the first via hole 31 in the penetrating process of the first electrical connection protrusion 51 can be avoided, and the reliability of the semiconductor device 100 can be improved.
As shown in connection with fig. 5, the first via hole 31 has at least one of a square, a rectangle, a circle, and a diamond shape. Specifically, the shape of the first via hole 31 may be at least one of square, rectangle, circle, and diamond, and correspondingly, the shape of the second via hole 41 and the shape of the cross section of the first electrical connection protrusion 51 may be designed, so that the shape of the first via hole 31 may be simple, the opening of the first via hole 31 and the second via hole 41 may be convenient, and the manufacturing of the first electrical connection protrusion 51 may be reduced, and the production difficulty of the semiconductor device 100 may be reduced.
Further, as shown in fig. 5, the first vias 31 are plural, the first vias 31 are disposed on the upper surface of the polysilicon field plate 30 at intervals, the first electrical connection protrusions 51 are plural, and the first electrical connection protrusions 51 and the first vias 31 are in one-to-one correspondence.
Specifically, the number of the first via holes 31 may be plural, and correspondingly, the number of the first electrical connection protrusions 51 and the second via holes 41 may be plural, so that the plurality of first electrical connection protrusions 51 and the plurality of first via holes 31 may be in one-to-one correspondence, and the plurality of first electrical connection protrusions 51 may penetrate through the plurality of first via holes 31 and the plurality of second via holes 41 to be in contact electrical connection with the pressure-resistant ring 20, thereby enabling the metal field plate 50 and the pressure-resistant ring 20 to have plural electrical connections, further improving stability and reliability of electrical connection between the metal field plate 50 and the pressure-resistant ring 20, and ensuring an equipotential between the metal field plate 50 and the pressure-resistant ring 20 more stably and reliably.
It should be noted that, the plurality of first vias 31 are disposed at intervals on the polysilicon field plate 30, so that it can be ensured that the polysilicon field plate 30 remains as a whole without breaking after being perforated.
As shown in fig. 4, the semiconductor device 100 may further include a field oxide layer 60, where the field oxide layer 60 is disposed above the surface of the voltage-resistant ring 20 and at least partially located between the polysilicon field plate 30 and the voltage-resistant ring 20, the field oxide layer 60 is provided with a fourth via 61, the fourth via 61 corresponds to the first via 31 and the second via 41, and the first electrical connection protrusion 51 sequentially penetrates the second via 41, the first via 31 and the fourth via 61 and is electrically connected to the voltage-resistant ring 20.
Specifically, a field oxide layer 60 may exist between the voltage-resistant ring 20 and the polysilicon field plate 30, the field oxide layer 60 may isolate the voltage-resistant ring 20 from the polysilicon field plate 30 and the first electrical connection protrusion 51 of the metal field plate 50, resulting in failure of electrical connection between the voltage-resistant ring 20 and the metal field plate 50, and the fourth via hole 61 corresponding to the first via hole 31 and the second via hole 41 is formed in the field oxide layer 60, so that the field oxide between the polysilicon field plate 30 and the voltage-resistant ring 20 may be at least partially removed, and after the first electrical connection protrusion 51 may sequentially penetrate the second via hole 41, the first via hole 31 and the fourth via hole 61, the first electrical connection protrusion 51 may be electrically connected to the voltage-resistant ring 20, i.e.: contact electrical connection between the metal field plate 50 and the voltage-resistant ring 20 can be achieved, thereby ensuring an equipotential of the voltage-resistant ring 20 and the metal field plate 50.
Further, as shown in fig. 4, the aperture of the fourth via hole 61 is equal to the aperture of the second via hole 41, so that the first electrical connection protrusion 51 can smoothly pass through the fourth via hole 61, which is convenient for the electrical connection between the metal field plate 50 and the voltage-resistant ring 20, and the fourth via hole 61 and the second via hole 41 can be conveniently formed synchronously, thereby improving the production efficiency of the semiconductor device 100.
As shown in fig. 1, the semiconductor device 100 includes an active region 102 and a transition region 103, the transition region 103 is disposed between the active region 102 and the termination region 101, and a plurality of the compressive rings 20 are disposed at intervals.
Specifically, the active region 102 may not only bear most of the forward current during forward conduction, but also bear high blocking voltage when a reverse voltage is applied, and the termination region 101 may relieve electric field crowding at the edge of the active region 102 when the semiconductor device 100 is applied with the reverse voltage, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.
In view of the large voltage borne by the termination region 101, the plurality of voltage-resistant rings 20 are arranged in the termination region 101 such that the plurality of voltage-resistant rings 20 are arranged at intervals, and thus the plurality of voltage-resistant rings 20 can further optimize the electric field distribution of the termination region 101 and increase the breakdown voltage of the termination region 101, thereby improving the voltage-resistant capability of the termination region 101.
In some embodiments of the present invention, as shown in connection with fig. 1, a polysilicon field plate 30 and a metal field plate 50 are correspondingly disposed above one of the plurality of compressive rings 20 that is far from the transition region 103. Specifically, one of the plurality of voltage-resistant rings 20 far from the transition region 103 bears the greatest voltage, and the polysilicon field plate 30 and the metal field plate 50 are correspondingly arranged above the voltage-resistant rings, so that the structure of the semiconductor device 100 is simplified and the production difficulty and the production cost of the semiconductor device 100 are reduced on the premise that the voltage-resistant capability and the reliability of the terminal region 101 can be improved.
In other embodiments of the present invention, at least one of the plurality of compressive rings 20 is provided with a polysilicon field plate 30 and a metal field plate 50, respectively, thereabove. Specifically, the polysilicon field plates 30 and the metal field plates 50 may be disposed above at least one of the plurality of voltage-resistant rings 20, so that the number of the polysilicon field plates 30 and the metal field plates 50 may be increased, thereby further optimizing the electric field distribution of the termination region 101, further improving the voltage-resistant capability of the termination region 101 and the semiconductor device 100, and improving the reliability of the semiconductor device 100.
Of course, no matter the polysilicon field plate 30 and the metal field plate 50 are correspondingly disposed above one of the plurality of pressure-resistant rings 20 far from the transition region 103, or the polysilicon field plate 30 and the metal field plate 50 are correspondingly disposed above at least one of the plurality of pressure-resistant rings 20, the equipotential of the polysilicon field plate 30, the first dielectric layer 40 and the metal field plate 50 needs to be ensured, which is not described herein.
In some embodiments of the present invention, the polysilicon field plates 30 are plural, the plural polysilicon field plates 30 are disposed at intervals, the plural polysilicon field plates 30 are each provided with a first via hole 31, a second dielectric layer is disposed between two adjacent polysilicon field plates 30, the first via holes 31 on the plural polysilicon field plates 30 correspond to each other, the second dielectric layer is provided with a fifth via hole corresponding to the first via hole 31, and the first electrical connection protrusion 51 penetrates through the fifth via hole, the first via hole 31 and the second via hole 41 and is electrically connected with the voltage-resistant ring 20.
Specifically, when the termination region 101 includes a plurality of polysilicon field plates 30 disposed at intervals and a second dielectric layer is disposed between the plurality of polysilicon field plates 30, first vias 31 corresponding to each other may be disposed on the plurality of polysilicon field plates 30 and fifth vias corresponding to the first vias 31 may be disposed on the second dielectric layer, so that the first electrical connection protrusions 51 may simultaneously penetrate the plurality of fifth vias, the plurality of first vias 31 and the plurality of second vias 41 and electrically connect with the voltage-resistant ring 20, thereby enabling the metal field plates 50 and the voltage-resistant ring 20 to be electrically connected to each other, and the plurality of polysilicon field plates 30 may also be electrically connected to the metal field plates 50 by perforating the polysilicon field plates 30 and the second dielectric layer disposed above thereof, so that even though the plurality of polysilicon field plates 30 are included, an improvement in electric field distribution of the termination region 101 may be ensured, and the voltage-resistant capability and reliability of the semiconductor device 100 may be improved.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a drift layer of the first conductivity type;
a second conductivity type voltage-resistant ring provided at a portion of the drift layer corresponding to a terminal region of the semiconductor device;
the polycrystalline silicon field plate is arranged above the surface of the pressure-resistant ring and provided with a first via hole;
the first dielectric layer is arranged above the surface of the polysilicon field plate, a second via hole and a third via hole are formed in the first dielectric layer, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are arranged on the surface of the first dielectric layer at intervals;
the metal field plate is arranged above the surface of the first dielectric layer, the metal field plate is provided with a first electric connection bulge and a second electric connection bulge, the first electric connection bulge sequentially penetrates through the second through hole and the first through hole and is electrically connected with the pressure-resistant ring, and the second electric connection bulge penetrates through the third through hole and is electrically connected with the polysilicon field plate.
2. The semiconductor device of claim 1, wherein the second via and the first via are disposed above within two side boundaries of the voltage-resistant ring, and two sides of the metal field plate and the polysilicon field plate extend beyond two side boundaries of the voltage-resistant ring, respectively.
3. The semiconductor device of claim 1, wherein a pore size of the first via is larger than a pore size of the second via.
4. The semiconductor device of claim 3, wherein the first electrical connection bumps are circumferentially spaced apart from the inner wall of the polysilicon field plate corresponding to the first vias.
5. The semiconductor device according to claim 3, wherein the plurality of first vias are arranged on the surface of the polysilicon field plate at intervals, the plurality of first electrical connection bumps are arranged in a plurality, and the plurality of first electrical connection bumps and the plurality of first vias are in one-to-one correspondence.
6. The semiconductor device of claim 1, further comprising a field oxide layer disposed above the surface of the pressure resistant ring and between the polysilicon field plate and the pressure resistant ring, the field oxide layer being provided with a fourth via corresponding to the first via and the second via, the first electrical connection bump passing through the second via, the first via, and the fourth via in sequence and electrically connected to the pressure resistant ring.
7. The semiconductor device according to claim 6, wherein an aperture of the fourth via is equal to an aperture of the second via.
8. The semiconductor device according to claim 1, further comprising an active region and a transition region, wherein the transition region is disposed between the active region and the terminal region, the plurality of voltage-resistant rings are disposed at intervals, and the polysilicon field plate and the metal field plate are disposed above one of the plurality of voltage-resistant rings away from the transition region.
9. The semiconductor device according to claim 1, wherein the number of the pressure-resistant rings is plural, the plurality of the pressure-resistant rings are arranged at intervals, and the polysilicon field plate and the metal field plate are arranged above at least one of the plurality of the pressure-resistant rings.
10. The semiconductor device according to claim 1, wherein the plurality of polysilicon field plates are arranged at intervals, the plurality of polysilicon field plates are each provided with a first via hole, a second dielectric layer is arranged between two adjacent polysilicon field plates, the first via holes on the plurality of polysilicon field plates correspond to each other, the second dielectric layer is provided with a fifth via hole, the fifth via hole corresponds to the first via hole, and the first electrical connection protrusion penetrates through the fifth via hole, the first via hole, the second via hole, and the voltage-resistant ring.
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| CN202311118361.1A CN117116974A (en) | 2023-08-31 | 2023-08-31 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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| CN202311118361.1A CN117116974A (en) | 2023-08-31 | 2023-08-31 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101719509A (en) * | 2009-11-10 | 2010-06-02 | 深圳深爱半导体有限公司 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor |
| CN102779840A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer |
| CN103534809A (en) * | 2011-08-05 | 2014-01-22 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN104995736A (en) * | 2013-02-15 | 2015-10-21 | 丰田自动车株式会社 | Semiconductor device and method of producing same |
| US20190067415A1 (en) * | 2016-09-17 | 2019-02-28 | University Of Electronic Science And Technology Of China | Folded Termination with Internal Field Plate |
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- 2023-08-31 CN CN202311118361.1A patent/CN117116974A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719509A (en) * | 2009-11-10 | 2010-06-02 | 深圳深爱半导体有限公司 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor |
| CN103534809A (en) * | 2011-08-05 | 2014-01-22 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN102779840A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer |
| CN104995736A (en) * | 2013-02-15 | 2015-10-21 | 丰田自动车株式会社 | Semiconductor device and method of producing same |
| US20190067415A1 (en) * | 2016-09-17 | 2019-02-28 | University Of Electronic Science And Technology Of China | Folded Termination with Internal Field Plate |
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