CN104332491A - Terminal unit structure with metal extending and polycrystal stopping field plates and method for manufacturing terminal unit structure - Google Patents
Terminal unit structure with metal extending and polycrystal stopping field plates and method for manufacturing terminal unit structure Download PDFInfo
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- CN104332491A CN104332491A CN201410614947.1A CN201410614947A CN104332491A CN 104332491 A CN104332491 A CN 104332491A CN 201410614947 A CN201410614947 A CN 201410614947A CN 104332491 A CN104332491 A CN 104332491A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 186
- 239000002184 metal Substances 0.000 title claims abstract description 186
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 230000004888 barrier function Effects 0.000 claims description 96
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052782 aluminium Inorganic materials 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 229910019213 POCl3 Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 39
- 230000000694 effects Effects 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 description 29
- 239000010949 copper Substances 0.000 description 16
- 239000010931 gold Substances 0.000 description 7
- 239000010944 silver (metal) Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to the power electronic technical field and particularly relates to a terminal unit structure with metal extending and polycrystal stopping field plates and a method for manufacturing the terminal unit structure. The terminal unit structure comprises a first conductive type substrate, a second conductive type field limit ring is arranged in a first main side of the first conductive type substrate, and a first insulation layer is arranged on a first main plane of the first conductive type substrate. The two field plates are disposed on the first insulation layer and cover the two sides of the second conductive type field limit ring. The field plates comprise the polycrystal stopping field plate and the metal extending field plate, and one end of the metal field plate is connected with the polycrystal stopping field plate. According to the terminal unit structure, polycrystals are used as the stopping field plate, metal is used as the extending field plate, the electric field stopping effect is good, breakdown of the first insulation layer brought by electric field extending is prevented, and dependency on the thickness of the first insulation layer is small.
Description
Technical field
The present invention relates to electric and electronic technical field, be specially and adopt terminal unit architecture and the manufacture method that metal extends, polycrystalline ends field plate.
Background technology
In the manufacturing and designing of power electronic device, terminal is an indispensable part, and it can make device inside depletion region become level and smooth when device bears high-tension, thus allows device bear higher voltage.The terminal of traditional power electronic device is generally and sinks to the bottom by injecting and advancing at low-doped, prepares field limiting ring; Also have and add that field plate is to realize the level and smooth further of electric field laterally on field limiting ring.
Relative to independent field limiting ring structure; the structure of field limiting ring+field plate can better level and smooth depletion region; therefore on the Terminal Design of identical pressure-bearing; the number of the ring that the design of field limiting ring+field plate needs than the design of independent field limiting ring is few; simultaneously field plate can the terminal of protect IC not by outside contamination, therefore there is better breakdown characteristics and device stability.
In addition, in the manufacture process of power electronic device, active region determines the important electrical characteristic of device, the part although terminal is absolutely necessary, but only affect puncture voltage and the stability of device, do not contribute the conduction voltage drop of device and turn-off time, therefore terminal is on the basis meeting the pressure-bearing required by device, and the area of terminal is the smaller the better.
The more than total junction device problem of two kinds of Terminal Designs, can be summed up as:
The structure of field plate protection device terminal can exempt from pollution, therefore needs the area increasing field plate as far as possible; And the area of terminal needs little as much as possible, increases the area of active region.And the area increasing field plate refers under the terminal prerequisite of certain size, increase field plate and cover the ratio of terminal, because the ratio that field plate covers terminal is larger, the ratio that terminal comes out is less, do not expose like this be exactly be not easy contaminated.
Existing Patents has: the patent No. is CN201010246809.4, the applying date is 2010-08-06, name is called the patent of invention of " a kind of edge termination structure of high voltage power semiconductor device ", its technology contents is: the edge termination structure that the invention discloses a kind of high voltage power semiconductor device, comprise several by power semiconductor around, with substrate, there is the field limiting ring of films of opposite conductivity, at each field limiting ring, one-sided or both sides are provided with identical with field limiting ring conduction type, doping content is less than the doped region of field limiting ring, field limiting ring is covered with field plate, silicon dioxide layer interval is used between field limiting ring and field plate.The material of field plate can be selected from copper, aluminium, polysilicon or oxygen-doped polysilicon etc.
For another example the patent No. is CN201010246816.4, the applying date is 2010-08-06, name is called the patent of invention of " a kind of edge termination structure of high voltage power semiconductor device ", its technology contents is: the edge termination structure that the invention discloses a kind of high voltage power semiconductor device, comprise several by power semiconductor around, with substrate, there is the field limiting ring of films of opposite conductivity, be provided with identical with field limiting ring conduction type around field limiting ring, doping content is less than the doped region of field limiting ring, field limiting ring wraps up by this doped region, field limiting ring is covered with field plate, silicon dioxide layer interval is used between field limiting ring and field plate.The material of field plate can be selected from copper, aluminium, polysilicon or oxygen-doped polysilicon etc.
Wherein CN201010246809.4 with CN201010246816.4 is identical with the object that this patent is protected; it is all a kind of semiconductor device itself " terminal structure "; but at the design of terminal structure and terminal structure functionally; both are different; these two patents above-mentioned are all reduce the electric field at field limiting ring place by the design of different field limiting rings and puncture voltage can be increased; be disjunct between their field plate and field limiting ring, field plate does not play the effect reducing electric field.
Summary of the invention
In order to overcome the problems referred to above that existing semiconductor chip terminal unit architecture exists, the terminal unit architecture of special proposition employing metal extension now, polycrystalline cut-off field plate and manufacture method, this design has larger field plate area coverage, can increase the stability of device; And have employed the design of cut-off field plate, the area of terminal can be reduced further.
Concrete scheme of the present invention is as follows:
Adopt the terminal unit architecture that metal extends, polycrystalline ends field plate, it is characterized in that: comprise the first conductivity type substrate, the second conduction type field limiting ring is provided with in first interarea of described first conductivity type substrate, on the primary principal plane of described first conductivity type substrate, be provided with the first insulating barrier; On described first insulating barrier and the both sides being positioned at the second conduction type field limiting ring are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier, and described second insulating barrier is provided with Metal field plate; The bottom of described Metal field plate contacts with the second conduction type field limiting ring, and described Metal field plate covers region and the both sides thereof of the second conduction type field limiting ring;
Described two blocks of field plates to be positioned at above the first insulating barrier and to cover the both sides of the second conduction type field limiting ring, and described field plate comprises polycrystalline cut-off field plate and metal extends field plate, and one end and the polycrystalline of described Metal field plate end field plate contact and be connected.
Described Metal field plate and polycrystalline end one end that field plate is connected along its lateral direction and bend downwards.
The other end of described Metal field plate and metal extend field plate and be arranged in parallel.
Described polycrystalline cut-off field plate is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate.
Further, described second insulating barrier is positioned at above field plate, covers whole field plate.
Further, described Metal field plate is positioned at above the second insulating barrier, and cover the region of whole second conduction type field circulation, described Metal field plate is connected with the second conduction type field limiting ring.
Further, described Metal field plate covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate is ended field plate contact by the electrode contact hole on the second insulating barrier with polycrystalline and is connected.
Further, the second interarea place of described first conductivity type substrate, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
Further, the first conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate is silicon substrate, and the first interarea of the first conductivity type substrate is its front, and the second interarea of the first conductivity type substrate is its back side.
Further, the diffusion depth of described second conduction type field limiting ring is 1um-10um; Described first insulating barrier is silicon dioxide layer, and thickness is 0.5um ~ 5um; Polycrystalline cut-off field plate width in described field plate is 0 um ~ 30um; It is 0 um ~ 50um that metal in field plate extends field plate width.
Adopt the manufacture method that metal extends, polycrystalline ends the terminal unit architecture of field plate, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate, the first insulating barrier is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and polycrystalline cut-off field plate and metal and extend field plate;
G. deposit the second insulating barrier by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate, make metal level by evaporating or sputtering, and form Metal field plate by photoetching, wet etching.
Further, described second conduction type field limiting ring doping content is higher than the doping content of the first conductivity type substrate; Described second insulating barrier is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
The invention has the advantages that:
1, the terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring, and polycrystalline cut-off field plate can compress electric field, and metal extends field plate can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.The present invention uses polycrystalline to serve as cutoff field version, uses metal to serve as and extends field version, and the effect of such electric field cut-off is best, avoids electric field simultaneously and extends the first insulating barrier brought and puncture, smaller to the thickness dependence of the first insulating barrier.
2, the polycrystalline that introduces of the application ends field plate, arrange simultaneously polycrystalline cut-off field plate and metal extend field plate for the design of traditional field limiting ring+field plate, under limited area, increase the area that device field plate covers, and can ensure that the width of terminal is in very among a small circle.
3, the field plate of the application is large due to the ratio covering terminal, can play the not contaminated effect of protection terminal.
4, compared to traditional field limiting ring+field plate termination structure, the application adds polycrystalline cut-off field plate, on the basis keeping total area constant, makes the area coverage of field plate larger, decreases the pollution of outer bound pair terminal, the stability of device is got a promotion.
5, the application is compared to traditional field limiting ring+field plate termination structure, present invention adds polycrystalline cut-off field plate, the area of whole terminal is reduced, so just relatively expands the active area of device, the electrology characteristic of device is improved further.
Accompanying drawing explanation
Fig. 1 is the application's overall structure schematic diagram.
The corresponding technique A of Fig. 2.
Fig. 3 corresponding technique B, C.
Fig. 4 corresponding technique D, E.
The corresponding technique F of Fig. 5.
Fig. 6,7 corresponding technique G.
Fig. 8,9 corresponding technique I.
110: the first conductivity type substrate in accompanying drawing; 120: the second conduction type field limiting rings; 130: the first insulating barriers; 141: polycrystalline cut-off field plate; 142: metal extends field plate; 150: the second insulating barriers; 160: Metal field plate.
Embodiment
Embodiment 1
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120; Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
Embodiment 2
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
Embodiment 3
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um-10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um ~ 5um; Polycrystalline cut-off field plate 141 width in described field plate is 0 um ~ 30um; It is 0 um ~ 50um that metal in field plate extends field plate 142 width.
Embodiment 4
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um; Polycrystalline cut-off field plate 141 width in described field plate is 30um; It is 50um that metal in field plate extends field plate 142 width.
Embodiment 5
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 5um; Polycrystalline cut-off field plate 141 width in described field plate is 10um; It is 20um that metal in field plate extends field plate 142 width.
Embodiment 6
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 4um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 3.1um; Polycrystalline cut-off field plate 141 width in described field plate is 20um; It is 35um that metal in field plate extends field plate 142 width.
Embodiment 7
Adopt the manufacture method that metal extends, polycrystalline ends the terminal unit architecture of field plate, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate 110, the first insulating barrier 130 is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier 130 is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring 120;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and polycrystalline cut-off field plate 141 and metal and extend field plate 142;
G. deposit the second insulating barrier 150 by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate 110, make metal level by evaporating or sputtering, and form Metal field plate 160 by photoetching, wet etching.
Described second conduction type field limiting ring 120 doping content is higher than the doping content of the first conductivity type substrate 110; Described second insulating barrier 150 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
Embodiment 8
The terminal unit architecture that metal extends, polycrystalline ends field plate is adopted to comprise the first conductivity type substrate 110, the second conduction type field limiting ring 120 is provided with in first interarea of described first conductivity type substrate 110, on the primary principal plane of described first conductivity type substrate 110, be provided with the first insulating barrier 130; On described first insulating barrier 130 and the both sides being positioned at the second conduction type field limiting ring 120 are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier 150, and described second insulating barrier 150 is provided with Metal field plate 160; The bottom of described Metal field plate 160 contacts with the second conduction type field limiting ring 120, and described Metal field plate 160 covers region and the both sides thereof of the second conduction type field limiting ring 120.
Described two blocks of field plates to be positioned at above the first insulating barrier 130 and to cover the both sides of the second conduction type field limiting ring 120, described field plate comprises polycrystalline cut-off field plate 141 and metal extends field plate 142, and one end and the polycrystalline of described Metal field plate 160 end field plate 141 and contact connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor device, and semiconductor device outermost is edge, is terminal inward, then is active region inside.
Described Metal field plate 160 and polycrystalline end one end that field plate 141 is connected along lateral direction and bend downwards.
The other end of described Metal field plate 160 and metal extend field plate 142 and be arranged in parallel.
Described polycrystalline cut-off field plate 141 is polysilicon.
It is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate 142.
Described second insulating barrier 150 is positioned at above field plate, covers whole field plate.
Described Metal field plate 160 is positioned at above the second insulating barrier 150, and cover the region of whole second conduction type field circulation, described Metal field plate 160 is connected with the second conduction type field limiting ring 120.
Described Metal field plate 160 covers region that is whole or part field plate, is provided with electrode contact hole in the region covering field plate; One end of described Metal field plate 160 is ended field plate 141 by the electrode contact hole on the second insulating barrier 150 and polycrystalline and is contacted connected.
Second interarea place of described first conductivity type substrate 110, is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate 110 is silicon substrate, and the first interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, similar structures was not there is in prior art, and its manufacturing process is simple, the application focuses on the architecture advances of field plate, the field plate of the application's design is connected with the second conduction type field limiting ring 120, and polycrystalline cut-off field plate 141 can compress electric field, and metal extends field plate 142 can extend electric field, thus make electric field from new distributing, achieve the effect reducing field limiting ring electric field equally.
The diffusion depth of the second conduction type field limiting ring 120 is 1um-10um; Described first insulating barrier 130 is silicon dioxide layer, and thickness is 0.5um ~ 5um; Polycrystalline cut-off field plate 141 width in described field plate is 0 um ~ 30um; It is 0 um ~ 50um that metal in field plate extends field plate 142 width.
Adopt the manufacture method that metal extends, polycrystalline ends the terminal unit architecture of field plate, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate 110, the first insulating barrier 130 is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier 130 is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring 120;
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and polycrystalline cut-off field plate 141 and metal and extend field plate 142;
G. deposit the second insulating barrier 150 by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate 110, make metal level by evaporating or sputtering, and form Metal field plate 160 by photoetching, wet etching.
Further, described second conduction type field limiting ring 120 doping content is higher than the doping content of the first conductivity type substrate 110; Described second insulating barrier 150 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
Claims (10)
1. adopt the terminal unit architecture that metal extends, polycrystalline ends field plate, it is characterized in that: comprise the first conductivity type substrate (110), the second conduction type field limiting ring (120) is provided with in first interarea of described first conductivity type substrate (110), on the primary principal plane of described first conductivity type substrate (110), be provided with the first insulating barrier (130); Described first insulating barrier (130) is upper and the both sides being positioned at the second conduction type field limiting ring (120) are respectively provided with one block of field plate; Described two blocks of field plates are provided with the second insulating barrier (150), and described second insulating barrier (150) is provided with Metal field plate (160); The bottom of described Metal field plate (160) contacts with the second conduction type field limiting ring (120), and described Metal field plate (160) covers region and the both sides thereof of the second conduction type field limiting ring (120);
Described two blocks of field plates to be positioned at above the first insulating barrier (130) and to cover the both sides of the second conduction type field limiting ring (120), described field plate comprises polycrystalline cut-off field plate (141) and metal extends field plate (142), and one end and the polycrystalline of described Metal field plate (160) end field plate (141) and contact connected.
2. employing metal according to claim 1 extend, the terminal unit architecture of polycrystalline cut-off field plate, it is characterized in that: described Metal field plate (160) and polycrystalline end one end that field plate (141) is connected along lateral direction and bend downwards.
3. the terminal unit architecture that employing metal according to claim 2 extends, polycrystalline ends field plate, is characterized in that: the other end of described Metal field plate (160) and metal extend field plate (142) and be arranged in parallel.
4. the terminal unit architecture that employing metal according to claim 3 extends, polycrystalline ends field plate, is characterized in that: it is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu that metal extends field plate (142).
5. the terminal unit architecture that employing metal according to claim 1 extends, polycrystalline ends field plate, is characterized in that: described second insulating barrier (150) is positioned at above field plate, covers whole field plate.
6. the employing metal according to claim 1-5 any one extends, the terminal unit architecture of polycrystalline cut-off field plate, it is characterized in that: described Metal field plate (160) is positioned at above the second insulating barrier (150), cover the region of whole second conduction type field circulation, described Metal field plate (160) is connected with the second conduction type field limiting ring (120).
7. the terminal unit architecture that employing metal according to claim 6 extends, polycrystalline ends field plate, it is characterized in that: described Metal field plate (160) covers region that is whole or part field plate, be provided with electrode contact hole in the region covering field plate, one end of described Metal field plate (160) is ended field plate (141) by the electrode contact hole on the second insulating barrier (150) and polycrystalline and is contacted connected.
8. the employing metal according to claim 1-5 any one extends, the terminal unit architecture of polycrystalline cut-off field plate is characterized in that: the second interarea place of described first conductivity type substrate (110), is disposed with the first conduction type field cutoff layer, the second conduction type collector electrode and back metal; Within described first conduction type field cutoff layer and the second conduction type collector electrode are positioned at the second interarea lower surface, and back metal is positioned at outside the second interarea lower surface; First conduction type is N-type, and the second conduction type is P type, and described first conductivity type substrate (110) is silicon substrate, and the first interarea of the first conductivity type substrate (110) is its front, and the second interarea of the first conductivity type substrate (110) is its back side.
9. the terminal unit architecture that employing metal according to claim 8 extends, polycrystalline ends field plate, is characterized in that: the diffusion depth of described second conduction type field limiting ring (120) is 1um-10um; Described first insulating barrier (130) is silicon dioxide layer, and thickness is 0.5um ~ 5um; Polycrystalline cut-off field plate (141) width in described field plate is 0 um ~ 30um; It is 0 um ~ 50um that metal in field plate extends field plate (142) width.
10. the manufacture method that employing metal according to claim 1 extends, polycrystalline ends the terminal unit architecture of field plate, is characterized in that: adopt the manufacture method that metal extends, polycrystalline ends the terminal unit architecture of field plate, concrete manufacturing process is:
A., on the first interarea of the first conductivity type substrate (110), the first insulating barrier (130) is grown by the method for thermal oxidation, LPCVD or PECVD;
B. by photoetching, dry etching, the first insulating barrier (130) is etched, formed and inject window region;
C. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type field limiting ring (120);
D. on gate insulator by the method for LPCVD or PECVD, deposition of polysilicon layer;
E. POCl3 is used to adulterate to polysilicon layer;
F. by photoetching, dry etching, polycrystalline silicon gate layer is etched, form window region and polycrystalline cut-off field plate (141) and metal and extend field plate (142);
G. deposit the second insulating barrier (150) by LPCVD or PECVD, by dry etching, form contact hole;
I. on first interarea and the second interarea of the first conductivity type substrate (110), make metal level by evaporating or sputtering, and form Metal field plate (160) by photoetching, wet etching;
Described second conduction type field limiting ring (120) doping content is higher than the doping content of the first conductivity type substrate (110); Described second insulating barrier (150) is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
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