CN104332491B - Extended using metal, the terminal unit architecture and manufacturing method of polycrystalline cut-off field plate - Google Patents
Extended using metal, the terminal unit architecture and manufacturing method of polycrystalline cut-off field plate Download PDFInfo
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- CN104332491B CN104332491B CN201410614947.1A CN201410614947A CN104332491B CN 104332491 B CN104332491 B CN 104332491B CN 201410614947 A CN201410614947 A CN 201410614947A CN 104332491 B CN104332491 B CN 104332491B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 181
- 239000002184 metal Substances 0.000 title claims abstract description 181
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 83
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052782 aluminium Inorganic materials 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 229910019213 POCl3 Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 230000026267 regulation of growth Effects 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 39
- 230000000694 effects Effects 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 description 28
- 239000010949 copper Substances 0.000 description 16
- 239000010931 gold Substances 0.000 description 10
- 239000010944 silver (metal) Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
Abstract
The present invention relates to power electronics fields, specially using metal extension, the terminal unit architecture and manufacturing method of polycrystalline cut-off field plate, including the first conductivity type substrate, the second conduction type field limiting ring is equipped in first interarea of first conductivity type substrate, on the primary principal plane of first conductivity type substrate, equipped with the first insulating layer；Two blocks of field plates are located at first insulating layer the upper surface of and are covered in the both sides of the second conduction type field limiting ring, and the field plate includes polycrystalline cut-off field plate and metal extension field plate, and one end of the Metal field plate is connected with polycrystalline cut-off field plate contact.The present invention serves as cutoff field version using polycrystalline, serves as extension field version using metal, the effect of such electric field cut-off is best, while avoids the first insulating layer breakdown caused by electric field extension, the thickness of the first insulating layer is relied on smaller.
Description
Technical field
The present invention relates to power electronics fields, are specially extended using metal, the terminal unit of polycrystalline cut-off field plate
Structure and manufacturing method.
Background technology
In the design and manufacture of power electronic devices, terminal is an indispensable part, it can bear high electricity in device
Cause that device inside depletion region is smoothened when pressure, so as to which device be allowed to bear higher voltage.Traditional power electronics device
The terminal of part is usually to be sunk to the bottom in low-doped by injecting and promoting, and prepares field limiting ring；Also have above field limiting ring to
Further smoothing for electric field is realized plus field plate in outside.
Compared with individual field limiting ring structure, the structure of field limiting ring+field plate being capable of preferably smooth depletion region, therefore in phase
With on the Terminal Design of pressure-bearing, the design of field limiting ring+field plate is fewer than the number of the ring of the design needs of individual field limiting ring, together
When field plate can protect the terminal of chip not by outside contamination, therefore with better breakdown characteristics and device stability.
In addition, in the manufacturing process of power electronic devices, active region determines the important electrical characteristic of device, though terminal
It is so essential part, but only influences the breakdown voltage and stability of device, conduction voltage drop and shut-off to device
Time does not contribute, therefore terminal, on the basis of the pressure-bearing required by meeting device, the area of terminal is the smaller the better.
The problem of total junction device both the above Terminal Design, it can be attributed to：
The structure of field plate can protect device terminal to exempt from pollution, it is therefore desirable to increase the area of field plate as far as possible；And
The area needs of terminal are small as far as possible, to increase the area of active region.And the area for increasing field plate is referred in certain area
Under the premise of the terminal of size, increase the ratio of field plate covering terminal, because the ratio of field plate covering terminal is bigger, terminal exposes
For the ratio come with regard to smaller, it is exactly to be not easy to be contaminated not expose so.
Existing related patents have：Patent No. CN201010246809.4, applying date 2010-08-06, entitled " one
The patent of invention of the edge termination structure of kind high voltage power semiconductor device ", technology contents are：The invention discloses a kind of high
Press the edge termination structure of power semiconductor, power semiconductor is surround including several, with substrate with opposite
The field limiting ring of conduction type, each field limiting ring is unilateral or both sides are equipped with identical with field limiting ring conduction type, doping concentration is less than
The doped region of field limiting ring is covered with field plate on field limiting ring, with silicon dioxide layer interval between field limiting ring and field plate.The material of field plate
It may be selected from copper, aluminium, polysilicon or mix oxygen polysilicon etc..
For another example Patent No. CN201010246816.4, applying date 2010-08-06, a kind of entitled " high-voltage power half
The patent of invention of the edge termination structure of conductor device ", technology contents are：The invention discloses a kind of high voltage power semiconductors
The edge termination structure of device, power semiconductor is surround including several, with substrate have films of opposite conductivity field
Limit ring, around field limiting ring be equipped with it is identical with field limiting ring conduction type, doping concentration be less than field limiting ring doped region, the doping
Field limiting ring is wrapped up in region, and field plate is covered on field limiting ring, with silicon dioxide layer interval between field limiting ring and field plate.The material of field plate
It may be selected from copper, aluminium, polysilicon or mix oxygen polysilicon etc..
Wherein CN201010246809.4 and CN201010246816.4 is identical with the object that this patent is protected, and is all one
" terminal structure " of kind semiconductor devices in itself, but in the design of terminal structure and the function of terminal structure, the two is not
With, the two above-mentioned patents are all to design to reduce the electric field at field limiting ring and breakdown voltage by different field limiting ring
It can increase, be disjunct between their field plate and field limiting ring, field plate does not play the role of reducing electric field.
The content of the invention
In order to overcome the above problem existing for existing semiconductor chip terminal unit architecture, specifically now propose using gold
Belong to extension, the terminal unit architecture and manufacturing method of polycrystalline cut-off field plate, which possesses the field plate area coverage of bigger, can
Increase the stability of device；And the design of cut-off field plate is employed, can further reduce the area of terminal.
The concrete scheme of the present invention is as follows：
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate, it is characterised in that：It is served as a contrast including the first conduction type
Bottom, the first interarea of first conductivity type substrate is interior to be equipped with the second conduction type field limiting ring, the first conduction type lining
On the primary principal plane at bottom, equipped with the first insulating layer；On first insulating layer and positioned at the two of the second conduction type field limiting ring
Side is respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer, and the second insulating layer is equipped with Metal field plate；Institute
The bottom for stating Metal field plate is contacted with the second conduction type field limiting ring, and the Metal field plate covers the second conduction type field limiting ring
Region and its both sides；
Two blocks of field plates are located at first insulating layer the upper surface of and are covered in the both sides of the second conduction type field limiting ring, institute
Stating field plate includes polycrystalline cut-off field plate and metal extension field plate, and one end and the polycrystalline of the Metal field plate end field plate contact phase
Even.
One end that the Metal field plate is connected with polycrystalline cut-off field plate is along its lateral direction and bends downwards.
The other end of the Metal field plate is arranged in parallel with metal extension field plate.
The polycrystalline cut-off field plate is polysilicon.
Metal extension field plate is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
Further, the second insulating layer is located at field plate the upper surface of, covers entire field plate.
Further, the Metal field plate is located at second insulating layer the upper surface of, covers entire second conduction type field Xun Huan
Region, the Metal field plate is connected with the second conduction type field limiting ring.
Further, the Metal field plate covers entire or part field plate region, is equipped in the region of covering field plate
Electrode contact hole；One end of the Metal field plate field plate contact phase is ended by the electrode contact hole in second insulating layer and polycrystalline
Even.
Further, at the second interarea of first conductivity type substrate, it is disposed with the first conduction type field and cuts
Only layer, the second conduction type collector and back metal；The first conduction type field cutoff layer and the second conduction type current collection
Pole is located within the second interarea lower surface, and back metal is located at outside the second interarea lower surface.
Further, the first conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate is silicon
Substrate, the first interarea of the first conductivity type substrate is its front, and the second interarea of the first conductivity type substrate is its back side.
Further, the diffusion depth of the second conduction type field limiting ring is 1um-10um；First insulating layer is
Silicon dioxide layer, thickness are 0.5um ~ 5um；Polycrystalline cut-off field plate width in the field plate is 0 um ~ 30um；In field plate
Metal extension field plate width is 0 um ~ 50um.
Extended using metal, the manufacturing method of the terminal unit architecture of polycrystalline cut-off field plate, specific manufacturing process is：
A. on the first interarea of the first conductivity type substrate, with the method growth regulation one of thermal oxide, LPCVD or PECVD
Insulating layer；
B. the first insulating layer is performed etching by photoetching, dry etching, forms injection window region；
C. the second conductive type impurity is injected in window region, annealed, push away trap processing, form the second conduction type
Field limiting ring；
D. the method that LPCVD or PECVD is used above gate insulator, deposit polycrystalline silicon layer；
E. polysilicon layer is doped using POCl3；
F. polycrystalline silicon gate layer is performed etching by photoetching, dry etching, formed window region and polycrystalline cut-off field plate and
Metal extends field plate；
G. second insulating layer is deposited by LPCVD or PECVD, by dry etching, forms contact hole；
I. by evaporating or sputtering making metal on the first interarea and the second interarea of the first conductivity type substrate
Layer, and pass through photoetching, wet etching formation Metal field plate.
Further, the second conduction type field limiting ring doping concentration is dense higher than the doping of the first conductivity type substrate
Degree；The second insulating layer is TEOS silica, phosphorosilicate glass PSG, the boron-phosphorosilicate glass deposited by LPCVD or PECVD
BPSG or silicon nitride SiNx and their any combination.
The advantage of the invention is that：
1st, the terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it is manufactured
Simple for process, the application focuses on that the structure of field plate is improved, and the field plate and the second conduction type field limiting ring of the application design are phases
Even, polycrystalline cut-off field plate can compress electric field, and metal extension field plate can extend electric field, so that electric field is distributed from new, together
Sample realizes the effect for reducing field limiting ring electric field.The present invention serves as cutoff field version using polycrystalline, and extension field version is served as using metal,
The effect of so electric field cut-off is best, while avoids the first insulating layer breakdown caused by electric field extension, to the first insulating layer
Thickness rely on it is smaller.
2nd, the application introduce polycrystalline cut-off field plate, while set polycrystalline cut-off field plate and metal extension field plate compared with
For the design of traditional field limiting ring+field plate, under limited area, the area of device field plate covering is increased, and can
Ensure the width of terminal in the range of very little.
3rd, the field plate of the application due to covering terminal ratio it is big, can play and protect the not contaminated effect of terminal.
4th, compared to traditional field limiting ring+field plate termination structure, the application adds polycrystalline cut-off field plate, is keeping overall
On the basis of area is constant so that the area coverage bigger of field plate reduces the pollution of outer bound pair terminal so that the stabilization of device
Property gets a promotion.
5th, for the application compared to traditional field limiting ring+field plate termination structure, present invention adds polycrystalline to end field plate so that
The area of entire terminal is reduced, thus the opposite active area for expanding device so that the electrology characteristic of device into
One step is improved.
Description of the drawings
Fig. 1 is the application overall structure diagram.
Fig. 2 corresponds to technique A.
Fig. 3 corresponds to technique B, C.
Fig. 4 corresponds to technique D, E.
Fig. 5 corresponds to technique F.
Fig. 6,7 correspond to technique G.
Fig. 8,9 correspond to technique I.
110 in attached drawing：First conductivity type substrate；120：Second conduction type field limiting ring；130：First insulating layer；141：
Polycrystalline ends field plate；142：Metal extends field plate；150：Second insulating layer；160：Metal field plate.
Specific embodiment
Embodiment 1
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120；Two blocks of field plates are located at the first insulating layer 130
Above and the both sides of the second conduction type field limiting ring 120 are covered in, the field plate includes polycrystalline cut-off field plate 141 and metal prolongs
Field plate 142 is stretched, one end of the Metal field plate 160 is contacted with polycrystalline cut-off field plate 141 to be connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
Embodiment 2
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
Embodiment 3
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
The diffusion depth of second conduction type field limiting ring 120 is 1um-10um；First insulating layer 130 is silica
Layer, thickness are 0.5um ~ 5um；Polycrystalline 141 width of cut-off field plate in the field plate is 0 um ~ 30um；Metal in field plate prolongs
142 width of field plate is stretched for 0 um ~ 50um.
Embodiment 4
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
The diffusion depth of second conduction type field limiting ring 120 is 10um；First insulating layer 130 is silicon dioxide layer,
Thickness is 0.5um；Polycrystalline 141 width of cut-off field plate in the field plate is 30um；Metal extension 142 width of field plate in field plate
For 50um.
Embodiment 5
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
The diffusion depth of second conduction type field limiting ring 120 is 1um；First insulating layer 130 is silicon dioxide layer, thick
It spends for 5um；Polycrystalline 141 width of cut-off field plate in the field plate is 10um；Metal in field plate extends 142 width of field plate
20um。
Embodiment 6
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
The diffusion depth of second conduction type field limiting ring 120 is 4um；First insulating layer 130 is silicon dioxide layer, thick
It spends for 3.1um；Polycrystalline 141 width of cut-off field plate in the field plate is 20um；Metal in field plate extends 142 width of field plate
35um。
Embodiment 7
Extended using metal, the manufacturing method of the terminal unit architecture of polycrystalline cut-off field plate, specific manufacturing process is：
A. on the first interarea of the first conductivity type substrate 110, with the method growth regulation of thermal oxide, LPCVD or PECVD
One insulating layer 130；
B. the first insulating layer 130 is performed etching by photoetching, dry etching, forms injection window region；
C. the second conductive type impurity is injected in window region, annealed, push away trap processing, form the second conduction type
Field limiting ring 120；
D. the method that LPCVD or PECVD is used above gate insulator, deposit polycrystalline silicon layer；
E. polysilicon layer is doped using POCl3；
F. polycrystalline silicon gate layer is performed etching by photoetching, dry etching, forms window region and polycrystalline cut-off field plate
141 and metal extension field plate 142；
G. second insulating layer 150 is deposited by LPCVD or PECVD, by dry etching, forms contact hole；
I. on the first interarea and the second interarea of the first conductivity type substrate 110 gold is made by evaporating or sputtering
Belong to layer, and pass through photoetching, wet etching formation Metal field plate 160.
Second conduction type field limiting ring, 120 doping concentration is higher than the doping concentration of the first conductivity type substrate 110；Institute
It is TEOS silica, phosphorosilicate glass PSG, the boron-phosphorosilicate glass deposited by LPCVD or PECVD to state second insulating layer 150
BPSG or silicon nitride SiNx and their any combination.
Embodiment 8
Extended using metal, the terminal unit architecture of polycrystalline cut-off field plate includes the first conductivity type substrate 110, described the
The second conduction type field limiting ring 120, first conductivity type substrate are equipped in first interarea of one conductivity type substrate 110
On 110 primary principal plane, equipped with the first insulating layer 130；On first insulating layer 130 and positioned at the second conduction type field
The both sides of limit ring 120 are respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer 150, the second insulating layer 150
It is equipped with Metal field plate 160；The bottom of the Metal field plate 160 is contacted with the second conduction type field limiting ring 120, the metal field
Plate 160 covers the region and its both sides of the second conduction type field limiting ring 120.
Two blocks of field plates are located at first insulating layer 130 the upper surface of and are covered in the two of the second conduction type field limiting ring 120
Side, the field plate include polycrystalline cut-off field plate 141 and metal extension field plate 142, and one end and the polycrystalline of the Metal field plate 160 are cut
The only contact of field plate 141 is connected.
Here device refers to power semiconductor, and active region refers to the active region on semiconductor devices, semiconductor
Device outermost is edge, is inward terminal, then is active region inside.
One end that the Metal field plate 160 is connected with polycrystalline cut-off field plate 141 is along lateral direction and bends downwards.
The other end of the Metal field plate 160 is arranged in parallel with metal extension field plate 142.
The polycrystalline cut-off field plate 141 is polysilicon.
Metal extension field plate 142 is Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
The second insulating layer 150 is located at field plate the upper surface of, covers entire field plate.
The Metal field plate 160 is located at second insulating layer 150 the upper surface of, covers the area of entire second conduction type field Xun Huan
Domain, the Metal field plate 160 are connected with the second conduction type field limiting ring 120.
The Metal field plate 160 covers entire or part field plate region, is connect in the region of covering field plate equipped with electrode
Contact hole；Field plate 141 is ended with polycrystalline by the electrode contact hole in second insulating layer 150 and is connect in one end of the Metal field plate 160
It touches and is connected.
At second interarea of first conductivity type substrate 110, the first conduction type field cutoff layer, are disposed with
Two conduction type collectors and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at the
Within two interarea lower surfaces, and back metal is located at outside the second interarea lower surface.
First conduction type is N-type, and the second conduction type is p-type, and first conductivity type substrate 110 is silicon substrate,
First interarea of the first conductivity type substrate 110 is its front, and the second interarea of the first conductivity type substrate 110 is its back side.
The terminal unit architecture of the application is novel in design, does not occur similar structures in the prior art, and it manufactures work
Skill is simple, and the application focuses on that the structure of field plate is improved, and the field plate of the application design is with the second conduction type field limiting ring 120
Connected, polycrystalline cut-off field plate 141 can compress electric field, and metal extension field plate 142 can extend electric field, so that electric field is from new
Distribution equally realizes the effect for reducing field limiting ring electric field.
The diffusion depth of second conduction type field limiting ring 120 is 1um-10um；First insulating layer 130 is silica
Layer, thickness are 0.5um ~ 5um；Polycrystalline 141 width of cut-off field plate in the field plate is 0 um ~ 30um；Metal in field plate prolongs
142 width of field plate is stretched for 0 um ~ 50um.
Extended using metal, the manufacturing method of the terminal unit architecture of polycrystalline cut-off field plate, specific manufacturing process is：
A. on the first interarea of the first conductivity type substrate 110, with the method growth regulation of thermal oxide, LPCVD or PECVD
One insulating layer 130；
B. the first insulating layer 130 is performed etching by photoetching, dry etching, forms injection window region；
C. the second conductive type impurity is injected in window region, annealed, push away trap processing, form the second conduction type
Field limiting ring 120；
D. the method that LPCVD or PECVD is used above gate insulator, deposit polycrystalline silicon layer；
E. polysilicon layer is doped using POCl3；
F. polycrystalline silicon gate layer is performed etching by photoetching, dry etching, forms window region and polycrystalline cut-off field plate
141 and metal extension field plate 142；
G. second insulating layer 150 is deposited by LPCVD or PECVD, by dry etching, forms contact hole；
I. on the first interarea and the second interarea of the first conductivity type substrate 110 gold is made by evaporating or sputtering
Belong to layer, and pass through photoetching, wet etching formation Metal field plate 160.
Further, 120 doping concentration of the second conduction type field limiting ring mixing higher than the first conductivity type substrate 110
Miscellaneous concentration；The second insulating layer 150 is TEOS silica, phosphorosilicate glass PSG, the boron phosphorus deposited by LPCVD or PECVD
Silica glass BPSG or silicon nitride SiNx and their any combination.
Claims (5)
1. using metal extension, the terminal unit architecture of polycrystalline cut-off field plate, it is characterised in that：Including the first conductivity type substrate
（110）, first conductivity type substrate（110）The first interarea in be equipped with the second conduction type field limiting ring（120）, described
One conductivity type substrate（110）The first interarea on, equipped with the first insulating layer（130）；First insulating layer（130）It is upper and
Positioned at the second conduction type field limiting ring（120）Both sides be respectively provided with one block of field plate；Two blocks of field plates are equipped with second insulating layer
（150）, the second insulating layer（150）It is equipped with Metal field plate（160）；The Metal field plate（160）Bottom led with second
Electric type field limiting ring（120）Contact, the Metal field plate（160）Cover the second conduction type field limiting ring（120）Region and its
Both sides；
First insulating layer（130）Top is located at the first insulating layer for unilateral perforate, two blocks of field plates（130）The upper surface of and cover
It covers in the second conduction type field limiting ring（120）Both sides, two blocks of field plates include polycrystalline and end field plate（141）Extend field plate with metal
（142）, the Metal field plate（160）One end and polycrystalline end field plate（141）Contact is connected；
The Metal field plate（160）End field plate with polycrystalline（141）Connected one end is along lateral direction and bends downwards；
The second insulating layer（150）End field plate positioned at polycrystalline（141）Extend field plate with metal（142）The upper surface of, covering is whole
A polycrystalline ends field plate（141）Extend field plate with metal（142）；
The Metal field plate（160）Positioned at second insulating layer（150）The upper surface of, cover entire second conduction type field limiting ring
（120）Region；
First conductivity type substrate（110）The second interarea at, be disposed with the first conduction type field cutoff layer, second
Conduction type collector and back metal；The first conduction type field cutoff layer and the second conduction type collector are located at second
Within interarea lower surface, and back metal is located at outside the second interarea lower surface；First conduction type be N-type, the second conductive-type
Type is p-type, first conductivity type substrate（110）For silicon substrate, the first conductivity type substrate（110）The first interarea be its
Front, the first conductivity type substrate（110）The second interarea be its back side；
The Metal field plate（160）The other end and metal extend field plate（142）It is arranged in parallel, and the Metal field plate（160）
Other end length be more than metal extend field plate（142）.
2. it is according to claim 1 extended using metal, polycrystalline cut-off field plate terminal unit architecture, it is characterised in that：
Metal extends field plate（142）For Al, Al/Si, Al/Si/Cu, Ag, Au or Cu.
3. it is according to claim 1 extended using metal, polycrystalline cut-off field plate terminal unit architecture, it is characterised in that：
The Metal field plate（160）Entire or part field plate region is covered, electrode contact hole, institute are equipped in the region of covering field plate
State Metal field plate（160）One end pass through second insulating layer（150）On electrode contact hole and polycrystalline end field plate（141）Contact
It is connected.
4. it is according to claim 1 extended using metal, polycrystalline cut-off field plate terminal unit architecture, it is characterised in that：
The second conduction type field limiting ring（120）Diffusion depth be 1um-10um；First insulating layer（130）For silica
Layer, thickness are 0.5um ~ 5um；Polycrystalline cut-off field plate in the field plate（141）Width is 0 um ~ 30um；Metal in field plate
Extend field plate（142）Width is 0 um ~ 50um.
5. it is according to claim 1 extended using metal, polycrystalline cut-off field plate terminal unit architecture manufacturing method,
It is characterized in that：Extended using metal, the manufacturing method of the terminal unit architecture of polycrystalline cut-off field plate, specific manufacturing process is：
A. in the first conductivity type substrate（110）The first interarea on, with the method growth regulation one of thermal oxide, LPCVD or PECVD
Insulating layer（130）；
B. by photoetching, dry etching to the first insulating layer（130）It performs etching, forms injection window region；
C. the second conductive type impurity is injected in window region, annealed, push away trap processing, form the second conduction type field limit
Ring（120）；
D. the method that LPCVD or PECVD is used above gate insulator, deposit polycrystalline polysilicon gate layer；
E. polycrystalline silicon gate layer is doped using POCl3；
F. polycrystalline silicon gate layer is performed etching by photoetching, dry etching, forms window region and polycrystalline cut-off field plate（141）
Extend field plate with metal（142）；
G. second insulating layer is deposited by LPCVD or PECVD（150）, by dry etching, form contact hole；
I. in the first conductivity type substrate（110）The first interarea and the second interarea on by evaporating or sputtering making metal
Layer, and pass through photoetching, wet etching forms Metal field plate on the first interarea（160）；
The second conduction type field limiting ring（120）Doping concentration is higher than the first conductivity type substrate（110）Doping concentration；Institute
State second insulating layer（150）To pass through the TEOS of LPCVD or PECVD deposits, silica, phosphorosilicate glass, boron-phosphorosilicate glass, nitrogen
SiClx or their any combination.
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|---|---|---|---|---|
| US5075739A (en) * | 1990-01-02 | 1991-12-24 | Motorola, Inc. | High voltage planar edge termination using a punch-through retarding implant and floating field plates |
| CN101221980A (en) * | 2007-01-11 | 2008-07-16 | 富士电机电子设备技术株式会社 | Power semiconductor device |
| CN103534809A (en) * | 2011-08-05 | 2014-01-22 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN103875074A (en) * | 2011-07-14 | 2014-06-18 | Abb技术有限公司 | Insulated gate transistor and method of production thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009117715A (en) * | 2007-11-08 | 2009-05-28 | Toshiba Corp | Semiconductor device and its manufacturing method |
| CN102779840B (en) * | 2012-07-18 | 2014-10-15 | 电子科技大学 | Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer |
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2014
- 2014-11-05 CN CN201410614947.1A patent/CN104332491B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075739A (en) * | 1990-01-02 | 1991-12-24 | Motorola, Inc. | High voltage planar edge termination using a punch-through retarding implant and floating field plates |
| CN101221980A (en) * | 2007-01-11 | 2008-07-16 | 富士电机电子设备技术株式会社 | Power semiconductor device |
| CN103875074A (en) * | 2011-07-14 | 2014-06-18 | Abb技术有限公司 | Insulated gate transistor and method of production thereof |
| CN103534809A (en) * | 2011-08-05 | 2014-01-22 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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