CN109888007A - SOI LIGBT device with diode clamp carrier accumulation layer - Google Patents
SOI LIGBT device with diode clamp carrier accumulation layer Download PDFInfo
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Abstract
The invention discloses a kind of SOI LIGBT devices with diode clamp carrier accumulation layer, by the way that P-type semiconductor base area is divided into multiple regions, and two or three series diodes are introduced in different zones, so that device is in reverse withstand voltage, after p-type electric field shielding area current potential is increased to the conduction voltage drop of two or three diodes, diode current flow, the current potential in p-type electric field shielding area is clamped near two or three diode conduction voltage drops, so the current potential of N-type carrier memory block is shielded well by p-type electric field shielding area in very low value, the back biased diode being mainly made of the resistance to pressure area in p-type electric field shielding area and surface is born in the pressure resistance of device, to thoroughly break the contradictory relation between breakdown voltage and N-type carrier layer concentration.
Description
Technical field
The invention belongs to power semiconductor device technology fields, and in particular to one kind has the storage of diode clamp carrier
The design of the SOI LIGBT device of layer.
Background technique
The miniaturization of power electronic system, it is integrated be power semiconductor an important research direction.Intelligent function
Rate integrated circuit (Smart Power Integrated Circuit, SPIC) or high voltage integrated circuit (High Voltage
Integrated Circuit, HVIC) low-voltage circuits such as protection, control, detection, driving and high voltage power device are integrated in together
On one chip, system bulk is not only reduced in this way, also improves system reliability.Meanwhile in the yard of upper frequency
It closes, due to the reduction of system lead-in inductance, for buffering and protecting circuit, its requirement can be significantly reduced.
Lateral insulated gate bipolar transistor (Lateral Insulated-Gate Bipolar Transistor, LIGBT)
One of the important power device of SPIC or HVIC, the LIGBT based on SOI technology be even more due to its excellent isolation characteristic and by
It is widely used.As bipolar power component, LIGBT has MOSFET high input impedance and the big spy of BJT current density simultaneously
Point.Also increase while however, the presence of a large amount of nonequilibrium carrier enhances drift region conductivity modulation effect in drift region
The turn-off power loss of device.So turn-off power loss (the Turn-off loss:E of optimised devicesoff) and conduction voltage drop (On-
State voltage drop:Von) between tradeoff, be the key that design one of LIGBT.
In order to obtain the more preferably tradeoff between turn-off power loss and conduction voltage drop, H.Takahashi et al. is 1996
Year is in article " Carrier Stored Trench-Gate Bipolar transistor (CSTBT)-A Novel Power
Device for High Voltage Application " in be put forward for the first time carrier accumulation layer technology, and applied
Into longitudinal IGBT structure.As shown in Figure 1 it is a kind of LIGBT structure with carrier accumulation layer, introduces N-type in cathode side
Carrier accumulation layer further enhances drift region so that accumulating more nonequilibrium carriers close to cathode side in drift region
Conductivity modulation effect.Simultaneously as cathode electronics injection efficiency improves, the injection efficiency of anode can be reduced, so that LIGBT is closed
When disconnected, anode, which will continue injected holes, to be reduced, and turn-off speed will improve.So the introducing of carrier accumulation layer, so that
LIGBT device is provided with more preferably EoffAnd VonTradeoff.
However, the prior art has in carrier accumulation layer LIGBT device, with carrier accumulation layer concentration
(Carrier-Stored Layer Concentration:Ncs) raising, the breakdown voltage (Breakdown of device
Voltage:BV) can reduce therewith.So the contradictory relation between breakdown voltage and carrier accumulation layer concentration how is solved,
It is the key that design has one of carrier accumulation layer LIGBT.
Summary of the invention
The purpose of the present invention is to solve existing breakdown voltages and current-carrying with carrier accumulation layer LIGBT device
Contradictory relation between sub- accumulation layer concentration proposes a kind of SOI LIGBT device with diode clamp carrier accumulation layer
Part can break the contradictory relation of breakdown voltage and carrier layer concentration and rapidly switch off, and improve short circuit peace
Existing carrier accumulation layer technology can also be compatible with while full workspace.
The technical solution of the present invention is as follows: the SOI LIGBT device with diode clamp carrier accumulation layer, including partly lead
Body substrate, the buried oxide layer area in semiconductor substrate and the semiconductor layer in buried oxide layer area.Semiconductor layer includes p-type
Semiconductor base area, gate regions, N-type carrier memory block, the resistance to pressure area in surface, p-type electric field shielding area, N-type semiconductor buffer area with
And p-type collecting zone, P-type semiconductor base area and gate region, in semiconductor layer side, N-type semiconductor buffer area is located at semiconductor layer
The other side, by P-type semiconductor base area, p-type electric field shielding area is located at by gate regions N-type carrier bank bit, surface pressure resistance
Area is located between N-type carrier memory block, p-type electric field shielding area and N-type semiconductor buffer area, and p-type collecting zone is set to N-type half
Conductor buffer area top side.
Further, gate regions include planar gate polar region and three-dimensional slot grid region, and planar gate polar region is by gate dielectric layer, grid gold
Belong to and polysilicon gate district's groups are at, three-dimensional slot grid region and P-type semiconductor base contact, three-dimensional slot grid region is by going deep into the depth of semiconductor layer
Slot constitute, deep trouth include gate dielectric layer, in deep trouth by gate dielectric layer surround polysilicon grid region and cover part it is more
The gate metal in crystal silicon grid region.
Further, P-type semiconductor base area is divided into four different sub-districts by three-dimensional slot grid region, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region as the channel base LIGBT, and in the first sub-district
With a heavily doped P-type semiconductor region, source area of the heavily doped N-type semiconductor region as the channel base LIGBT, heavily doped P-type
Ohmic contact regions of the semiconductor region as the channel base LIGBT, part heavily doped N-type semiconductor region and part heavily doped P-type half
Emitter metal is covered on conductor region；First sub-region surface is additionally provided with planar gate polar region, the gate dielectric layer of planar gate polar region
Cover part heavily doped N-type semiconductor region, P-type semiconductor base area and part N-type carrier memory block, gate dielectric layer upper surface
It is successively covered with polysilicon grid region and gate metal from bottom to up.
It is respectively arranged with a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region in second sub-district, second
Cathode ohmic contact area of the heavily doped N-type semiconductor region of sub-district as first diode, the heavily doped P-type of the second sub-district are partly led
Anode ohmic contact zone of the body area as first diode, the cathode ohmic contact area of first diode and emitter metal connect
It connects.
A heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region, third are respectively arranged in third sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region of sub-district as the second diode, the heavily doped P-type of third sub-district are partly led
The cathode ohmic contact area of anode ohmic contact zone of the body area as the second diode, the second diode passes through the first floating metal
It is connect with the anode ohmic contact zone of first diode.
4th sub-district is connect by the second floating metal with the anode ohmic contact zone of the second diode, the 4th sub-district and P
Type electric field shielding area is connected, and a side section near surface pressure resistance area is leaned in three-dimensional slot grid region with p-type electric field shielding area by the 4th sub-district
It surrounds, the 4th sub-district and p-type electric field shielding area collectively form an electric field shielding area.
Further, the ohmic contact regions of base area, the source area of base area, gate regions, P-type semiconductor base area, N-type carrier
Memory block, emitter metal are collectively formed the nMOS structure of LIGBT, nMOS structure and p-type electric field shielding area, first diode with
And second diode constitute the first active area.
Further, P-type semiconductor base area is divided into five different sub-districts by three-dimensional slot grid region, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region as the channel base LIGBT, and in the first sub-district
With a heavily doped P-type semiconductor region, source area of the heavily doped N-type semiconductor region as the channel base LIGBT, heavily doped P-type
Ohmic contact regions of the semiconductor region as the channel base LIGBT, part heavily doped N-type semiconductor region and part heavily doped P-type half
Emitter metal is covered on conductor region；First sub-region surface is additionally provided with planar gate polar region, the gate dielectric layer of planar gate polar region
Cover part heavily doped N-type semiconductor region, P-type semiconductor base area and part N-type carrier memory block, gate dielectric layer upper surface
It is successively covered with polysilicon grid region and gate metal from bottom to up.
It is respectively arranged with a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region in second sub-district, second
Cathode ohmic contact area of the heavily doped N-type semiconductor region of sub-district as first diode, the heavily doped P-type of the second sub-district are partly led
Anode ohmic contact zone of the body area as first diode, the cathode ohmic contact area of first diode and emitter metal connect
It connects.
A heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region, third are respectively arranged in third sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region of sub-district as the second diode, the heavily doped P-type of third sub-district are partly led
The cathode ohmic contact area of anode ohmic contact zone of the body area as the second diode, the second diode passes through the first floating metal
It is connect with the anode ohmic contact zone of first diode.
It is respectively arranged with a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region in 4th sub-district, the 4th
Cathode ohmic contact area of the heavily doped N-type semiconductor region of sub-district as third diode, the heavily doped P-type of the 4th sub-district are partly led
The cathode ohmic contact area of anode ohmic contact zone of the body area as third diode, third diode passes through third floating metal
It is connect with the anode ohmic contact zone of the second diode.
5th sub-district is connect by the second floating metal with the anode ohmic contact zone of third diode, the 5th sub-district and P
Type electric field shielding area is connected, and a side section near surface pressure resistance area is leaned in three-dimensional slot grid region with p-type electric field shielding area by the 5th sub-district
It surrounds, the 5th sub-district and p-type electric field shielding area collectively form an electric field shielding area.
Further, the ohmic contact regions of base area, the source area of base area, gate regions, P-type semiconductor base area, N-type carrier
Memory block, emitter metal are collectively formed the nMOS structure of LIGBT, nMOS structure and p-type electric field shielding area, first diode,
Second diode and third diode constitute the first active area.
Further, p-type collecting zone upper surface is covered with collector electrode metal, N-type semiconductor buffer area, p-type collecting zone and
The second active area is collectively formed in collector electrode metal.
Further, the resistance to pressure area in surface is formed by n type semiconductor layer, one side and three-dimensional slot grid region and N-type carrier
Memory block contact, the other side is contacted with N-type semiconductor buffer area.
Further, the resistance to pressure area in surface is with the n type semiconductor layer that linear gradient adulterates by forming, and doping is from close to the
One active area is gradually increased to the second active area.
The beneficial effects of the present invention are: the invention proposes one kind to have low conduction voltage drop, low turn-off power loss and excellent anti-
The novel SOI LIGBT device of short-circuit capacity.In the present invention, by the way that P-type semiconductor base area is divided into multiple regions, and
Different zones introduce two or three series diodes, so that device, in reverse withstand voltage, p-type electric field shielding area current potential is increased to
After the conduction voltage drop of two or three diodes, the current potential of diode current flow, p-type electric field shielding area is clamped at two or three
Near diode conduction voltage drop, so the current potential of N-type carrier memory block is shielded well by p-type electric field shielding area very low
The back biased diode being mainly made of the resistance to pressure area in p-type electric field shielding area and surface is born in the pressure resistance of value, device, to thoroughly beat
The contradictory relation between breakdown voltage and N-type carrier layer concentration is broken.Several numbers can be improved in the doping of N-type carrier memory block
Magnitude at current-carrying subpool and the back biased diode of P-type semiconductor base area composition without puncturing.In the present invention
The emitter injection efficiency of LIGBT can significantly improve, to reduce the conduction voltage drop of LIGBT.It is imitated again since emitter injects
The raising of rate, LIGBT collector injection efficiency can be suitably lowered, to improve turn-off speed.Meanwhile the present invention is arranged
The first active area of multiple series diode energy clampers LIGBT nMOS drain voltage, i.e., N-type carrier memory block electricity
Pressure, so that device has lower saturation current density, to improve short-circuit safety operation area.To sum up, this hair
It is bright to be compatible on the basis of prior art, LIGBT conduction voltage drop is reduced, turn-off speed is improved, improves short-circuit safety operation area.
Detailed description of the invention
Fig. 1 show the SOI LIGBT structural schematic diagram that tradition in the prior art has carrier accumulation layer.
Fig. 2 show the tool that the embodiment of the present invention one provides, and there are two the SOI LIGBT structural schematic diagrams of diode clamp.
Fig. 3 show the tool that the embodiment of the present invention one provides, and there are two the SOI LIGBT structure top views of diode clamp.
Fig. 4 show SOI LIGBT structural schematic diagram of the tool provided by Embodiment 2 of the present invention there are three diode clamp.
Fig. 5 show SOI LIGBT structure top view of the tool provided by Embodiment 2 of the present invention there are three diode clamp.
Fig. 6 show it is provided in an embodiment of the present invention to tradition have carrier accumulation layer SOI LIGBT and tool there are two
The V that the SOI LIGBT of diode clamp is emulatedon-EoffTradeoff comparison diagram.
Description of symbols:
1- semiconductor substrate, 2- buried oxide layer area, 3-P type semiconductor base area, 4- heavily doped N-type semiconductor region, 5- heavy doping P
Type semiconductor region, 6-N type current-carrying subpool, the resistance to pressure area in the surface 7-, 8- gate dielectric layer, 9- gate metal, 10- emitter gold
Belong to, 11- the first floating metal, 12- the second floating metal, 13-P type electric field shielding area, 14- polysilicon grid region, 15-N type is partly led
Volume buffer, 16-P type collecting zone, 17- collector electrode metal, 18- third floating metal.
Specific embodiment
Carry out detailed description of the present invention illustrative embodiments with reference to the drawings.It should be appreciated that shown in attached drawing and
The embodiment of description is only exemplary, it is intended that is illustrated the principle and spirit of the invention, and is not limited model of the invention
It encloses.
Embodiment one:
The embodiment of the invention provides a kind of tool, there are two the SOI LIGBT devices of diode clamp, as Fig. 2~Fig. 3 is total
With shown in, including semiconductor substrate 1, the buried oxide layer area 2 in semiconductor substrate 1 and partly leading in buried oxide layer area 2
Body layer (soi layer).Semiconductor layer includes P-type semiconductor base area 3, gate regions, N-type carrier memory block 6, the resistance to pressure area 7 in surface, P
Type electric field shielding area 13, N-type semiconductor buffer area 15 and p-type collecting zone 16, P-type semiconductor base area 3 and gate region are in half
Conductor layer side, N-type semiconductor buffer area 15 are located at the semiconductor layer other side, and N-type carrier memory block 6 is located at P-type semiconductor
By base area 3, p-type electric field shielding area 13 is located at by gate regions, and the resistance to pressure area 7 in surface is located at N-type carrier memory block 6, p-type electric field screen
It covers between area 13 and N-type semiconductor buffer area 15, p-type collecting zone 16 is set to 15 top side of N-type semiconductor buffer area.This hair
In bright embodiment, P-type semiconductor base area 3 can be contacted with buried oxide layer area 2, can not also be contacted；P-type electric field shielding area 13 can be with
It contacts, can not also contact with buried oxide layer area 2.
Gate regions include planar gate polar region and three-dimensional slot grid region, and planar gate polar region is by gate dielectric layer 8, gate metal 9 and more
Crystal silicon grid region 14 forms, and three-dimensional slot grid region contacts with P-type semiconductor base area 3, and three-dimensional slot grid region is by going deep into the deep trouth of semiconductor layer
It constitutes, deep trouth includes gate dielectric layer 8, in deep trouth by polysilicon grid region 14 that gate dielectric layer 8 surrounds and covers part
The gate metal 9 in polysilicon grid region 14.
In the embodiment of the present invention, P-type semiconductor base area 3 is divided into four different sub-districts by three-dimensional slot grid region, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region as the channel base LIGBT, and in the first sub-district
4 and a heavily doped P-type semiconductor region 5, source area of the heavily doped N-type semiconductor region 4 as the channel base LIGBT, heavy doping P
Ohmic contact regions of the type semiconductor region 5 as the channel base LIGBT, part heavily doped N-type semiconductor region 4 and part heavy doping P
Emitter metal 10 is covered on type semiconductor region 5.First sub-region surface is additionally provided with planar gate polar region, the grid of planar gate polar region
Dielectric layer 8 covers part heavily doped N-type semiconductor region 4, P-type semiconductor base area 3 and part N-type carrier memory block 6, and grid are situated between
8 upper surface of matter layer is successively covered with polysilicon grid region 14 and gate metal 9 from bottom to up.
A heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in second sub-district, the
Cathode ohmic contact area of the heavily doped N-type semiconductor region 4 of two sub-districts as first diode, the heavily doped P-type of the second sub-district
Anode ohmic contact zone of the semiconductor region 5 as first diode, the cathode ohmic contact area of first diode and emitter gold
Belong to 10 connections.
A heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in third sub-district, the
Cathode ohmic contact area of the heavily doped N-type semiconductor region 4 of three sub-districts as the second diode, the heavily doped P-type of third sub-district
The cathode ohmic contact area of anode ohmic contact zone of the semiconductor region 5 as the second diode, the second diode is floating by first
Empty metal 11 is connect with the anode ohmic contact zone of first diode, i.e., the second diode is connected with first diode.
4th sub-district is connect by the second floating metal 12 with the anode ohmic contact zone of the second diode, the 4th sub-district and
P-type electric field shielding area 13 is connected, and three-dimensional slot grid region is leaned on the one of near surface pressure resistance area 7 with p-type electric field shielding area 13 by the 4th sub-district
Side section is surrounded, and the 4th sub-district and p-type electric field shielding area 13 collectively form an electric field shielding area.
The ohmic contact regions of base area, the source area of base area, gate regions, P-type semiconductor base area 3, N-type carrier memory block 6,
Emitter metal 10 is collectively formed the nMOS structure of LIGBT, nMOS structure and p-type electric field shielding area 13, first diode and
Second diode constitutes the first active area.
16 upper surface of p-type collecting zone is covered with collector electrode metal 17, N-type semiconductor buffer area 15,16 sum aggregate of p-type collecting zone
The second active area is collectively formed in electrode metal 17.
The resistance to pressure area 7 in surface is formed by n type semiconductor layer, and one side connects with three-dimensional slot grid region and N-type carrier memory block 6
Touching, the other side is contacted with N-type semiconductor buffer area 15.In the embodiment of the present invention, the resistance to pressure area 7 in surface with linear gradient by mixing
Miscellaneous n type semiconductor layer is formed, and doping is gradually increased from close to the first active area to the second active area.
Embodiment two:
The embodiment of the invention provides a kind of tool, there are three the SOI LIGBT devices of diode clamp, as Fig. 4~Fig. 5 is total
With shown in, including semiconductor substrate 1, the buried oxide layer area 2 in semiconductor substrate 1 and partly leading in buried oxide layer area 2
Body layer (soi layer).Semiconductor layer includes P-type semiconductor base area 3, gate regions, N-type carrier memory block 6, the resistance to pressure area 7 in surface, P
Type electric field shielding area 13, N-type semiconductor buffer area 15 and p-type collecting zone 16, P-type semiconductor base area 3 and gate region are in half
Conductor layer side, N-type semiconductor buffer area 15 are located at the semiconductor layer other side, and N-type carrier memory block 6 is located at P-type semiconductor
By base area 3, p-type electric field shielding area 13 is located at by gate regions, and the resistance to pressure area 7 in surface is located at N-type carrier memory block 6, p-type electric field screen
It covers between area 13 and N-type semiconductor buffer area 15.P-type collecting zone 16 is set to 15 top side of N-type semiconductor buffer area.This hair
In bright embodiment, P-type semiconductor base area 3 can be contacted with buried oxide layer area 2, can not also be contacted；P-type electric field shielding area 13 can be with
It contacts, can not also contact with buried oxide layer area 2.
Gate regions include planar gate polar region and three-dimensional slot grid region, and planar gate polar region is by gate dielectric layer 8, gate metal 9 and more
Crystal silicon grid region 14 forms, and three-dimensional slot grid region contacts with P-type semiconductor base area 3, and three-dimensional slot grid region is by going deep into the deep trouth of semiconductor layer
It constitutes, deep trouth includes gate dielectric layer 8, in deep trouth by polysilicon grid region 14 that gate dielectric layer 8 surrounds and covers part
The gate metal 9 in polysilicon grid region 14.
In the embodiment of the present invention, P-type semiconductor base area 3 is divided into five different sub-districts by three-dimensional slot grid region, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region as the channel base LIGBT, and in the first sub-district
4 and a heavily doped P-type semiconductor region 5, source area of the heavily doped N-type semiconductor region 4 as the channel base LIGBT, heavy doping P
Ohmic contact regions of the type semiconductor region 5 as the channel base LIGBT, part heavily doped N-type semiconductor region 4 and part heavy doping P
Emitter metal 10 is covered on type semiconductor region 5.First sub-region surface is additionally provided with planar gate polar region, the grid of planar gate polar region
Dielectric layer 8 covers part heavily doped N-type semiconductor region 4, P-type semiconductor base area 3 and part N-type carrier memory block 6, and grid are situated between
8 upper surface of matter layer is successively covered with polysilicon grid region 14 and gate metal 9 from bottom to up.
A heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in second sub-district, the
Cathode ohmic contact area of the heavily doped N-type semiconductor region 4 of two sub-districts as first diode, the heavily doped P-type of the second sub-district
Anode ohmic contact zone of the semiconductor region 5 as first diode, the cathode ohmic contact area of first diode and emitter gold
Belong to 10 connections.
A heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in third sub-district, the
Cathode ohmic contact area of the heavily doped N-type semiconductor region 4 of three sub-districts as the second diode, the heavily doped P-type of third sub-district
The cathode ohmic contact area of anode ohmic contact zone of the semiconductor region 5 as the second diode, the second diode is floating by first
Empty metal 11 is connect with the anode ohmic contact zone of first diode, i.e., the second diode is connected with first diode.
A heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in 4th sub-district, the
Cathode ohmic contact area of the heavily doped N-type semiconductor region 4 of four sub-districts as third diode, the heavily doped P-type of the 4th sub-district
The cathode ohmic contact area of anode ohmic contact zone of the semiconductor region 5 as third diode, third diode is floating by third
Empty metal 18 is connect with the anode ohmic contact zone of the second diode, i.e. third diode and the second Diode series.
5th sub-district is connect by the second floating metal 12 with the anode ohmic contact zone of third diode, the 5th sub-district and
P-type electric field shielding area 13 is connected, and three-dimensional slot grid region is leaned on the one of near surface pressure resistance area 7 with p-type electric field shielding area 13 by the 5th sub-district
Side section is surrounded, and the 5th sub-district and p-type electric field shielding area 13 collectively form an electric field shielding area.
The ohmic contact regions of base area, the source area of base area, gate regions, P-type semiconductor base area 3, N-type carrier memory block 6,
The nMOS structure of LIGBT, nMOS structure and p-type electric field shielding area 13, first diode, second is collectively formed in emitter metal 10
Diode and third diode constitute the first active area.
16 upper surface of p-type collecting zone is covered with collector electrode metal 17, N-type semiconductor buffer area 15,16 sum aggregate of p-type collecting zone
The second active area is collectively formed in electrode metal 17.
The resistance to pressure area 7 in surface is formed by n type semiconductor layer, and one side connects with three-dimensional slot grid region and N-type carrier memory block 6
Touching, the other side is contacted with N-type semiconductor buffer area 15.In the embodiment of the present invention, the resistance to pressure area 7 in surface with linear gradient by mixing
Miscellaneous n type semiconductor layer is formed, and doping is gradually increased from close to the first active area to the second active area.
Based on both examples above, the working principle of the invention is described in detail with reference to the accompanying drawings of the specification:
Compared with tradition has carrier accumulation layer SOI LIGBT, the present invention has been introduced primarily into series diode and p-type electricity
Field blind zone 13.In conjunction with Fig. 2 and Fig. 4, when device work is in reverse withstand voltage condition, with the rising of collector voltage, p-type electricity
13 current potential of field blind zone also rises with it, when the current potential in p-type electric field shielding area 13 rises about 1.4V or 2.1V, that is, two
Or the sum of three series diode conduction voltage drops are (actually since only leakage current, the voltage that flow through should be less than 1.4V
Or 2.1V), the current potential in p-type electric field shielding area 13 will no longer rise.Simultaneously between N-type carrier memory block 6 and p-type electric field shielding
The resistance to pressure area 7 of part of the surface between area 13, due to its thickness is small, doping concentration is low and quickly by fully- depleted.Hereafter, the first sub-district
P-type semiconductor base area 3 and the reverse biased of PN junction that is formed of N-type carrier memory block 6 substantially will not be with collector voltage
Raising and quickly increase, the increased voltage of collector is mainly formed by the resistance to pressure area 7 in p-type electric field shielding area 13 and surface reverse-biased
Diode is born.In other words, SOI LIGBT proposed by the present invention is mainly formed by the resistance to pressure area 7 in p-type electric field shielding area 13 and surface
PN junction bear reverse biased, rather than by P-type semiconductor base area 3 and N-type carrier memory block 6 in traditional SOI LIGBT structure
The PN junction of formation bears reverse biased.So the doping concentration of N-type carrier memory block 6 is no longer by device breakdown potential in the present invention
The limitation of pressure, so that carrier accumulation layer can be with heavy doping to improve emitter electron injection efficiency.
When device work in forward conduction state, due to N-type carrier memory block 6 have very high doping concentration, make
It obtains a large amount of nonequilibrium carrier to be collected near the first active area, enhances the conductivity modulation effect of the resistance to pressure area 7 in surface, significantly
Reduce the conduction voltage drop (V of deviceon).On the other hand, since series diode understands the current potential in clamper p-type electric field shielding area 13,
Make the nMOS of LIGBT that there is very low drain voltage to improve safety to reduce the saturation current density of device in this way
Workspace.For turn-off characteristic, since emitter injection efficiency is enhanced, it is possible to suitably reduce the note in collector hole
Enter efficiency to obtain identical conduction voltage drop, so that when off, the carrier of the high concentration of emitter will be quick by strong electrical field
It extracts, and after the hole injection efficiency of collector reduces, the lasting injection in hole will be greatly diminished, so that device is with more excellent
Von-EoffTradeoff.
In the embodiment of the present invention, the emulation device structural parameters of use are mainly set are as follows: soi layer buries oxygen with a thickness of 1.5 μm
Floor area 2 with a thickness of 3 μm, device length is 35 μm, and the concentration of N-type carrier memory block 6 is 1 × 1019cm-3, the resistance to pressure area in surface
7 use laterally graded doping, obtained Von-EoffSimulation result is as shown in fig. 6, from fig. 6, it can be seen that the embodiment of the present invention one
There are two the SOI LIGBT devices of diode clamp compared with prior art traditional structure for the tool of offer, has better Von-
EoffCompromise curve, in 300K, identical VonUnder, EoffHave dropped 26.5%.
The key point of the technology of the present invention is for be separated into three-dimensional slot grid region the P-type semiconductor base area 3 of LIGBT multiple
Sub-district, is provided with multiple concatenated diodes in certain sub-districts, series diode and other to be located at three-dimensional slot grid region close
The p-type electric field shielding area 13 of resistance to 7 side of pressure area in surface together by the potential screen of N-type carrier memory block 6 in very low value, from
And the doping concentration of carrier accumulation layer can be greatlyd improve and be unlikely in device pressure resistance, 6 He of N-type carrier memory block
The diode that P-type semiconductor base area 3 is constituted punctures, so as to greatly reduce conduction voltage drop and the raising of LIGBT
Turn-off speed.And since carrier accumulation layer current potential is shielded in very low value, the saturation current density of LIGBT is mentioned
Height, to greatly improve the short-circuit safety operation area of LIGBT.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.This field
Those of ordinary skill disclosed the technical disclosures can make according to the present invention and various not depart from the other each of essence of the invention
The specific variations and combinations of kind, these variations and combinations are still within the scope of the present invention.
Claims (9)
1. with diode clamp carrier accumulation layer SOI LIGBT device, which is characterized in that including semiconductor substrate (1),
Buried oxide layer area (2) on semiconductor substrate (1) and the semiconductor layer on the buried oxide layer area (2)；
The semiconductor layer include P-type semiconductor base area (3), gate regions, N-type carrier memory block (6), the resistance to pressure area in surface (7),
P-type electric field shielding area (13), N-type semiconductor buffer area (15) and p-type collecting zone (16), the P-type semiconductor base area (3) and
Gate region is located at the semiconductor layer other side, the N-type current-carrying in semiconductor layer side, the N-type semiconductor buffer area (15)
Subpool (6) is located at P-type semiconductor base area (3) side, and p-type electric field shielding area (13) is located at by gate regions, the surface
Resistance to pressure area (7) is located between N-type carrier memory block (6), p-type electric field shielding area (13) and N-type semiconductor buffer area (15), institute
It states p-type collecting zone (16) and is set to N-type semiconductor buffer area (15) top side.
2. SOI LIGBT device according to claim 1, which is characterized in that the gate regions include planar gate polar region and
Three-dimensional slot grid region, the planar gate polar region are made of gate dielectric layer (8), gate metal (9) and polysilicon grid region (14), described vertical
Body slot grid region is contacted with P-type semiconductor base area (3), and the solid slot grid region is made of the deep trouth for going deep into semiconductor layer, the depth
Slot includes gate dielectric layer (8), is located in deep trouth by the polysilicon grid region (14) of gate dielectric layer (8) encirclement and covers partially more
The gate metal (9) in crystal silicon grid region (14).
3. SOI LIGBT device according to claim 2, which is characterized in that the P-type semiconductor base area (3) is three-dimensional
Slot grid region is divided into four different sub-districts, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region (4) as the channel base LIGBT, and in the first sub-district
With a heavily doped P-type semiconductor region (5), source area of the heavily doped N-type semiconductor region (4) as the channel base LIGBT,
Ohmic contact regions of the heavily doped P-type semiconductor region (5) as the channel base LIGBT, the part heavily doped N-type semiconductor
Emitter metal (10) are covered on area (4) and part the heavily doped P-type semiconductor region (5)；First sub-region surface is also
It is provided with planar gate polar region, the gate dielectric layer (8) of the planar gate polar region covers part heavily doped N-type semiconductor region (4), P
Type semiconductor base area (3) and part N-type carrier memory block (6), gate dielectric layer (8) upper surface successively cover from bottom to up
There are polysilicon grid region (14) and gate metal (9)；
A heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5), institute are respectively arranged in second sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region (4) of the second sub-district as first diode is stated, second sub-district
Anode ohmic contact zone of the heavily doped P-type semiconductor region (5) as first diode, the cathode ohmic of the first diode connect
Touching area is connect with emitter metal (10)；
A heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5), institute are respectively arranged in third sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region (4) of third sub-district as the second diode is stated, the third sub-district
Anode ohmic contact zone of the heavily doped P-type semiconductor region (5) as the second diode, the cathode ohmic of second diode connect
Touching area is connect by the first floating metal (11) with the anode ohmic contact zone of first diode；
4th sub-district is connect by the second floating metal (12) with the anode ohmic contact zone of the second diode, the 4th sub-district
It is connected with p-type electric field shielding area (13), the 4th sub-district is resistance to by near surface by three-dimensional slot grid region with p-type electric field shielding area (13)
One side section of pressure area (7) is surrounded, and the 4th sub-district and p-type electric field shielding area (13) collectively form an electric field shielding area.
4. SOI LIGBT device according to claim 3, which is characterized in that the ohmic contact regions of the base area, base area
LIGBT is collectively formed in source area, gate regions, P-type semiconductor base area (3), N-type carrier memory block (6), emitter metal (10)
NMOS structure, the nMOS structure and p-type electric field shielding area (13), first diode and the second diode, which constitute first, to be had
Source region.
5. SOI LIGBT device according to claim 2, which is characterized in that the P-type semiconductor base area (3) is three-dimensional
Slot grid region is divided into five different sub-districts, in which:
First sub-district is respectively arranged with a heavily doped N-type semiconductor region (4) as the channel base LIGBT, and in the first sub-district
With a heavily doped P-type semiconductor region (5), source area of the heavily doped N-type semiconductor region (4) as the channel base LIGBT,
Ohmic contact regions of the heavily doped P-type semiconductor region (5) as the channel base LIGBT, the part heavily doped N-type semiconductor
Emitter metal (10) are covered on area (4) and part the heavily doped P-type semiconductor region (5)；First sub-region surface is also
It is provided with planar gate polar region, the gate dielectric layer (8) of the planar gate polar region covers part heavily doped N-type semiconductor region (4), P
Type semiconductor base area (3) and part N-type carrier memory block (6), gate dielectric layer (8) upper surface successively cover from bottom to up
There are polysilicon grid region (14) and gate metal (9)；
A heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5), institute are respectively arranged in second sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region (4) of the second sub-district as first diode is stated, second sub-district
Anode ohmic contact zone of the heavily doped P-type semiconductor region (5) as first diode, the cathode ohmic of the first diode connect
Touching area is connect with emitter metal (10)；
A heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5), institute are respectively arranged in third sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region (4) of third sub-district as the second diode is stated, the third sub-district
Anode ohmic contact zone of the heavily doped P-type semiconductor region (5) as the second diode, the cathode ohmic of second diode connect
Touching area is connect by the first floating metal (11) with the anode ohmic contact zone of first diode；
A heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5), institute are respectively arranged in 4th sub-district
Cathode ohmic contact area of the heavily doped N-type semiconductor region (4) of the 4th sub-district as third diode is stated, the 4th sub-district
Anode ohmic contact zone of the heavily doped P-type semiconductor region (5) as third diode, the cathode ohmic of the third diode connect
Touching area is connect by third floating metal (18) with the anode ohmic contact zone of the second diode；
5th sub-district is connect by the second floating metal (12) with the anode ohmic contact zone of third diode, the 5th sub-district
It is connected with p-type electric field shielding area (13), the 5th sub-district is resistance to by near surface by three-dimensional slot grid region with p-type electric field shielding area (13)
One side section of pressure area (7) is surrounded, and the 5th sub-district and p-type electric field shielding area (13) collectively form an electric field shielding area.
6. SOI LIGBT device according to claim 5, which is characterized in that the ohmic contact regions of the base area, base area
LIGBT is collectively formed in source area, gate regions, P-type semiconductor base area (3), N-type carrier memory block (6), emitter metal (10)
NMOS structure, the nMOS structure and p-type electric field shielding area (13), first diode, the second diode and the three or two pole
Pipe constitutes the first active area.
7. according to any SOI LIGBT device of claim 4 or 6, which is characterized in that on the p-type collecting zone (16)
Surface is covered with collector electrode metal (17), the N-type semiconductor buffer area (15), p-type collecting zone (16) and collector electrode metal
(17) the second active area is collectively formed.
8. SOI LIGBT device according to claim 7, which is characterized in that the resistance to pressure area in surface (7) is partly led by N-type
Body layer is formed, and one side is contacted with three-dimensional slot grid region and N-type carrier memory block (6), and the other side and N-type semiconductor buffer
Area (15) contact.
9. SOI LIGBT device according to claim 8, which is characterized in that the resistance to pressure area in surface (7) is linear by having
The n type semiconductor layer of gradient doping is formed, and doping is gradually increased from close to the first active area to the second active area.
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| CN201910316577.6A CN109888007B (en) | 2019-04-19 | 2019-04-19 | SOI LIGBT device with diode clamped carrier storage layer |
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| CN201910316577.6A CN109888007B (en) | 2019-04-19 | 2019-04-19 | SOI LIGBT device with diode clamped carrier storage layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504312A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of transversal I GBT with short-circuit self-shield ability |
| CN110504305A (en) * | 2019-08-06 | 2019-11-26 | 电子科技大学 | A kind of SOI-LIGBT device with automatic biasing pmos clamper carrier accumulation layer |
| CN111403385A (en) * | 2020-03-02 | 2020-07-10 | 电子科技大学 | RC-L IGBT device with embedded Schottky diode |
| CN111816698A (en) * | 2020-08-31 | 2020-10-23 | 电子科技大学 | Power device integrated with Zener diode and collector PMOS structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959345A (en) * | 1997-11-28 | 1999-09-28 | Delco Electronics Corporation | Edge termination for zener-clamped power device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
| CN109103186A (en) * | 2018-08-14 | 2018-12-28 | 电子科技大学 | A kind of integrated hetero-junctions freewheeling diode silicon carbide tank gate MOSFET |
-
2019
- 2019-04-19 CN CN201910316577.6A patent/CN109888007B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959345A (en) * | 1997-11-28 | 1999-09-28 | Delco Electronics Corporation | Edge termination for zener-clamped power device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
| CN109103186A (en) * | 2018-08-14 | 2018-12-28 | 电子科技大学 | A kind of integrated hetero-junctions freewheeling diode silicon carbide tank gate MOSFET |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504305A (en) * | 2019-08-06 | 2019-11-26 | 电子科技大学 | A kind of SOI-LIGBT device with automatic biasing pmos clamper carrier accumulation layer |
| CN110504312A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of transversal I GBT with short-circuit self-shield ability |
| CN111403385A (en) * | 2020-03-02 | 2020-07-10 | 电子科技大学 | RC-L IGBT device with embedded Schottky diode |
| CN111403385B (en) * | 2020-03-02 | 2022-10-14 | 电子科技大学 | RC-LIGBT device with embedded Schottky diode |
| CN111816698A (en) * | 2020-08-31 | 2020-10-23 | 电子科技大学 | Power device integrated with Zener diode and collector PMOS structure |
| CN111816698B (en) * | 2020-08-31 | 2021-06-08 | 电子科技大学 | Power device integrated with Zener diode and collector PMOS structure |
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| CN109888007B (en) | 2020-08-18 |
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