KR102087029B1 - Display device and manufacturing method thereof - Google Patents

Abstract

Provided are a display device and a method of manufacturing the same, which can prevent a malfunction of a thin film transistor by applying a double layer light blocking layer to block a drain electric field. The display device is formed of a substrate, an oxide semiconductor layer formed on the substrate, and a light blocking layer having a double structure of a silicon film doped with a metal film and a P-type doped on the metal film and between the substrate and the oxide semiconductor layer. It includes.

Description

Display device and manufacturing method thereof {DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a top gate structure and a method of manufacturing the same. In particular, a display device capable of preventing malfunction of a thin film transistor by blocking a drain electric field by applying a light blocking layer having a double structure, and a method of manufacturing the same. It is about.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes, and the flat panel display includes a liquid crystal display and a field emission display. , Plasma display panels, organic light emitting displays, and the like.

In particular, the display device has advantages such as miniaturization, light weight, and low power consumption, and is generally configured as an active matrix type. In an active matrix type display device, pixels arranged in a matrix form are defined by intersections of a plurality of scan lines and a plurality of data lines, and the pixels are provided with a thin film transistor as a switching element. The thin film transistor includes a semiconductor layer having a channel region, a gate electrode, and a source / drain electrode.

The thin film transistor of the display device may be divided into a display device having a bottom gate structure and a top gate structure according to a formation position of the gate electrode. The bottom gate structure display device has a structure in which a gate electrode is positioned below the source electrode and a drain electrode, and the top gate structure display device has a structure in which the gate electrode is positioned above the source electrode and the drain electrode.

The display device of the top gate structure can minimize parasitic capacitance between the gate electrode and the source / drain electrodes as compared to the display device of the bottom gate structure. However, in the display device having the top gate structure, since the gate electrode is on the upper side, light emitted from the backlight of the display device, or reflected light or external light from the display device may affect the semiconductor layer. Therefore, in the conventional top gate display device, an additional light blocking layer is required to block light flowing from the bottom.

1 is a view showing a display device of a conventional top gate structure.

Referring to FIG. 1, a conventional display device 1 includes a light blocking layer 3 formed on a substrate 2, a buffer layer 4 and a buffer layer 4 formed on an entire surface of a substrate 2 on which a light blocking layer 3 is formed. ) And a semiconductor layer 5 formed in a region corresponding to the light blocking layer 3.

In addition, a contact hole (not shown) covering the gate insulating layer 6 and the gate electrode 7, the gate electrode 7, and the semiconductor layer 5 formed on the semiconductor layer 5 and exposing the semiconductor layer 5 is exposed. And a source electrode 9 and a drain electrode 10 connected to the semiconductor layer 5 through the formed interlayer insulating film 8 and contact holes.

In addition, a passivation film 11 having a contact hole (not shown) covering the source electrode 9 and the drain electrode 10 and exposing the drain electrode 10 is connected to the drain electrode 10 through the contact hole. The pixel electrode 12 is included.

The light blocking layer 3 of the above-described conventional display device 1 is formed of a floating metal film that is not electrically connected to the outside. The light blocking layer 3 of the floating structure is formed to cover a region where the source electrode 9 and the drain electrode 10 are formed so as to prevent the inflow of light from the lower portion.

However, since the conventional light blocking layer 3 is formed to cover the source electrode 9 and the drain electrode 10, electric charge is induced to the light blocking layer 3 by the electric field generated from the drain electrode 10, As a result, the electrical potential of the semiconductor layer 5 is lowered to move the threshold voltage in the negative direction.

As a result, current-voltage characteristics of the drain electrode become poor, which causes malfunction of the thin film transistor, thereby degrading operation reliability of the display device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and by forming a double structure by adding a silicon film on top of the light blocking layer so as to block an electric field between the drain electrode and the light blocking layer, the display which can improve the operation reliability of the display device. An object of the present invention is to provide a device and a method of manufacturing the same.

A display device according to an embodiment of the present invention for achieving the above object is a substrate; An oxide semiconductor layer formed on the substrate; And a light blocking layer formed between the substrate and the oxide semiconductor layer so as to correspond to the oxide semiconductor layer, and having a double structure of a metal film and a silicon film doped with a P type on the metal film.

In accordance with an aspect of the present invention, there is provided a method of manufacturing a display device, including sequentially depositing and selectively patterning a metal material and an amorphous silicon doped with a P type on a substrate, thereby forming a dual structure of a metal film and a silicon film. Forming a light blocking layer; And forming an oxide semiconductor layer on the light blocking layer to correspond to the light blocking layer.

According to the display device of the present invention and a method of manufacturing the same, a malfunction of the thin film transistor can be improved by blocking an electric field from the drain electrode by adding an amorphous silicon film doped with P type on the light blocking layer.

In addition, by forming the light blocking layer in a floating structure to cover the source / drain electrodes, it is possible to reduce the reflection of the upper light as well as the light flowing from the lower portion of the display device, thereby improving the reliability of the thin film transistor.

1 is a view of a display device of a conventional top gate structure.
2 is a diagram of a display device having a top gate structure according to an exemplary embodiment of the present invention.
3A to 3D are process diagrams of the display device shown in FIG. 2.
4A is a graph of current-voltage characteristics of a conventional display device.
4B is a graph of current-voltage characteristics of the display device according to the present invention.

Hereinafter, a display device and a manufacturing method thereof of the top gate structure according to the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a display device having a top gate structure according to the present invention.

3A to 3D are process diagrams of the display device of FIG. 2.

First, referring to FIG. 2, the display device 100 according to the present invention includes a light blocking layer 105, an oxide semiconductor layer 107, a gate electrode 109, a source electrode 111, The drain electrode 113 and the pixel electrode 117 may be included.

In addition, the display device 100 may include a buffer layer 106 formed between the light blocking layer 105 and the oxide semiconductor layer 107, and a gate insulating layer 108 formed between the gate electrode 109 and the oxide semiconductor layer 107. It may further include.

In addition, the display device 100 includes an interlayer insulating film 110 and a source electrode 111 and a drain electrode 113 and a pixel electrode 117 formed between the gate electrode 109, the source electrode 111, and the drain electrode 113. May further include a passivation film 115 formed between the layers.

The light blocking layer 105 corresponding to the oxide semiconductor layer 107 with the buffer layer 106 interposed therebetween may cover both the source electrode 111 and the drain electrode 113 at a position corresponding to the oxide semiconductor layer 107. It can be formed to be.

The light blocking layer 105 may be formed in a double film structure of the metal film 102 and the silicon film 103. The light blocking layer 105 may be formed through a process such as sputtering, chemical vapor deposition (CVD), or ion implantation.

2 and 3A, the light blocking layer 105 may be formed by sequentially depositing a metal material (not shown) and amorphous silicon (not shown) on the front surface of the substrate 101, and selectively patterning them.

The metal material may be a metal having low light transmittance, such as aluminum (Al), copper (Cu), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), or tantalum (Ta). Molybdenum alloys such as MoTi, MoTa or MoNb may be used.

The metal material may be patterned together with amorphous silicon, which will be described later, through a patterning process, and may form a lower structure of the light blocking layer 105, that is, a lower metal layer 102.

The amorphous silicon may be silicon (Si) doped with P type, but silicon of nanocrystalline or microcrystalline form may be doped with P type and used. In addition, one of materials other than silicon, such as germanium (Ge), silicon carbide (SiC), silicon oxide (SiOx), zinc oxide (ZnO), or the like in amorphous, nanocrystalline or microcrystalline form, may be used. .

The amorphous silicon may be patterned together with the metal material through a patterning process, and the upper structure of the light blocking layer 105, that is, the upper silicon film 103 may be formed.

As described above, the silicon film 103 forming the upper structure of the light blocking layer 105 may be a silicon film doped with a P type. When the silicon film 103 is deposited with a metal material on the substrate 101 and then amorphous silicon is deposited by a CVD process, the concentration of a gas, for example, a dopant gas, is adjusted to P type. Can be doped.

For example, when depositing amorphous silicon on the substrate 101 by a CVD process, a diborane (B2H6) gas and a silane (SiH4) gas may be used, and by adjusting the concentration ratio of B2H6 and SiH4 The amorphous silicon may be doped to P type. Here, the B2H6 gas may be adjusted to have a concentration range of 0.1 to 10%, preferably 0.5 to 1%, compared to the SiH4 gas.

In the present embodiment, an example in which amorphous silicon is doped to P type when deposited by a CVD process has been described. However, as described above, germanium, silicon carbide, silicon oxide, or zinc oxide in amorphous, nanocrystalline or microcrystalline form is also amorphous. It may be doped to P type through the same CVD process as silicon.

In addition, the silicon film 103 may be doped to a P type through an ion implantation process. In other words, the metal material and the amorphous silicon may be sequentially deposited on the substrate 101, and the P-type dopant material may be ion implanted into the deposited silicon to allow the amorphous silicon to be doped into the P-type.

For example, after depositing silicon on the substrate 101, ion implantation using boron (B), aluminum (Al), gallium (Ga), indium (In), etc. as a dopant material, the silicon is P-type To be doped.

In addition, by depositing germanium on the substrate 101, by implanting the boron, aluminum, gallium, indium, etc. as a dopant material, it is possible to make the germanium doped to the P type. In addition, by depositing silicon carbide on the substrate 101 and ion implantation using aluminum or the like as a dopant material, the silicon carbide can be doped to P type. In addition, after zinc oxide is deposited on the substrate 101, ion implantation is performed using nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), copper (Cu), or the like as a dopant material. Zinc can be doped to P type.

As described above, a silicon film doped with a P type may be formed through an ion implantation process of a dopant material. In this case, elements used as the dopant material may be doped in a concentration range of approximately 10 ¹⁷ to 10 ²¹ atoms / cm ³ , and an appropriate doping depth may be determined in an ion implantation process. As the doping concentration of the dopant material is increased, the thickness of the silicon film formed may be reduced.

In addition, the silicon film 103 may be formed through a sputtering process targeting silicon doped with P type, or may be formed by diffusing a P type dopant material.

Subsequently, the metal layer 102 and the silicon layer 103 may be doubled by selectively patterning the metal material sequentially deposited on the substrate 101 and the amorphous silicon doped with P type through a photo process using a mask. The light blocking layer 105 having a film structure can be formed.

Meanwhile, the light blocking layer 105 may be formed as a floating structure that is separated from the upper structures, that is, the oxide semiconductor layer 107 with the buffer layer 106 interposed therebetween. The light blocking layer 105 may be formed to cover the entire region of the oxide semiconductor layer 107, or may be formed to cover a connection portion between the oxide semiconductor layer 107 and the source / drain electrodes 111 and 113.

Accordingly, the light blocking layer 105 according to the present invention is parasitic between the oxide semiconductor layer 107 because the upper silicon film 103 blocks the drain electric field so that the electric field is not induced to the light blocking layer 105. No capacitance is formed.

In addition, since the light blocking layer 105 is formed to cover the entire oxide semiconductor layer 107, not only the light flowing into the oxide semiconductor layer 107 from the lower portion of the display device 100, but also the upper electrodes such as a source electrode. Light reflected by the 111 or the drain electrode 113 may be reduced. In addition, since the silicon film 103 formed on the light blocking layer 105 absorbs light, reflection of light flowing from the upper portion of the display device 100 may be reduced.

2 and 3B, the buffer layer 106 may be formed to cover the light blocking layer 105 on the entire surface of the substrate 101 on which the light blocking layer 105 is formed.

The buffer layer 106 may be formed of an oxide, nitride, or oxynitride containing at least one of Si, Ge, Al, Hf, Ti, In, Ga, La, and Ta. It may be formed to a thickness of approximately 500 ~ 7000Å.

An oxide semiconductor layer 107 may be formed on the buffer layer 106. The oxide semiconductor layer 107 may be formed to correspond to the light blocking layer 105 by depositing an oxide including a metal material on the buffer layer 106 and selectively patterning the oxide.

The oxide semiconductor layer 107 includes, but is not limited to, InGaZnO-based materials, and includes In, Ga, Zn, Al, tin (Sn), zirconium (Zr), hydrogen fluoride (Hf), cadmium (Cd), and nickel ( Ni) and Cu, and may be formed of an oxide including at least one metal selected from Cu.

The oxide semiconductor layer 107 has an active region 107a in the center portion, i.e., a portion corresponding to the gate electrode 109, and a conductorization region in both portions, ie, the portion corresponding to the source electrode 111 and the drain electrode 113. 107b.

The conductive region 107b of the oxide semiconductor layer 107 may be formed by a dry etch process, plasma treatment, hydrogen diffusion, metal diffusion, doping, or the like, and may be a region having high conductivity. have. For example, in the patterning process of the gate insulating layer 108, the conductive region 107b may be formed to have high conductivity by self aligning by overetching by increasing the time of dry etching. have.

2 and 3C, the gate insulating film 108 and the gate electrode 109 are formed by sequentially depositing and patterning a silicon film and a metal film on the entire surface of the substrate 101 including the oxide semiconductor layer 107.

The gate insulating layer 108 may be formed of oxide, nitride, or oxynitride containing at least one of Si, Ge, Al, Hf, Ti, In, Ga, La, and Ta. It may be formed to a thickness of approximately 500 ~ 7000Å.

The gate electrode 109 may be formed of a metal material of aluminum (Al), copper (Cu), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), or tantalum (Ta) or MoTi, MoW, MoTa or A metal material such as MoNb molybdenum alloy (Mo alloy) may be deposited by CVD or sputtering, and then selectively patterned.

Subsequently, an interlayer insulating layer 110 may be formed on the entire surface of the substrate 101 including the gate electrode 109.

The interlayer insulating layer 110 may be formed of oxide, nitride, or oxynitride containing at least one of Si, Ge, Al, Hf, Ti, In, Ga, La, and Ta. It may be formed to a thickness of approximately 500 ~ 7000Å.

In addition, the oxide semiconductor layer 107 may be exposed by forming the first contact hole 110a and the second contact hole 110b in the interlayer insulating layer 110.

On the other hand, the gate insulating film 108 is shown to be formed only below the gate electrode 109, but is not limited thereto. For example, the gate insulating layer 108 may be formed to cover the entire substrate 101 on which the oxide semiconductor layer 107 is formed. In this case, the first contact hole 110a and the second contact hole formed in the interlayer insulating layer 110 may be formed. The gate 110b may be formed up to the gate insulating layer 108 to expose the oxide semiconductor layer 107.

2 and 3D, a metal film may be deposited and patterned on the entire surface of the substrate 101 on which the interlayer insulating layer 110 is formed to form the source electrode 111 and the drain electrode 113.

The source electrode 111 is formed to cover the first contact hole 110a and is connected to the oxide semiconductor layer 107, and the drain electrode 113 is formed to cover the second contact hole 110b to form the oxide semiconductor layer ( 107).

The source electrode 111 and the drain electrode 113 may be formed of a metal material of aluminum (Al), copper (Cu), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), or tantalum (Ta). A metal material such as MoTi, MoW, MoTa, or MoNb molybdenum alloy (Mo alloy) may be deposited by CVD or sputtering, and selectively patterned.

Subsequently, the passivation layer 115 may be formed on the entire surface of the substrate 101 on which the source electrode 111 and the drain electrode 113 are formed.

The passivation film 115 may be formed of oxide, nitride, or oxynitride containing at least one of Si, Ge, Al, Hf, Ti, In, Ga, La, and Ta. It may be formed to a thickness of approximately 500 ~ 7000Å.

In addition, a third contact hole 115a may be formed in the passivation layer 115 to expose the drain electrode 113.

As shown in FIG. 2, the pixel electrode 117 may be formed by depositing and patterning a metal film on the passivation film 115.

The pixel electrode 117 may be formed to cover the third contact hole 115a and be connected to the drain electrode 113. The pixel electrode 117 may be formed of a transparent conductive metal material, for example, a transparent conductive metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

4A is a current-voltage characteristic graph in a conventional display device, and FIG. 4B is a current-voltage characteristic graph in a display device according to the present invention.

1 and 4A, in the conventional display device 1, since the drain electric field is induced in the light blocking layer 3 formed on the substrate 2, the current-voltage characteristic of the high drain voltage VDS is negative ( Move in the direction of-).

The movement of the drain voltage causes a phenomenon in which the current-voltage characteristics of the high drain voltage VDS and the low drain voltage Vds are opened, which causes abnormal operation of the thin film transistor.

However, referring to FIGS. 2 and 4B, since the drain electric field is not induced to the light blocking layer 105 by the silicon film 103 on the light blocking layer 105, the display device 100 according to the present invention is high. The current-voltage characteristic of the drain voltage VDS does not move. As a result, abnormal operation of the thin film transistor due to the drain electric field can be prevented.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

102: metal film 103: silicon film
105: light blocking layer 107: oxide semiconductor layer
109: gate electrode 111: source electrode
113: drain electrode 117: pixel electrode

Claims (10)

Board;
An oxide semiconductor layer formed on the substrate;
A gate electrode formed on the oxide semiconductor layer;
An interlayer insulating layer formed on the gate electrode and having first and second contact holes exposing the oxide semiconductor layer;
A source electrode and a drain electrode formed on the interlayer insulating film and connected to the oxide semiconductor layer through the first and second contact holes;
A light blocking layer formed between the substrate and the oxide semiconductor layer so as to correspond to the oxide semiconductor layer, and having a double structure of a metal film and a silicon film doped with a P type on the metal film; And
A buffer layer disposed between the light blocking layer and the oxide semiconductor layer,
The light blocking layer is separated from the oxide semiconductor layer with the buffer layer interposed therebetween.
And an electric field between the drain electrode and the metal film of the light blocking layer is blocked by a silicon film doped with a P type of the light blocking layer. The method of claim 1,
The silicon layer is doped with a P type by adjusting the concentration of the deposition gas. The method of claim 1,
And the silicon film is a silicon film doped with P type by implanting ions containing a boron element. The method of claim 1,
A passivation layer formed on the source electrode and the drain electrode and having a third contact hole exposing the drain electrode; And
And a pixel electrode formed on the passivation layer and connected to the drain electrode through the third contact hole. Depositing and selectively patterning a metal material and an amorphous silicon doped with P-type on a substrate to form a light blocking layer having a dual structure of a metal film and a silicon film;
Forming a buffer layer on the substrate on which the light blocking layer is formed;
Forming an oxide semiconductor layer on the buffer layer so as to correspond to the light blocking layer;
Forming a gate electrode on the oxide semiconductor layer;
Forming an interlayer insulating film having first and second contact holes exposing the oxide semiconductor layer on the gate electrode;
Forming a source electrode and a drain electrode connected to the oxide semiconductor layer through the first and second contact holes on the interlayer insulating film,
Forming the buffer layer, wherein the light blocking layer is separated from the oxide semiconductor layer with the buffer layer interposed therebetween. The method of claim 5,
The forming of the light blocking layer may include depositing amorphous silicon on the metal material by chemical vapor deposition, and controlling the concentration of the deposition gas to form the amorphous silicon doped with the P-type. The method of claim 6,
The deposition gas is a manufacturing method of a display device for adjusting the concentration of B2H6 / SiH4 in the range of 0.5 ~ 1%. The method of claim 5,
The forming of the light blocking layer may include depositing amorphous silicon on the metal material and ion implanting a P type dopant material into the amorphous silicon to form the P type amorphous silicon. . The method of claim 8,
The P-type dopant material is one of boron, aluminum, gallium and indium. The method of claim 5,
Forming a passivation film having a third contact hole exposing the drain electrode on the source electrode and the drain electrode; And
And forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the third contact hole.

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