KR102255589B1 - Oxide Semiconductor Thin Film Transistor Substrate Having Light Shield Layer Of Light Guiding Structure - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a flat panel display device comprising an oxide semiconductor having a light-shielding layer having an optical waveguide structure. The thin film transistor substrate according to the present invention includes a substrate, a plurality of pixel regions, a thin film transistor, a light shielding layer, a buffer layer, and a pixel electrode. The plurality of pixel regions are arranged in a matrix manner on the substrate. The thin film transistor is disposed in each pixel region and has a channel region including an oxide semiconductor material. The light blocking layer is interposed between the substrate and the thin film transistor, and a first metal layer having a light blocking thickness, a high refractive index layer, and a second metal layer having a light transmitting thickness are stacked. The buffer layer is interposed between the light shielding layer and the thin film transistor, and covers the entire surface of the substrate. Then, it is connected to the thin film transistor and disposed in the pixel region.

Description

[Oxide Semiconductor Thin Film Transistor Substrate Having Light Shield Layer Of Light Guiding Structure}

The present invention is a flat panel display device such as a liquid crystal display (LCD) and/or an organic light emitting diode display (OLED) including an oxide semiconductor having a light-shielding layer of an optical waveguide structure. It relates to a thin film transistor substrate for. In particular, the present invention relates to a thin film transistor substrate for a flat panel display device having an oxide semiconductor having an optical waveguide structure to prevent the inflow of external light into the channel region due to diffraction and reflection, and having a light-shielding layer that reduces the amount of incoming light. .

The display device field has rapidly changed to a flat panel display device (FPD) that is thin, light, and capable of large area, replacing a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED).

In the case of an active liquid crystal display device, an organic light emitting display device, and an electrophoretic display device, a thin film transistor substrate including a thin film transistor allocated in a pixel region arranged in a matrix manner is disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. An organic light-emitting display device displays an image by forming an organic light-emitting element on the pixels themselves arranged in a matrix manner.

1 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device, which is a type of horizontal electric field type according to the prior art. FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line I-I'.

The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 1 and 2 is a gate wiring GL and a data wiring DL intersecting on a lower substrate SUB with a gate insulating layer GI interposed therebetween, and a cross structure thereof. A thin film transistor T formed in each pixel region defined by is provided.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate. It includes a semiconductor layer (A) forming a channel region between the source electrode (S) and the drain electrode (D) when overlapping the gate electrode (G) on the insulating layer (GI).

In particular, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a large charging capacity due to its high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protection from an etchant on the upper surface in order to secure the stability of the device. Specifically, it is preferable to form the etch stopper ES to protect the semiconductor layer A from the etchant introduced through the separated portion between the source electrode S and the drain electrode D.

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 penetrating the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2. Meanwhile, a data pad DP for receiving a pixel signal from the outside is included at one end of the data line DL. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2.

In the pixel area, a pixel electrode PXL and a common electrode COM formed with the second passivation layer PA2 interposed therebetween are provided to form a fringe field. The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may be variously formed according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes at any time according to the video data to be implemented is applied to the pixel electrode PXL. Accordingly, parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such parasitic capacitance may cause a problem in image quality, it is preferable to first form the common electrode COM and then form the pixel electrode PXL on the uppermost layer.

That is, after forming a planarization layer PAC formed by thickly forming an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. In addition, after forming the second passivation layer PA2 covering the common electrode COM, a pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2. In this structure, since the pixel electrode PXL is separated by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL are separated. In between, the parasitic capacity can be reduced.

The common electrode COM is formed in a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL is formed in the shape of a plurality of line segments. In particular, the pixel electrode PXL has a structure vertically overlapping the common electrode COM with the second passivation layer PA2 interposed therebetween. A fringe field is formed between the pixel electrode PXL and the common electrode COM, so that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

An example of another flat panel display device is an electroluminescent display device. Electroluminescent displays are roughly classified into inorganic electroluminescent displays and organic light emitting diode displays depending on the material of the light emitting layer, and are self-luminous devices that emit light, have a fast response speed, and have great luminous efficiency, luminance, and viewing angles. In particular, the organic light emitting diode display (OLEDD) using the characteristics of an organic light emitting diode with excellent energy efficiency includes a passive matrix type organic light emitting diode display (PMOLED) and It is broadly classified as an active matrix type organic light emitting diode display (AMOLED).

3 is a plan view showing a structure of one pixel in an active matrix organic light emitting diode display. FIG. 4 is a cross-sectional view illustrating the structure of an active matrix organic light emitting diode display taken along line II-II' in FIG. 3.

3 and 4, the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode OLE connected to the driving thin film transistor DT. Includes.

The switching thin film transistor ST is formed at a portion where the scan line SL and the data line DL cross each other. The switching thin film transistor ST serves to select a pixel. The switching thin film transistor ST includes a gate electrode SG branching from the scan line SL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT serves to drive the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST.

The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. The organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the ground voltage VSS.

Referring to FIG. 4 to examine in more detail, the switching thin film transistor ST and the gate electrodes SG and DG of the driving thin film transistor DT are formed on the substrate SUB of the active matrix organic light emitting diode display. have. In addition, the gate insulating film GI is covering the gate electrodes SG and DG. The semiconductor layers SA and DA are formed on a part of the gate insulating film GI overlapping the gate electrodes SG and DG. Source electrodes SS and DS and drain electrodes SD and DD are formed on the semiconductor layers SA and DA at regular intervals to face each other. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH formed in the gate insulating layer GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is applied on the entire surface.

The color filter CF is formed in a portion corresponding to the area of the anode electrode ANO to be formed later. It is preferable to form the color filter CF to occupy as large an area as possible. For example, it is preferable to form the data line DL, the driving current line VDD, and the plurality of regions of the scan line SL at the front end to overlap each other. In the substrate on which the color filter CF is formed as described above, the surface of the substrate on which the color filter CF is formed is not flat and has many steps. Therefore, a planarization film (PAC) or an overcoat layer (OC) is applied to the entire surface of the substrate for the purpose of flattening the surface of the substrate.

In addition, the anode electrode ANO of the organic light emitting diode OLE is formed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

On the substrate on which the anode electrode ANO is formed, in order to define a pixel region, a bank BA (or , Bank pattern).

The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic light emitting layer OL and a cathode electrode CAT are sequentially stacked on the anode electrode ANO exposed by the bank BA. When the organic light-emitting layer OL is made of an organic material emitting white light, the organic light-emitting layer OL represents a color assigned to each pixel by the color filter CF located below. The organic light emitting diode display having the structure as shown in FIG. 4 becomes a bottom emission display device that emits light in a downward direction.

By including the thin film transistor in the flat panel display as described above, a high-quality active display device can be implemented. In particular, in order to have more excellent driving characteristics, the semiconductor layer of the thin film transistor is preferably formed of a metal oxide semiconductor material.

The metal oxide semiconductor material has a characteristic that when voltage is driven while being exposed to light, its characteristics are rapidly deteriorated. Therefore, it is desirable to have a structure capable of blocking light from outside in the upper and lower portions of the semiconductor layer. In the case of the aforementioned thin film transistor substrate, the thin film transistor has a bottom gate structure. Accordingly, light flowing from the bottom may be partially blocked by the gate electrode G, which is a metal material.

However, in the bottom gate structure, the source-drain electrode and the gate electrode overlap. In this structure, a parasitic capacitance is formed between the source electrode S and the gate electrode G, which may deteriorate the characteristics of the thin film transistor. In addition, in the bottom gate structure, light flowing from the bottom may be blocked by the gate electrode G, but in order to block the light flowing from the top, an additional light blocking layer must be formed.

Referring to FIG. 5, a thin film transistor substrate having a top gate structure and including a metal oxide semiconductor material will be described. In order to minimize the parasitic capacitance generated between the gate electrode and the source-drain electrode, a thin film transistor having a top gate structure is suitable. 5 is a cross-sectional view showing a thin film transistor substrate having a top gate structure according to the prior art.

Referring to FIG. 5, a thin film transistor substrate having a top gate structure includes a pixel region disposed on a substrate SUB in a matrix arrangement, and a thin film transistor T allocated one to each pixel region. The semiconductor layer of the thin film transistor T is directly formed on the substrate SUB. The semiconductor layer includes a channel region A in the center, a source region SA disposed on the left side of the channel region A, and a drain region DA disposed on the right side of the channel region A.

A gate insulating film GI and a gate electrode G are formed on the channel region A of the semiconductor layer. The gate insulating layer GI and the gate electrode G have substantially the same size as the channel region A and have a structure substantially vertically and completely overlapped. The intermediate insulating layer IN is covered on the semiconductor layer and the gate electrode G. The intermediate insulating layer IN covering the source region SA and the drain region DA of the semiconductor layer is partially removed so that the source electrode S and the drain electrode D contact each other.

The protective layer PAS covers the entire substrate SUB on which the thin film transistor T including the source electrode S, the channel region A, the gate electrode G, and the drain electrode D is formed. The drain electrode D is exposed by removing a portion of the passivation layer PAS covering the drain electrode D. The exposed drain electrode D is connected to the pixel electrode PXL or the anode electrode ANO formed on the passivation layer PAS.

As described above, in the thin film transistor T having the top gate structure, the end of the gate electrode G and the end of the source electrode S have a gate-source gap Ggs spaced apart by a predetermined distance. Similarly, an end of the gate electrode G and an end of the drain electrode D have a gate-drain interval Ggd spaced apart by a predetermined distance. Therefore, almost no parasitic capacitance is formed between the gate electrode G and the source-drain electrode S-D. As a result, it is possible to prevent the characteristics of the channel region A from deteriorating.

However, in the top gate structure as shown in FIG. 5, it is easy to be exposed by light flowing from the lower portion of the substrate SUB, for example, a backlight. When external light flows into the channel region A, the characteristics of the channel region A are deteriorated, and when used for a long period of time, the characteristics of the thin film transistor may be changed. This may cause the image quality of the display device to deteriorate.

In order to improve the performance of the display device, it is preferable to have a top gate structure for improving material properties and to include a thin film transistor including an oxide semiconductor material. In this case, there is a need for a new structure and/or a new component capable of preventing external light from flowing into the channel region of the thin film transistor.

An object of the present invention is to provide a thin film transistor substrate having a top gate structure minimizing parasitic capacitance between a gate electrode and a source-drain electrode constituting a thin film transistor, as an invention devised to solve the problems of the prior art. have. Another object of the present invention is to provide a thin film transistor substrate having a light shielding layer for blocking light from flowing into a channel region of a semiconductor layer from a lower portion of a thin film transistor substrate having a top gate structure. Another object of the present invention is to provide a light-shielding layer having an optical waveguide structure that prevents the light-shielding layer from entering the channel region by diffraction at the outer boundary of the light-shielding layer or from being introduced by reflection between the light-shielding layer and the source-drain metal layer. It is to provide a thin film transistor substrate.

In order to achieve the above object, the thin film transistor substrate according to the present invention includes a substrate, a plurality of pixel regions, a thin film transistor, a light shielding layer, a buffer layer, and a pixel electrode. The plurality of pixel regions are arranged in a matrix manner on the substrate. The thin film transistor is disposed in each pixel region and has a channel region including an oxide semiconductor material. The light blocking layer is interposed between the substrate and the thin film transistor, and a first metal layer having a light blocking thickness, a high refractive index layer, and a second metal layer having a light transmitting thickness are stacked. The buffer layer is interposed between the light shielding layer and the thin film transistor, and covers the entire surface of the substrate. Then, it is connected to the thin film transistor and disposed in the pixel region.

For example, the first metal layer includes any one of molybdenum, titanium, and molybdenum-titanium, and has a thickness of 1,000 Å or more. The second metal layer includes the same material as the first metal layer, and has a thickness of 100 Å or less. The high refractive layer includes a material having a refractive index higher than that of the first and second metal layers, and has a thickness of 100 Å or more to 500 Å or less.

For example, the thin film transistor further includes a gate electrode, a source electrode, and a drain electrode. The gate electrode overlaps the channel region. The source electrode is connected to one side of the channel region. In addition, the drain electrode is connected to the other side of the channel region and connected to the pixel electrode. In the source electrode and the drain electrode, the second metal layer having a light transmission thickness, a high refractive index layer, and the first metal layer having a light blocking thickness are stacked. The second metal layer of the source electrode and the drain electrode are disposed to face each other with the second metal layer of the light blocking layer.

For example, the high refractive layer includes at least one of gallium-arsenic (GaAs), germanium (Ge), and silicon.

The thin film transistor substrate according to the present invention includes a gate electrode positioned above and a light shielding layer positioned below the channel region of the semiconductor layer. Accordingly, light flowing into the channel region from the top and bottom of the semiconductor layer can be effectively blocked. In addition, since the gate electrode and the light blocking layer do not overlap each other in a vertical structure with the source-drain electrode, parasitic capacitance can be minimized. In order to maximize the light blocking efficiency, the light blocking layer is formed to have a complex structure, so that the amount of light flowing from the side of the light blocking layer can be reduced. In particular, by forming the light-shielding layer as a triple layer with a material having a high refractive index interposed therebetween, the amount of light reflected from the light-shielding layer can be significantly reduced, and the introduced light can be induced not to reach the channel region. Accordingly, by minimizing the amount of light reflected from the light shielding layer and flowing into the channel region, optical reliability and thermal stability (PBTiS: Positive Bias Temperature Instability and/or NBTiS: Negative Bias Temperature Instability) may be improved.

1 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device, which is a type of horizontal electric field type according to the prior art.
FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line II′.
3 is a plan view showing a structure of one pixel in an active matrix organic light emitting diode display.
FIG. 4 is a cross-sectional view showing the structure of an active matrix organic light emitting diode display taken along line II-II' in FIG. 3;
5 is a cross-sectional view showing a thin film transistor substrate having a top gate structure according to the prior art.
6 is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure further including a light blocking layer according to the first embodiment of the present invention.
7A is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure including a light-shielding layer having an optical waveguide structure according to a second embodiment of the present invention.
7B is a cross-sectional view schematically showing a light path in a light blocking layer of an optical waveguide structure according to a second embodiment of the present invention.
8 is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure including a light-shielding layer having an optical waveguide structure according to a third embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of preparation of the specification, and may be different from the names of parts of an actual product.

The present invention relates to a thin film transistor substrate used in a flat panel display device such as a liquid crystal display device, an organic light emitting diode display device, and an electrophoretic display device, and includes a plurality of pixels constituting a matrix arrangement, and a thin film transistor disposed in each pixel. Includes. In particular, since the present invention relates to a structure of a thin film transistor constituting a thin film transistor substrate of a flat panel display device, the structure of the thin film transistor will be mainly described. Therefore, those skilled in the art can easily apply the thin film transistor substrate according to the present invention to the liquid crystal display device and the organic light emitting diode display device shown in FIGS. 1 to 4.

<First embodiment>

Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 6. The first embodiment of the present invention provides a thin film transistor substrate having a top gate structure further including a light blocking layer LS for blocking light flowing from a lower portion of the substrate SUB. 6 is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure further including a light blocking layer according to the first embodiment of the present invention.

Referring to FIG. 6, the basic configuration is the same as that of FIG. 5. If there is a difference, it has a structure that further includes a light blocking layer LS under the semiconductor layer. In more detail, the light blocking layer LS is formed on the surface of the substrate SUB at a position where the semiconductor layer is to be formed. In particular, it is preferable that the size of the light shielding layer LS is slightly larger so as to completely cover the semiconductor layer.

The buffer layer BUF is coated on the entire surface of the substrate SUB on which the light blocking layer LS is formed. On the buffer layer BUF, a semiconductor layer SE having a size substantially equal to or slightly smaller than the size of the light blocking layer LS is formed so as to overlap the light blocking layer LS. The semiconductor layer SE includes a channel region A at the center, a source region SA disposed to the left of the channel region A, and a drain region DA disposed to the right of the channel region A.

A gate insulating layer GI and a gate electrode G are formed on the channel region A of the semiconductor layer SE. The gate insulating layer GI and the gate electrode G have substantially the same size as the channel region A and have a structure substantially vertically and completely overlapped. The intermediate insulating layer IN is covered on the semiconductor layer SE and the gate electrode G. The intermediate insulating layer IN covering the source region SA and the drain region DA of the semiconductor layer SE is partially removed, so that the source electrode S and the drain electrode D contact each other.

The protective layer PAS covers the entire substrate SUB on which the thin film transistor T including the source electrode S, the channel region A, the gate electrode G, and the drain electrode D is formed. The drain electrode D is exposed by removing a portion of the passivation layer PAS covering the drain electrode D. The exposed drain electrode D is connected to the pixel electrode PXL formed on the passivation layer PAS.

As shown in FIG. 6, in the thin film transistor substrate having a top gate structure further including the light blocking layer LS, parasitic capacitance between the gate electrode G and the source-drain electrode SD hardly occurs, and the substrate ( Light entering from the lower portion of the SUB) is blocked by the light blocking layer LS. Accordingly, the characteristics of the channel region A of the semiconductor layer including the excellent metal oxide are not deteriorated, and can be maintained for a long time.

However, in order for the light blocking layer LS to completely block external light so that light does not flow into the channel region A, it must have a sufficient thickness. For example, in the case of using a metal material such as molybdenum-titanium (MoTi), a sufficient light blocking rate can be secured when it has a thickness of at least 1,000 Å or more. As another example, the light blocking layer LS may be formed of amorphous silicon (a-Si). In this case, even if it has a thickness of 2,500 Å, it cannot completely block light of 550 nm or more.

In this way, even if the light blocking layer LS configured to reflect light without transmitting it is provided, some light may flow into the channel region A. For example, the external light OL enters directly under the light blocking layer LS. Most of the external light OL is reflected by the light blocking layer LS. However, some of the light entering the edge portion of the light blocking layer LS may be introduced into the diffracted light FL due to a diffraction phenomenon at the edge.

In addition, light emitted from the neighboring pixel area may come in from the side direction of the light blocking layer LS. The internal light IL spreads in the lateral direction between the thin film transistor T and the substrate SUB through reflection and re-reflection processes. In this way, the internal light IL and the diffracted light FL may be introduced between the light blocking layer LS and the thin film transistor T. For example, it may flow into the channel region A through reflection and re-reflection between the source-drain electrodes S and D and the light blocking layer LS.

When the light shielding layer LS having a simple structure as in the first embodiment is provided, it is possible to block a significant amount of light that is introduced from the outside, but it cannot block even light that is introduced by diffraction and/or reflection. In the following embodiments, a structure of a light shielding layer capable of effectively preventing light introduced by diffraction of external light and even light introduced by reflection and diffraction of internal light will be described.

<Second Example>

Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 7A and 7B. The second embodiment of the present invention provides a thin film transistor substrate capable of blocking light propagating from neighboring pixels or flowing from a lower portion of the substrate SUB and flowing into the light shielding layer and the thin film transistor through a phenomenon such as diffraction. In particular, there is provided a thin film transistor substrate having a top gate structure including a light-shielding layer having an optical waveguide structure that guides incoming light to a place other than a channel region. 7A is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure including a light-shielding layer having an optical waveguide structure according to a second embodiment of the present invention.

Referring to FIG. 7A, the basic configuration is the same as that of FIG. 6. The difference lies in that the light blocking layer LS disposed under the semiconductor layer SE has a triple layer structure for forming an optical waveguide structure. The triple layer has a structure in which a high refractive layer is interposed between two layers of the same material. For example, a first metal layer M1, a high refractive index layer HR, and a second metal layer M2 may be stacked. Here, the first metal layer M1 and the second metal layer M2 are the same metal material, and are made of any one of molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi). The high refractive layer HR has a higher refractive index than the first and second metal layers M1 and M2 and is made of an insulating material or a metal material capable of securing transparency.

For example, when the first and second metal layers M1 and M2 contain molybdenum, the refractive index is about 3. The high refractive layer HR may be formed of gallium-arsenic (GaAs) having a refractive index of about 3.9, germanium (Ge) having a refractive index of 5.47, or silicon having a refractive index of 3.9.

In the case of having the light blocking layer LS having such a structure, the external light OL flowing into the light blocking layer LS from the bottom is reflected and returned. However, at the boundary of the light blocking layer LS, some light becomes diffracted light FL and flows into the space between the thin film transistor T and the light blocking layer LS.

In addition, side light may be introduced from the side of the light blocking layer LS. The side light may be light introduced from an organic emission layer of a neighboring pixel. Some side light is introduced into the space between the thin film transistor T and the light blocking layer LS by diffraction and/or reflection at the end of the light blocking layer LS. In this way, all of the light flowing between the thin film transistor T and the light blocking layer LS will be described as internal light IL.

The internal light (IL) introduced in this way mainly flows into the channel region (A) through reflection and re-reflection between the metal layer forming the source-drain electrodes (S, D) and the data line (DL) and the light blocking layer (LS). Can be. However, if the light blocking layer LS having an optical waveguide structure as in the second embodiment is provided, the amount of internal light IL flowing into the channel region A can be significantly reduced.

In the light blocking layer LS according to the second embodiment, the first metal layer M1 is formed of molybdenum-titanium (MoTi) to a thickness of 1,000 Å or more. That is, the first metal layer M1 has a thickness capable of reflecting all light incident on the surface without transmitting it. The second metal layer M2 is formed of molybdenum-titanium (MoTi) to a thickness of 100 Å or less. The second metal layer M2 has a thickness capable of transmitting most of the light incident on the surface. In addition, the high refractive layer HR is formed of a material having a refractive index higher than that of molybdenum-titanium, for example, a material such as gallium-arsenic, germanium, or silicon to a thickness of 100 to 500 Å.

Hereinafter, a case where the internal light IL is reflected from the data line DL or the source electrode S and enters the light blocking layer LS will be described with reference to FIG. 7B. 7B is a cross-sectional view schematically illustrating a light path in a light blocking layer of an optical waveguide structure according to a second embodiment of the present invention.

The second metal layer M2 disposed on the light blocking layer LS has a thickness of 100 Å or less, so that light may be transmitted. Accordingly, only a part of the internal light IL introduced from the top of the second metal layer M2 becomes the reflected light 100 reflected from the surface of the second metal layer M2. Most of them are refracted to enter (①) the inside of the second metal layer M2.

Some of the lights (①) entering the second metal layer (M2) are reflected (②) at the interface between the second metal layer (M2) and the high refractive layer (HR), and some are refracted to enter the high refractive layer (HR) ( ③) Do it. Since the refractive index of the high refractive layer HR is higher than that of the second metal layer M2, most of the light enters the high refractive layer HR.

Light (③) entering the high refractive layer (HR) is reflected (④) at the interface between the high refractive layer (HR) and the first metal layer (M1). Since the first metal layer M1 has a thickness of 1,000 Å or more, which is a thickness that does not transmit light, all light is not transmitted and reflected. Among the reflected lights (④), lights satisfying the total reflection condition at the interface between the high refractive layer HR and the second metal layer M2 are reflected (⑤) toward the first metal layer M1 again. Lights that satisfy the total reflection condition continue to advance while repeating reflection through the high refractive layer (HR) (⑤). That is, since the light along the light path ⑤ is guided to the end of the light blocking layer LS and exits, it does not affect the channel region A.

Light that does not satisfy the total reflection condition is refracted (⑥) into the second metal layer M2 and enters. Among the lights (⑥) refracted by the second metal layer (M2), those that satisfy the total reflection condition at the interface between the second metal layer (M2) and the buffer layer (BUF) are reflected (⑦) to the second metal layer (M2). Go back. As described above, some of the lights ⑦ returned to the second metal layer M2 are reflected, and some are refracted to the high refractive layer HR.

Among the lights (⑥) refracted by the second metal layer (M2), those that do not satisfy the total reflection condition are refracted (8) by the buffer layer (BUF) and emitted. In this way, some of the incoming light DL incident on the light blocking layer LS for the first time is reflected by the second metal layer M2, and the rest enters the interior of the light blocking layer LS. Among the lights entering the light blocking layer LS, only a portion (8) of the light is emitted to the buffer layer BUF. That is, the light emitted from the upper surface of the light blocking layer LS is the reflected light 100 and the emitted light ⑧, which have different light paths, and thus some may be canceled out or extinguished by interference.

In addition, most of the light (⑥) refracted by the second metal layer (M2) is totally reflected inside the high refractive layer (HR) or the second metal layer (M2), so that the opposite end of the light blocking layer (LS). Is guided to and exits.

In the first embodiment, the amount of reflected light flows into the channel region as it is, while in the second embodiment, a large amount of light penetrates the interior of the light-shielding layer LS by the light-shielding layer LS having an optical waveguide structure. Exit to the side through. In addition, even if there is reflected light, the intensity of the reflected light is considerably reduced due to the difference in the light path from the transmitted and reflected light.

<Third Example>

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 8. The third embodiment of the present invention provides a thin film transistor substrate capable of further reducing light flowing into the channel region A through reflection and re-reflection between the thin film transistor T and the light blocking layer LS. 8 is a cross-sectional view illustrating a thin film transistor substrate having a top gate structure including a light-shielding layer having an optical waveguide structure according to a third embodiment of the present invention.

The thin film transistor substrate according to the third embodiment has a structure capable of further reducing the amount of internal light IL flowing into the channel region A through reflection and re-reflection. The internal light IL mainly proceeds while repeating reflection and re-reflection between the metal layer including the thin film transistor T and the light shielding layer LS. The light shielding layer according to the second embodiment further includes a high refractive index layer, thereby guiding the incoming light away from the channel region A.

In the third embodiment, an optical waveguide structure such as a light blocking layer is applied to the source-drain electrode and/or the data line to further reduce the amount of light flowing into the channel region. Specifically, in the source-drain element, a second metal layer M2, a high refractive index layer HR, and a first metal layer M1 may be stacked. Here, the first metal layer M1 and the second metal layer M2 are the same metal material, and are made of any one of molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi). The high refractive layer HR has a higher refractive index than the first and second metal layers M1 and M2 and is made of an insulating material or a metal material capable of securing transparency.

For example, when the first and second metal layers M1 and M2 contain molybdenum, the refractive index is about 3. The high refractive layer HR may be formed of gallium-arsenide (GaAs) having a refractive index of about 3.9, germanium (Ge) having a refractive index of 5.47, or silicon having a refractive index of 3.9.

The source-drain element includes source-drain electrodes S and D and a data line DL. The source-drain elements have a stacked structure opposite to the light blocking layer LS. That is, the source-drain elements S, D, and DL and the light blocking layer LS face each other and have a symmetrical stacked structure.

Accordingly, when the internal light IL is reflected from the source-drain element, the same method as the optical path described in the second embodiment is followed. As a result, some of the light incident on the source-drain element is guided in the lateral direction along the high refractive index layer (HR) and the second metal layer (M2) of the source-drain element, and the light path is reflected differently even though other parts are reflected. It becomes the primary reflected light 110 whose intensity is weakened by offset and/or interference with the light.

The primary reflected light 110 whose intensity is weakened is incident on the light blocking layer LS. Light incident on the light blocking layer LS also follows the same method as the light path described above. As a result, some of the light incident on the light blocking layer LS is guided in a lateral direction along the high refractive layer HR and the second metal layer M2 of the light blocking layer LS, and the light path is It becomes the secondary reflected light 200 whose intensity is weaker due to offset and/or interference with the differently reflected light.

The secondary reflected light 200 reflected by the light blocking layer LS is in a state of weaker intensity than the primary reflected light 110 reflected by the source-drain element. That is, in the thin film transistor substrate having the structure according to the third embodiment, the amount of light flowing into the channel region A is only a very fine amount that does not have any effect on the channel region A.

As described above, in the thin film transistor including the light blocking layer and/or the source-drain element according to the second and third embodiments, the amount of light entering the space between the thin film transistor and the light blocking layer by diffraction and/or reflection is significantly reduced. I can. That is, almost no light enters the channel region. As a result, the thin film transistor substrate having the structure according to the present invention can improve the optical reliability and thermal stability of the devices.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the present invention should not be limited to the content described in the detailed description, but should be defined by the claims.

T: thin film transistor SUB: substrate
GL: Gate wiring CL: Common wiring
DL: data wiring PXL: pixel electrode
G: gate electrode SE: semiconductor layer
S: source electrode D: drain electrode
A: (semiconductor) channel area ES: etch stopper
GI: gate insulating film PAS: protective film
PA1: first protective film PA2: second protective film
PAC: planarization film DH: drain contact hole
SL: scan wiring ST: switching thin film transistor
DT: Driving thin film transistor OLE: Organic light emitting diode
SG, DG: gate electrode SS, DS: source electrode
SD, DD: drain electrode SE, DE: etch stopper
CAT: cathode electrode (layer) ANO: anode electrode (layer)
BA: Bank CF: Color filter
OL: (white) organic light emitting layer OC: overcoat layer
PL: planarization film PH: pixel contact hole
SA: source region DA: drain region
Ggs: Gate-source separation Ggd: Gate-drain separation
BUF: buffer layer LS: light-shielding layer
M1: first metal layer M2: second metal layer
HR: high refractive layer

Claims (5)

Board;
A plurality of pixel regions arranged on the substrate in a matrix manner;
A thin film transistor disposed in each of the pixel regions and having a channel region including an oxide semiconductor material;
A light blocking layer interposed between the substrate and the thin film transistor and in which a first metal layer having a light blocking thickness, a high refractive index layer, and a second metal layer having a light transmitting thickness are stacked;
A buffer layer interposed between the light blocking layer and the thin film transistor and covering the entire surface of the substrate; And
A pixel electrode connected to the thin film transistor and disposed in the pixel region,
The thin film transistor,
A gate electrode overlapping the channel region;
A source electrode connected to one side of the channel region; And
A drain electrode connected to the other side of the channel region and connected to the pixel electrode,
The source electrode and the drain electrode,
The second metal layer having the light transmitting thickness, the high refractive layer, and the first metal layer having the light blocking thickness are stacked,
The second metal layer of the source electrode and the drain electrode is disposed to face each other with the second metal layer of the light blocking layer.
The method of claim 1,
The first metal layer,
Contains any one of molybdenum, titanium and molybdenum-titanium, and has a thickness of 1,000 Å or more,
The second metal layer,
It contains the same material as the first metal layer, has a thickness of 100 Å or less,
The high refractive layer,
A thin film transistor substrate comprising a transparent material having a refractive index higher than that of the first and second metal layers, and having a thickness of 100 Å or more to 500 Å or less.
delete delete The method of claim 1,
The high refractive layer is a thin film transistor substrate including at least one of gallium-arsenic (GaAs), germanium (Ge), and silicon.

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