JPH0563196A - Thin film semiconductor device, manufacture thereof and liquid crystal display device - Google Patents

Thin film semiconductor device, manufacture thereof and liquid crystal display device

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Publication number
JPH0563196A
JPH0563196A JP22395391A JP22395391A JPH0563196A JP H0563196 A JPH0563196 A JP H0563196A JP 22395391 A JP22395391 A JP 22395391A JP 22395391 A JP22395391 A JP 22395391A JP H0563196 A JPH0563196 A JP H0563196A
Authority
JP
Japan
Prior art keywords
film
thin film
liquid crystal
region
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22395391A
Other languages
Japanese (ja)
Inventor
Kazuhiro Ogawa
和宏 小川
Kikuo Ono
記久雄 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22395391A priority Critical patent/JPH0563196A/en
Publication of JPH0563196A publication Critical patent/JPH0563196A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To increase a field effect mobility and to decrease an OFF current by forming a channel layer of a two-layer structure of a poly-Si and a hydrogenated amorphous silicon film having a special thickness in a reversely staggered structure thin film transistor. CONSTITUTION:A gate electrode 2 is first formed on a glass substrate, an SiN insulating film 3 is deposited, and a hydrogenated amorphous silicon film (H film) is deposited in thickness of 10 to 40nm. Thereafter, it is irradiated with an excimer laser to modify the H film to a poly-Si film 4. Then, the H film 5 is deposited on the upper part, the Si film of a part for forming a thin film transistor(TFT) having a reversely staggered structure is insularly formed, source/drain electrodes 7 are then formed, and with both the electrodes as masks the n-type silicon film on the part corresponding to a channel is removed. Thus, the TFT having a high mobility and a low OFF current can be formed, and a driving peripheral circuit can be contained in a liquid crystal display substrate or an image processing substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は薄膜半導体装置に係り、
特に液晶表示装置に用いる逆スタガ構造の薄膜トランジ
スタ並びにその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device,
In particular, the present invention relates to a thin film transistor having an inverted stagger structure used for a liquid crystal display device and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来より、逆スタガ構造の薄膜トランジ
スタ(以下TFTと略記)はゲート絶縁膜,半導体薄
膜,高濃度不純物層をプラズマCVD法により順次連続
形成できるため製造工程が容易であり、遮光膜が不要で
あるという利点などから液晶ディスプレイ用アクティブ
マトリクス基板に広く用いられている。図2は逆スタガ
構造a−Si TFTのプロセスフロー及び構造断面図
を示す。このように、プラズマCVD膜(ゲート絶縁
膜,半導体薄膜,高濃度不純物層)を3層連続に形成で
きるため特性のばらつきは小さい。しかし、水素化非晶
質シリコン膜(以下a−Si:H膜と略記)をチャネル
層に使用した場合、電界効果移動度が0.5cm2/V・s
程度と小さいため、液晶表示装置の画素部に用いるには
十分であるが、画素部と同一基板上に前記a−Si T
FTで駆動用周辺回路を構成することは非常に困難であ
る。
2. Description of the Related Art Conventionally, a reverse staggered thin film transistor (hereinafter abbreviated as TFT) has a gate insulating film, a semiconductor thin film, and a high-concentration impurity layer which can be successively formed by a plasma CVD method, so that a manufacturing process is easy and a light-shielding film. It is widely used as an active matrix substrate for liquid crystal displays because of the advantage that it is unnecessary. FIG. 2 shows a process flow and a structural sectional view of an inverted stagger structure a-Si TFT. As described above, the plasma CVD film (gate insulating film, semiconductor thin film, high-concentration impurity layer) can be continuously formed in three layers, so that the characteristic variation is small. However, when a hydrogenated amorphous silicon film (hereinafter abbreviated as a-Si: H film) is used for the channel layer, the field effect mobility is 0.5 cm 2 / V · s.
Since it is small in size, it is sufficient for use in a pixel portion of a liquid crystal display device, but the a-SiT film is formed on the same substrate as the pixel portion.
It is very difficult to configure a driving peripheral circuit with FT.

【0003】そこで、上記問題点を克服するためa−S
i:H膜にレーザビームを照射し、電界効果移動度を向
上させる方法が考えられている。特に発振波長が紫外光
領域であるエキシマレーザはa−Si:H膜に対して吸
収係数が大きく、ガラス基板への熱的影響が小さい。そ
のため、安価な低融点ガラスを使用することができると
ともに、レーザを用いることで局所的な結晶化も可能で
ある。
Therefore, in order to overcome the above problems, aS
A method of irradiating the i: H film with a laser beam to improve the field effect mobility has been considered. In particular, the excimer laser whose oscillation wavelength is in the ultraviolet region has a large absorption coefficient for the a-Si: H film and has a small thermal influence on the glass substrate. Therefore, inexpensive low-melting glass can be used, and local crystallization is also possible by using a laser.

【0004】上記プロセスを利用した従来の多結晶シリ
コン薄膜トランジスタ(以下poly−Si TFTと略
記)の製造方法の一例を以下に示す。
An example of a conventional method of manufacturing a polycrystalline silicon thin film transistor (hereinafter abbreviated as poly-Si TFT) using the above process is shown below.

【0005】ガラス基板上にスパッタ法により形成した
クロム(Cr)やアルミニウム(Al)等でゲート電極
を形成した後、ゲート絶縁膜,a−Si:H膜を順次プ
ラズマCVD法で堆積する。その後、XeClエキシマ
レーザを照射し、前記a−Si:H膜をpoly−Si膜に
変換する。この時の構造断面図を図3に示す。次に、オ
ーミックコンタクト層としてn型シリコン膜をプラズマ
CVD法で堆積し、TFTを形成する部分のSi膜をホ
ト・エッチング工程により島状加工する。その後、スパ
ッタ法により形成したCrやAl等でソース電極,ドレ
イン電極を形成し、両電極をマスクにチャネル部に対応
する部分上のn型シリコン膜をドライエッチング法等で
選択除去する。最後に、全面にパッシペーション膜を被
着形成し、目的のpoly−Si TFTを製造している
(特開平2−130913号公報記載)。
After forming a gate electrode of chromium (Cr), aluminum (Al) or the like formed on a glass substrate by a sputtering method, a gate insulating film and an a-Si: H film are sequentially deposited by a plasma CVD method. After that, XeCl excimer laser is irradiated to convert the a-Si: H film into a poly-Si film. A structural sectional view at this time is shown in FIG. Next, an n-type silicon film is deposited as an ohmic contact layer by the plasma CVD method, and the Si film in the portion where the TFT is formed is processed into an island shape by a photo-etching process. After that, a source electrode and a drain electrode are formed of Cr or Al formed by a sputtering method, and the n-type silicon film on the portion corresponding to the channel portion is selectively removed by a dry etching method or the like using both electrodes as a mask. Finally, a passivation film is deposited on the entire surface to manufacture the target poly-Si TFT.
(Described in JP-A-2-130913).

【0006】上記従来例と異なるものとして、図4に示
すように全面にパッシベーション膜を被着形成した後に
XeClエキシマレーザを照射する方法が考えられてい
る。この方法によれば、従来のa−Si TFTの製造
プロセス完了後にレーザを照射するため、プロセス変更
が最も少ない(特開昭60−245124号公報記載)。
As a method different from the above-mentioned conventional example, a method of irradiating a XeCl excimer laser after depositing a passivation film on the entire surface as shown in FIG. 4 is considered. According to this method, the laser irradiation is performed after the conventional manufacturing process of the a-Si TFT is completed, so that the process is changed the least (described in JP-A-60-245124).

【0007】又、a−Si:H膜にレーザビームを照射
して逆スタガ構造TFTを高移動度化する方法及び構造
として以下のものも考えられる。一般にa−SiTFT
の場合、n型シリコン膜とa−Si:H膜のエッチング
は選択性が小さいため、チャネル層となるa−Si:H
膜をある程度厚くしておく必要がある。しかし、a−S
i:H膜を厚くした場合、エキシマレーザを高エネルギ
ーで照射しても膜全体を結晶化することが困難であり、
実際オン電流が流れるゲート絶縁膜との界面付近の結晶
性向上が不十分となる。そのため、TFTの電界効果移
動度の向上も小さい。そこで、まずa−Si:H膜を薄
く堆積した後、レーザビームを照射して前記a−Si:
H膜をpoly−Si膜に改質し、次に前記poly−Si膜の
上部にa−Si:H膜を堆積する。この様に、チャネル
層をpoly−Siとa−Si:Hの二層構造とすることで
電界効果移動度を向上させ、なおかつn型シリコン膜の
エッチングに裕度を持たせることができる。
Further, as a method and structure for irradiating the a-Si: H film with a laser beam to increase the mobility of the inverted stagger structure TFT, the following can be considered. Generally a-Si TFT
In this case, since the etching of the n-type silicon film and the a-Si: H film has a low selectivity, a-Si: H which will become the channel layer is formed.
It is necessary to make the film thick to some extent. However, a-S
When the i: H film is thickened, it is difficult to crystallize the entire film even if the excimer laser is irradiated with high energy.
In reality, the improvement of crystallinity in the vicinity of the interface with the gate insulating film through which the on-current flows becomes insufficient. Therefore, the improvement of the field effect mobility of the TFT is small. Therefore, first, after thinly depositing an a-Si: H film, a laser beam is irradiated to the a-Si: H film.
The H film is modified into a poly-Si film, and then an a-Si: H film is deposited on the poly-Si film. In this way, by forming the channel layer into a two-layer structure of poly-Si and a-Si: H, it is possible to improve the field effect mobility and to allow the etching of the n-type silicon film to have a margin.

【0008】[0008]

【発明が解決しようとする課題】上記従来技術では、結
晶化するSi膜の膜厚、レーザビームを照射する際のエ
ネルギー、さらにはレーザビームを照射した際のゲート
絶縁膜への加熱の影響等に関して配慮がなされていな
い。
In the above prior art, the film thickness of the Si film to be crystallized, the energy when the laser beam is irradiated, the influence of the heating on the gate insulating film when the laser beam is irradiated, etc. Is not considered.

【0009】TFTが逆スタガ構造であるため、結晶化
するa−Si:H膜が厚い場合には、高エネルギーのレ
ーザビームを照射しても実際にオン電流が流れるゲート
絶縁膜との界面付近の結晶性を向上させるのが困難であ
る。そのため、電界効果移動度を向上させることも困難
となる。しかし、a−Si:H膜の膜厚を100nm以
下にすることで、前記a−Si:H膜全体を結晶化する
ことができる。そのため、SiO2 膜によりゲート絶縁
膜を構成した場合には、上記のように膜厚を制限するこ
とにより電界効果移動度を向上できる。
Since the TFT has an inverted staggered structure, when the a-Si: H film to be crystallized is thick, the vicinity of the interface with the gate insulating film where the on-current actually flows even when the high energy laser beam is irradiated. It is difficult to improve the crystallinity. Therefore, it is difficult to improve the field effect mobility. However, by setting the film thickness of the a-Si: H film to 100 nm or less, the entire a-Si: H film can be crystallized. Therefore, when the gate insulating film is composed of the SiO 2 film, the field effect mobility can be improved by limiting the film thickness as described above.

【0010】しかし、SiN膜でゲート絶縁膜を構成し
た場合には、上記SiO2 膜の場合とは得られるTFT
の特性が異なる。レーザビームをa−Si:H膜に照射
した場合、Si膜は潜熱をもち、この潜熱はa−Si:
H膜の膜厚が厚いほど大きい。従って、a−Si:H膜
の膜厚が厚いほどゲート絶縁膜への加熱の影響は大きく
なる。さらには照射するレーザが高エネルギーであるほ
ど前記影響は大きい。SiO2 膜のように膜中に水素が
含有されていない場合には、上記のような加熱の影響に
よる膜質の劣化は起こらない。しかし、SiN膜のよう
に膜中に多量の水素を含んでいる場合には、この加熱の
影響により前記含有水素が離脱し、膜質が著しく劣化す
る。そのため、TFTを形成した際の電気特性も低下す
る。
However, when the gate insulating film is composed of the SiN film, the TFT obtained is different from the case of the above-mentioned SiO 2 film.
Have different characteristics. When the a-Si: H film is irradiated with a laser beam, the Si film has latent heat, and this latent heat is a-Si:
The thicker the H film, the larger. Therefore, the thicker the a-Si: H film, the greater the influence of heating on the gate insulating film. Further, the higher the energy of the laser to be irradiated, the greater the influence. When hydrogen is not contained in the film like the SiO 2 film, the deterioration of the film quality due to the influence of heating does not occur. However, when a large amount of hydrogen is contained in the film such as the SiN film, the contained hydrogen is released due to the effect of this heating, and the film quality is significantly deteriorated. Therefore, the electrical characteristics when the TFT is formed are also deteriorated.

【0011】又、上記従来技術では、オフ電流(以下I
OFF と略記)や逆方向リーク電流(以下IREV と略記)
について十分に配慮されておらず、最終的に液晶ディス
プレイ用アクティブマトリクス基板に駆動用周辺回路を
内蔵できない問題があった。
Further, in the above-mentioned prior art, the off current (hereinafter I
OFF ) and reverse leakage current (hereinafter abbreviated as I REV )
However, there was a problem that the driving peripheral circuit could not be built in the active matrix substrate for the liquid crystal display finally.

【0012】本発明は、ゲート絶縁膜の膜質を劣化させ
ることなく、電界効果移動度が大きくかつオフ電流が低
いTFTを形成し、最終的には駆動用周辺回路を表示部
と同一基板上に内蔵することを目的とする。
According to the present invention, a TFT having a large field effect mobility and a low off current is formed without deteriorating the film quality of the gate insulating film, and finally the driving peripheral circuit is formed on the same substrate as the display section. Intended to be built-in.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するため
に、本発明では逆スタガ構造TFTを以下の構成とし
た。絶縁性基板上にゲート電極、SiN膜を形成した
後、チャネル層を前記SiN膜と接する側からpoly−S
i,a−Si:Hの二層構造とし、なおかつpoly−Si
の膜厚を10nm以上40nm以下とする逆スタガ構造
TFTである。
In order to achieve the above object, the present invention employs an inverted staggered structure TFT as follows. After forming the gate electrode and the SiN film on the insulative substrate, the channel layer is made of poly-S from the side in contact with the SiN film.
i, a-Si: H has a two-layer structure and poly-Si
The reverse staggered structure TFT has a film thickness of 10 nm or more and 40 nm or less.

【0014】上記目的を達成するために、本発明は逆ス
タガ構造TFTの製造方法を以下のようにした。まず絶
縁性基板上にゲート電極,SiN膜を形成した後、a−
Si:H膜を10nm以上40nm以下の膜厚で堆積す
る。その後、エキシマレーザを130mJ/cm2 以上2
00mJ/cm2 のエネルギーで照射し、前記a−Si:
H膜をpoly−Si膜に変換する。その際の照射雰囲気
は、HeやArなどの不活性ガス中或いは真空中が望ま
しい。前記poly−Si膜形成後、その上部にa−Si:
H膜を堆積し、TFTを形成する部分のSi膜を島状加
工する。次に、ソース・ドレイン電極を形成し、両電極
をマスクにチャネル部に対応する部分上のn型シリコン
膜をドライエッチング法等で選択除去する。最後に、全
面にパッシベーション膜を形成して、目的の高移動度の
TFTを形成する。
In order to achieve the above object, the present invention uses a method of manufacturing an inverted stagger structure TFT as follows. First, after forming a gate electrode and a SiN film on an insulating substrate, a-
A Si: H film is deposited with a film thickness of 10 nm or more and 40 nm or less. After that, use an excimer laser of 130 mJ / cm 2 or more 2
Irradiation with an energy of 00 mJ / cm 2 is carried out, and the a-Si:
The H film is converted into a poly-Si film. The irradiation atmosphere at that time is preferably in an inert gas such as He or Ar or in a vacuum. After forming the poly-Si film, a-Si:
The H film is deposited, and the Si film in the portion forming the TFT is processed into an island shape. Next, source / drain electrodes are formed, and the n-type silicon film on the portion corresponding to the channel portion is selectively removed by a dry etching method or the like using both electrodes as a mask. Finally, a passivation film is formed on the entire surface to form a target high mobility TFT.

【0015】[0015]

【作用】上記のようにして製造した本発明の逆スタガ構
造TFTは、レーザを照射する際のa−Si:H膜の膜
厚が40nm以下であるためSi膜の潜熱が小さく、そ
のためSiN膜への加熱の影響も小さい。一方、a−S
i:H膜の膜厚が40nmを超えると潜熱が大きくな
り、SiN膜が加熱される。そのため、SiN膜中のS
i−H結合が切断され、含有水素が離脱して膜質が著し
く劣化する。この様な状態で形成した場合、電界効果移
動度が小さく、しきい電圧が大きく、オフ電流が高いT
FTとなる。しかし、本発明の手段によりTFTを形成
することで、ゲート絶縁膜の膜厚を劣化させることはな
い。又、結晶化したSi膜の上部にa−Si:H膜を堆
積するためチャネル層を厚くすることができ、n型シリ
コン膜をドライエッチング法等で選択除去する際のプロ
セスの裕度を増すことができる。この様にして形成した
TFTは、ゲート電極に順方向電圧を印加してトランジ
スタをオン状態にした場合、反転層はキャリア移動度の
大きいpoly−Si膜中に形成され、かつスタガ構造であ
るため反転層とソース・ドレインの重なりが大きく、po
ly−Si膜とa−Si:H膜の二層構造でもオン電流が
大きくとれる。なお、poly−Si膜の膜厚は反転層の厚
さよりも厚くする必要があり、さらには成膜の安定性な
どを考慮すると、poly−Si膜の膜厚は10nm以上で
あることが望ましい。
In the inverted stagger structure TFT of the present invention manufactured as described above, the latent heat of the Si film is small because the film thickness of the a-Si: H film is 40 nm or less when the laser is irradiated, and therefore the SiN film is formed. The effect of heating on is small. On the other hand, a-S
When the film thickness of the i: H film exceeds 40 nm, the latent heat becomes large and the SiN film is heated. Therefore, S in the SiN film
The i-H bond is broken, the contained hydrogen is released, and the film quality is significantly deteriorated. When formed in such a state, the field effect mobility is low, the threshold voltage is high, and the off current is high.
It becomes FT. However, forming the TFT by the means of the present invention does not deteriorate the film thickness of the gate insulating film. In addition, since the a-Si: H film is deposited on the crystallized Si film, the channel layer can be thickened, increasing the process margin when selectively removing the n-type silicon film by the dry etching method or the like. be able to. In the TFT thus formed, when a forward voltage is applied to the gate electrode to turn on the transistor, the inversion layer is formed in a poly-Si film having high carrier mobility and has a staggered structure. There is a large overlap between the inversion layer and the source / drain.
A large on-current can be obtained even in the two-layer structure of the ly-Si film and the a-Si: H film. Note that the thickness of the poly-Si film needs to be larger than the thickness of the inversion layer, and further, considering the stability of the film formation, the thickness of the poly-Si film is preferably 10 nm or more.

【0016】又、電界が集中するソース・ドレイン領域
との接合部にa−Si:H膜が存在するため電界が緩和
され、オフ電流や逆方向リーク電流を抑えることができ
る。又、ゲート絶縁膜に接する側のSi層の膜厚を40
nm以下としても、200mJ/cm2 を超えるエネルギ
ーのエキシマレーザを照射した場合には、SiN膜が加
熱され、膜中の含有水素が離脱して膜質が劣化する現象
が起こる。しかし、エキシマレーザの照射エネルギーを
200mJ/cm2 以下とすることで、SiN膜の膜厚を
劣化させることなく、Si膜を結晶化することができ
る。又、130mJ/cm2 以下の照射エネルギーではa
−Si:H膜の結晶化が安定して起こらないため、照射
エネルギーの下限は130mJ/cm2 である。
Further, since the a-Si: H film is present at the junction with the source / drain region where the electric field is concentrated, the electric field is relaxed, and the off current and the reverse leakage current can be suppressed. In addition, the thickness of the Si layer on the side in contact with the gate insulating film is 40
Even if the thickness is less than or equal to nm, when an excimer laser having an energy of more than 200 mJ / cm 2 is irradiated, the SiN film is heated, hydrogen contained in the film is released, and the film quality deteriorates. However, by setting the irradiation energy of the excimer laser to 200 mJ / cm 2 or less, the Si film can be crystallized without degrading the film thickness of the SiN film. Also, when the irradiation energy is 130 mJ / cm 2 or less, a
Since the crystallization of the —Si: H film does not occur stably, the lower limit of the irradiation energy is 130 mJ / cm 2 .

【0017】上記TFT構造及び製造方法により、目的
とする駆動用回路内蔵液晶表示装置が実現できる。
With the above TFT structure and manufacturing method, a target liquid crystal display device with a built-in driving circuit can be realized.

【0018】[0018]

【実施例】以下、本発明の実施例を図面を用いて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

【0019】実施例1 図1は、本発明の構成を示す薄膜トランジスタの構造断
面図である。ガラス基板1上にまずCrによりゲート電
極2を形成した後、ゲート絶縁膜3を堆積する。その
後、a−Si:H膜を10〜80nmの膜厚で各々堆積
し、He雰囲気中でXeClエキシマレーザを200m
J/cm2 のエネルギーで照射した。この時、a−Si:
H膜中の含有水素量が多い場合には、エキシマレーザを
照射するとSi膜が剥離するため、レーザアニールの前
処理として400℃以上で熱処理したり、或いはArレ
ーザ等のエネルギービームを照射してa−Si:H膜中
の含有水素量を制御する必要がある。以上のようにして
エキシマレーザを照射することで、前記a−Si:H膜
はpoly−Si膜4に改質される。次に、Si膜のトータ
ル膜厚が220nmになるように前記poly−Si膜4の
上部にa−Si:H膜5を堆積し、その後n型シリコン
層6を35nm堆積する。次に、TFTを形成する部分
のSi膜をホト・エッチング工程により島状加工した
後、Al等でソース・ドレイン電極7を形成する。両電
極をマスクにチャネル部に対応する部分上のn型シリコ
ン膜をドライエッチング法で除去した後、最後に全面に
パッシベーション膜を被着形成して、目的のTFTが完
成する。図5は、ゲート絶縁膜をSiN膜或いはSiO
2 膜により構成した場合のpoly−Si膜の膜厚と電界効
果移動度との関係を示す。SiO2 膜によりゲート絶縁
膜を構成した場合、poly−Si膜が10〜80nmの範
囲で電界効果移動度20cm2/V・s 程度のTFTが得
られる。しかし、SiN膜によりゲート絶縁膜を構成し
た場合、poly−Si膜の膜厚が40nmを超えると、電
界効果移動度が著しく低下する。この様にSiN膜をゲ
ート絶縁膜に使用した場合には、poly−Si膜の膜厚を
40nm以下にする必要があるが、前記のように膜厚を
制限することによりSiO2 膜をゲート絶縁膜に用いた
場合と同様に電界効果移動度20cm2/V・s のTF
Tを形成することができる。
Example 1 FIG. 1 is a structural sectional view of a thin film transistor showing the constitution of the present invention. First, the gate electrode 2 is formed of Cr on the glass substrate 1, and then the gate insulating film 3 is deposited. After that, an a-Si: H film is deposited with a film thickness of 10 to 80 nm, and a XeCl excimer laser is set to 200 m in a He atmosphere.
Irradiation was performed with an energy of J / cm 2 . At this time, a-Si:
If the H film contains a large amount of hydrogen, the Si film is peeled off by irradiation with an excimer laser. Therefore, heat treatment is performed at 400 ° C. or higher as a pretreatment for laser annealing, or irradiation with an energy beam such as an Ar laser is performed. It is necessary to control the amount of hydrogen contained in the a-Si: H film. By irradiating the excimer laser as described above, the a-Si: H film is modified into the poly-Si film 4. Next, an a-Si: H film 5 is deposited on the poly-Si film 4 so that the total film thickness of the Si film is 220 nm, and then an n-type silicon layer 6 is deposited to 35 nm. Next, the Si film in the portion for forming the TFT is processed into an island shape by a photo-etching process, and then the source / drain electrodes 7 are formed of Al or the like. The n-type silicon film on the portion corresponding to the channel portion is removed by dry etching using both electrodes as a mask, and finally, a passivation film is deposited on the entire surface to complete the target TFT. In FIG. 5, the gate insulating film is a SiN film or SiO.
The relationship between the film thickness of the poly-Si film and the field effect mobility in the case of being composed of two films is shown. When the gate insulating film is composed of the SiO 2 film, a TFT having a field effect mobility of about 20 cm 2 / V · s can be obtained in the range of 10 to 80 nm for the poly-Si film. However, when the gate insulating film is made of the SiN film and the film thickness of the poly-Si film exceeds 40 nm, the field effect mobility remarkably decreases. When the SiN film is used as the gate insulating film as described above, the film thickness of the poly-Si film needs to be 40 nm or less. However, by limiting the film thickness as described above, the SiO 2 film is used as the gate insulating film. TF with a field effect mobility of 20 cm 2 / V · s as in the case of using the film
T can be formed.

【0020】実施例2 次に、a−Si:H膜に照射するエキシマレーザのエネ
ルギーを変えた場合について以下に示す。ガラス基板上
にスパッタ法によりCrを120nm堆積し、ホト・エ
ッチング工程によりゲート電極を形成する。次に、プラ
ズマCVD法によりSiN膜、a−Si:H膜を各々3
50nm,30nm堆積する。その後、エキシマレーザ
を照射する前処理として400℃15分間窒素雰囲気中
で熱処理を行い、a−Si:H膜中の含有水素量を減少
させる。この前処理は、Arレーザ等のエネルギービー
ムを照射しても良い。次に、エキシマレーザを100〜
250mJ/cm2 のエネルギーで照射し、前記a−S
i:H膜をpoly−Si膜4に改質する。その後、プラズ
マCVD法によりa−Si:H膜5、n型シリコン膜6
を各々190nm,35nm堆積し、TFTを形成する
部分のSi膜をホト・エッチング工程により島状加工す
る。次に、スパッタ法により形成したAlでソース・ド
レイン電極と形成した後、両電極をマスクにチャネル部
に対応する部分上のn型シリコン膜をドライエッチング
法等で選択除去する。最後に、全面にパッシベーション
膜を形成してTFTが完成する。この様にして形成した
TFTの電界効果移動度とエキシマレーザの照射エネル
ギーとの関係を図6に示す。エキシマレーザの照射エネ
ルギーが130mJ/cm2以下ではa−Si:H膜が結
晶化せず、電界効果移動度の向上は見られない。又、エ
キシマレーザの照射エネルギーが200mJ/cm2 を超
えるとSiN膜中の水素が昇温により離脱するため、電
界効果移動度が著しく低下する。又、オフ電流も電界効
果移動度の低下と共に増加している。しかし、エキシマ
レーザの照射エネルギーを130〜200mJ/cm2
することで電界効果移動度20cm2/V・s 、オフ電流
2pAのTFTをばらつきなく製造することができた。
Example 2 Next, the case where the energy of the excimer laser for irradiating the a-Si: H film was changed will be described below. Cr is deposited to a thickness of 120 nm on a glass substrate by a sputtering method, and a gate electrode is formed by a photo-etching process. Next, a SiN film and an a-Si: H film are each formed by plasma CVD to form 3 films each.
Deposit 50 nm and 30 nm. Then, heat treatment is performed in a nitrogen atmosphere at 400 ° C. for 15 minutes as a pretreatment for irradiating the excimer laser to reduce the amount of hydrogen contained in the a-Si: H film. In this pretreatment, an energy beam such as an Ar laser may be irradiated. Next, the excimer laser 100-
Irradiation with an energy of 250 mJ / cm 2
The i: H film is modified into the poly-Si film 4. After that, the a-Si: H film 5 and the n-type silicon film 6 are formed by the plasma CVD method.
Of 190 nm and 35 nm respectively are deposited, and the Si film of the portion forming the TFT is processed into an island shape by a photo-etching process. Next, after forming a source / drain electrode with Al formed by a sputtering method, the n-type silicon film on a portion corresponding to the channel portion is selectively removed by a dry etching method or the like using both electrodes as a mask. Finally, a passivation film is formed on the entire surface to complete the TFT. The relationship between the field effect mobility of the TFT thus formed and the irradiation energy of the excimer laser is shown in FIG. When the irradiation energy of the excimer laser is 130 mJ / cm 2 or less, the a-Si: H film is not crystallized and the field effect mobility is not improved. Further, when the irradiation energy of the excimer laser exceeds 200 mJ / cm 2 , hydrogen in the SiN film is released due to the temperature rise, so that the field effect mobility is significantly reduced. Further, the off-current also increases as the field effect mobility decreases. However, by setting the irradiation energy of the excimer laser to 130 to 200 mJ / cm 2 , a TFT having a field effect mobility of 20 cm 2 / Vs and an off current of 2 pA could be manufactured without variation.

【0021】実施例3 次に、ゲート絶縁膜を陽極酸化膜とSiN膜の二層構造
にした場合の実施例を図7を用いて説明する。
Embodiment 3 Next, an embodiment in which the gate insulating film has a two-layer structure of an anodic oxide film and a SiN film will be described with reference to FIG.

【0022】ガラス基板1上にAl膜10をスパッタ法
により圧力54μPa、パワー2.1kW、基板温度10
0℃の条件で250nm堆積する。ホト・エッチング工
程によりゲート電極パターンを形成した後、Alの表面
を陽極化成する。この時形成するAl23膜11の膜厚
は200nmとする。その後、プラズマCVD法により
SiN膜3を圧力0.6Torr、パワー60W、基板温度
350℃、ガス流量SiH48sccm NH348sccmN2
160sccmの条件で200nm、a−Si:H膜を圧力
0.6Torr、パワー40W、基板温度300℃、ガス流
量SiH414sccm H240sccmの条件で30nm連続
形成した後、Arレーザを出力6.0W、ビーム径2.0
mmφ、走査速度3.0mm/sの条件で、TFTを形成す
る部分上のa−Si:H膜に照射する。これにより、a
−Si:H膜中の水素量を減少させ、マキシマレーザを
照射した時の膜剥がれを防止する。Arレーザを照射し
た後、XeClエキシマレーザを170mJ/cm2 のエ
ネルギーで照射して前記a−Si:H膜をpoly−Si膜
4に改質する。次に、プラズマCVD法でa−Si:H
膜5を前記a−Si:H膜と同条件で190nm、n型
シリコン膜6を圧力0.6Torr、パワー40W、基板温
度250℃、ガス流量SiH420sccm PH320sccm
2 50sccmの条件で35nm連続形成する。その
後、Si膜をホト・エッチング工程により島状加工した
後、Cr膜12,Al膜10をスパッタ法によりゲート
Al膜と同条件で各々60nm,400nm形成し、ソ
ース・ドレイン電極にパターニングする。両電極をマス
クにチャネル部に対応する部分上のn型シリコン膜をド
ライエッチング法で選択除去した後、全面にパッシベー
ション膜8を1μm形成して目的のTFTが完成する。
これにより、電界効果移動度20cm2/Vs、しきい電
圧2V、オフ電流2pA(W/L=10)のTFTが形
成できた。又、陽極化成後にエキシマレーザ等のエネル
ギービームを照射することでSiN膜との密着性が向上
し、TFT特性のばらつきが一層小さくなる。
An Al film 10 is sputtered on the glass substrate 1 to have a pressure of 54 μPa, a power of 2.1 kW and a substrate temperature of 10.
250 nm is deposited under the condition of 0 ° C. After forming a gate electrode pattern by a photo-etching process, the surface of Al is anodized. The film thickness of the Al 2 O 3 film 11 formed at this time is 200 nm. After that, the SiN film 3 is formed by plasma CVD at a pressure of 0.6 Torr, a power of 60 W, a substrate temperature of 350 ° C., and a gas flow rate of SiH 4 8 sccm NH 3 48 sccm N 2.
An a-Si: H film having a thickness of 160 nm, a pressure of 0.6 Torr, a power of 40 W, a substrate temperature of 300 ° C., and a gas flow rate of SiH 4 14 sccm H 2 40 sccm are continuously formed for 30 nm, and then an Ar laser is output at 6.0 W. , Beam diameter 2.0
Irradiation is performed on the a-Si: H film on the part where the TFT is formed under the conditions of mmφ and scanning speed of 3.0 mm / s. This gives a
-Reduce the amount of hydrogen in the Si: H film and prevent the film from peeling off when irradiated with a maximer laser. After irradiating with Ar laser, XeCl excimer laser is irradiated with energy of 170 mJ / cm 2 to modify the a-Si: H film into poly-Si film 4. Next, a-Si: H is formed by a plasma CVD method.
The film 5 is 190 nm under the same conditions as the a-Si: H film, the n-type silicon film 6 is pressure 0.6 Torr, power 40 W, substrate temperature 250 ° C., gas flow rate SiH 4 20 sccm PH 3 20 sccm.
35 nm is continuously formed under the condition of H 2 50 sccm. After that, the Si film is processed into an island shape by a photo-etching process, and then a Cr film 12 and an Al film 10 are formed by a sputtering method under the same conditions as the gate Al film to have a thickness of 60 nm and 400 nm, respectively, and are patterned into source / drain electrodes. The n-type silicon film on the portion corresponding to the channel portion is selectively removed by dry etching using both electrodes as a mask, and then a passivation film 8 of 1 μm is formed on the entire surface to complete the target TFT.
As a result, a TFT having a field effect mobility of 20 cm 2 / Vs, a threshold voltage of 2 V and an off current of 2 pA (W / L = 10) could be formed. Further, by irradiating an energy beam such as an excimer laser after anodizing, the adhesion with the SiN film is improved, and the variation in TFT characteristics is further reduced.

【0023】実施例4 図8は本発明の一実施例を示すものであり、駆動用周辺
回路内蔵型アクティブマトリクス基板の概略図である。
本実施例は、表示部100が対角10インチで表示部を
駆動するための周辺回路101を内蔵したビデオディス
プレイターミナル(以下、VDTと略記)を実現する場
合のものである。この場合は、表示部100の画素数は
480×640×(3)であり、表示部100に用いる
TFTは通常の逆スタガ構造a−Si TFTで、周辺
回路部に用いるTFTはチャネル領域がpoly−Si膜と
a−Si:H膜の二層構造である。
Embodiment 4 FIG. 8 shows an embodiment of the present invention and is a schematic view of an active matrix substrate with a built-in driving peripheral circuit.
In the present embodiment, the display unit 100 realizes a video display terminal (hereinafter abbreviated as VDT) including a peripheral circuit 101 for driving the display unit with a diagonal of 10 inches. In this case, the number of pixels of the display unit 100 is 480 × 640 × (3), the TFT used in the display unit 100 is a normal a-Si TFT having an inverted stagger structure, and the TFT used in the peripheral circuit unit has a poly-channel region. It has a two-layer structure of an -Si film and an a-Si: H film.

【0024】まず、対角12インチのガラス基板上にス
パッタ法によりゲート電極としてCr膜を120nm堆
積する。Cr膜をホト・エッチング工程によりパターニ
ングした後、プラズマCVD法によりSiN膜3を35
0nm、a−Si:H膜を30nm順次連続形成する。
ここで、基板上の駆動用周辺回路を形成する部分にHe
雰囲気中でXeClエキシマレーザを170mJ/cm2
のエネルギーで照射して、a−Si:H膜をpoly−Si
膜4に変換する。続いて、プラズマCVD法によりa−
Si:H膜5を190nm堆積する。これにより、周辺
回路部はa−Si:H(190nm)/poly−Si(3
0nm)の二層構造で、画素部100はa−Si:H
(220nm)の単層構造が得られる。各々の断面構造
図を図9に示す。次に、プラズマCVD法によりn型シ
リコン層を35nm堆積し、ホト・エッチング工程によ
りSi膜を島状加工した後、透明電極であるITOをス
パッタ法で堆積し、ホト・エッチング工程によりパター
ニングする。その後、スパッタ法でCr膜,Al膜を各
々60nm,400nm堆積し、ホト・エッチング工程
によりソース・ドレイン電極を形成する。両電極をマス
クにしてチャネル部に対応する部分上のn型シリコン膜
をドライエッチング法で選択除去した後、全面にパッシ
ベーション膜を形成すると目的の液晶ディスプレイ用ア
クティブマトリクス基板が完成する。前記アクティブマ
トリクス基板に備えられたTFTの特性は、周辺回路部
において電界効果移動度:20cm2/Vs ,しきい値電
圧:2V,オフ電流:2pA,逆方向リーク電流:3p
A(W/L=10)、画素部においては電界効果移動
度:0.4cm2/Vs ,しきい値電圧:1.5V,オフ電
流:1pA(W/L=10)が得られる。一方、他の1
2インチのガラス基板上に偏光板,カラーフィルタ,透
明電極を形成し、前記アクティブマトリクス基板との間
に液晶を封入すると、10インチサイズのVDT用液晶
表示装置が完成する。
First, a Cr film having a thickness of 120 nm is deposited as a gate electrode on a 12-inch diagonal glass substrate by a sputtering method. After patterning the Cr film by the photo-etching process, the SiN film 3 is formed by the plasma CVD method.
A 0-nm a-Si: H film is successively formed in a thickness of 30 nm.
Here, He is formed on a portion of the substrate where the driving peripheral circuit is formed.
170 mJ / cm 2 of XeCl excimer laser in the atmosphere
Irradiation of the a-Si: H film to poly-Si
Convert to Membrane 4. Then, a-
The Si: H film 5 is deposited to a thickness of 190 nm. As a result, the peripheral circuit section has a-Si: H (190 nm) / poly-Si (3
The pixel portion 100 is a-Si: H.
A single layer structure of (220 nm) is obtained. The cross-sectional structure diagram of each is shown in FIG. Next, an n-type silicon layer is deposited to a thickness of 35 nm by the plasma CVD method, the Si film is processed into an island shape by a photo-etching step, ITO that is a transparent electrode is deposited by the sputtering method, and patterning is performed by the photo-etching step. Thereafter, a Cr film and an Al film are deposited by sputtering to 60 nm and 400 nm, respectively, and a source / drain electrode is formed by a photo-etching process. After selectively removing the n-type silicon film on the portion corresponding to the channel portion by a dry etching method using both electrodes as a mask, a passivation film is formed on the entire surface to complete the intended active matrix substrate for liquid crystal display. The characteristics of the TFT provided on the active matrix substrate are as follows: field effect mobility in the peripheral circuit part: 20 cm 2 / Vs, threshold voltage: 2 V, off current: 2 pA, reverse leakage current: 3 p
A (W / L = 10), field effect mobility in the pixel portion: 0.4 cm 2 / Vs, threshold voltage: 1.5 V, off current: 1 pA (W / L = 10). On the other hand, the other one
A polarizing plate, a color filter, and a transparent electrode are formed on a 2-inch glass substrate, and liquid crystal is sealed between the active matrix substrate and the active matrix substrate to complete a 10-inch size VDT liquid crystal display device.

【0025】[0025]

【発明の効果】本発明によれば、ゲート絶縁膜の膜質を
劣化させることなく、前記ゲート絶縁膜の上部に形成し
たa−Si:H膜にレーザビームを照射してpoly−Si
膜に変換することができる効果があり、高移動度かつ低
オフ電流のTFTを形成することができる。又、最終的
には駆動用周辺回路を液晶表示基板や画像処理基板に内
蔵できる効果がある。
According to the present invention, the a-Si: H film formed on the gate insulating film is irradiated with a laser beam without deteriorating the film quality of the gate insulating film and poly-Si.
There is an effect that it can be converted into a film, and a TFT having high mobility and low off-current can be formed. Further, finally, there is an effect that the driving peripheral circuit can be built in the liquid crystal display substrate or the image processing substrate.

【図面の簡単な説明】[Brief description of drawings]

【図1】二層構造TFTの断面図である。FIG. 1 is a cross-sectional view of a two-layer structure TFT.

【図2】a−Si TFTのプロセスフロー図である。FIG. 2 is a process flow diagram of an a-Si TFT.

【図3】従来技術のレーザアニール時の断面構造図であ
る。
FIG. 3 is a cross-sectional structure diagram at the time of laser annealing of a conventional technique.

【図4】従来技術のレーザアニール時の断面構造図であ
る。
FIG. 4 is a cross-sectional structural diagram at the time of laser annealing of a conventional technique.

【図5】ゲート絶縁膜とTFT特性の関係図である。FIG. 5 is a relationship diagram between a gate insulating film and TFT characteristics.

【図6】レーザ照射エネルギーと電界効果移動度の関係
図である。
FIG. 6 is a relationship diagram between laser irradiation energy and field effect mobility.

【図7】二層構造TFTの断面構造である。FIG. 7 is a cross-sectional structure of a two-layer structure TFT.

【図8】駆動用周辺回路内蔵型アクティブマトリクス基
板を示す図である。
FIG. 8 is a diagram showing an active matrix substrate with built-in driving peripheral circuits.

【図9】画素部及び回路部のTFT構造図である。FIG. 9 is a TFT structure diagram of a pixel portion and a circuit portion.

【符号の説明】[Explanation of symbols]

1…ガラス基板、2…ゲート電極、3…ゲート絶縁膜、
4…多結晶シリコン膜、5…水素化非晶質シリコン膜、
6…n型シリコン膜、7…ソース・ドレイン電極、8…
パッシベーション膜、10…アルミニウム膜、11…ア
ルミナ膜、12…クロム膜、100…液晶表示装置画素
部、101…液晶表示装置駆動用周辺回路部。
1 ... Glass substrate, 2 ... Gate electrode, 3 ... Gate insulating film,
4 ... Polycrystalline silicon film, 5 ... Hydrogenated amorphous silicon film,
6 ... N-type silicon film, 7 ... Source / drain electrodes, 8 ...
Passivation film, 10 ... Aluminum film, 11 ... Alumina film, 12 ... Chrome film, 100 ... Liquid crystal display device pixel portion, 101 ... Liquid crystal display device driving peripheral circuit portion.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板上にゲート電極,ゲート絶縁
膜,チャンネル領域,ソース領域,ドレイン領域を備え
た逆スタガ構造の薄膜半導体装置において、前記チャネ
ル領域をゲート絶縁膜と接する側から多結晶シリコン,
非晶質シリコンの順で二層構造とし、かつ前記多結晶シ
リコンの膜厚が10nm以上40nm以下であることを
特徴とする薄膜半導体装置。
1. A reverse staggered thin film semiconductor device having a gate electrode, a gate insulating film, a channel region, a source region, and a drain region on an insulating substrate, wherein the channel region is polycrystalline from the side in contact with the gate insulating film. silicon,
A thin film semiconductor device having a two-layer structure of amorphous silicon in this order, and the film thickness of the polycrystalline silicon is 10 nm or more and 40 nm or less.
【請求項2】請求項1において、ゲート絶縁膜の少なく
ともチャネル領域に接する側が窒化シリコンで構成され
ていることを特徴とする薄膜半導体装置。
2. A thin film semiconductor device according to claim 1, wherein at least a side of the gate insulating film which is in contact with the channel region is made of silicon nitride.
【請求項3】絶縁性基板上にゲート電極,ゲート絶縁
膜,チャネル領域,ソース領域,ドレイン領域を備えた
逆スタガ構造の薄膜半導体装置の製造方法において、ゲ
ート電極及びゲート絶縁膜を形成した後、膜厚が10n
m以上40nm以下の多結晶シリコン層を堆積し、次
に、非晶質シリコン層を堆積し、ソース領域,ドレイン
領域を形成することを特徴とする薄膜半導体装置の製造
方法。
3. A method of manufacturing a thin film semiconductor device having an inverted stagger structure, comprising a gate electrode, a gate insulating film, a channel region, a source region, and a drain region on an insulating substrate, after forming the gate electrode and the gate insulating film. , Film thickness is 10n
A method for manufacturing a thin film semiconductor device, comprising depositing a polycrystalline silicon layer having a thickness of m or more and 40 nm or less, and then depositing an amorphous silicon layer to form a source region and a drain region.
【請求項4】請求項3において、前記ゲート絶縁膜を形
成した後、非晶質シリコン層を堆積し、レーザなどのエ
ネルギービームにより前記非晶質シリコン層を多結晶シ
リコン層に変換することを特徴とする薄膜半導体装置の
製造方法。
4. The method according to claim 3, wherein after forming the gate insulating film, an amorphous silicon layer is deposited, and the amorphous silicon layer is converted into a polycrystalline silicon layer by an energy beam such as a laser. A method of manufacturing a thin-film semiconductor device characterized.
【請求項5】請求項4において、ゲート絶縁膜の少なく
ともチャネル領域に接する側を窒化シリコンで構成する
ことを特徴とする薄膜半導体装置の製造方法。
5. A method of manufacturing a thin film semiconductor device according to claim 4, wherein at least a side of the gate insulating film in contact with the channel region is made of silicon nitride.
【請求項6】透明絶縁性基板間に液晶を封入し、前記透
明絶縁性基板の一方に薄膜トランジスタをスイッチング
素子として備えた液晶表示装置において、表示部となる
画素領域と画素を駆動する周辺回路領域との少なくとも
一方に、絶縁性基板上にゲート電極,ゲート絶縁膜,チ
ャネル領域,ソース領域,ドレイン領域を備えた逆スタ
ガ構造であり、前記ゲート絶縁膜の少なくともチャネル
領域に接する側を窒化シリコンにより構成し、かつ前記
チャネル領域がゲート絶縁膜と接する側から多結晶シリ
コン,非晶質シリコンの順で二層構造を成し、かつ前記
多結晶シリコンの膜厚が10nm以上40nm以下であ
る薄膜トランジスタを用いたことを特徴とする液晶表示
装置。
6. A liquid crystal display device in which a liquid crystal is sealed between transparent insulating substrates, and a thin film transistor is provided as a switching element on one side of the transparent insulating substrate, in a pixel region serving as a display portion and a peripheral circuit region for driving the pixels. And an inverted staggered structure having a gate electrode, a gate insulating film, a channel region, a source region, and a drain region on an insulating substrate, and at least one side of the gate insulating film in contact with the channel region is made of silicon nitride. A thin film transistor having a double-layered structure, in which polycrystalline silicon and amorphous silicon are formed in this order from the side where the channel region contacts the gate insulating film, and the polycrystalline silicon has a film thickness of 10 nm or more and 40 nm or less. A liquid crystal display device characterized by being used.
【請求項7】透明絶縁性基板間に液晶を封入し、前記透
明絶縁性基板の一方に薄膜トランジスタをスイッチング
素子として備えた液晶表示装置において、絶縁性基板上
にゲート電極,窒化シリコン膜を堆積した後、膜厚が1
0nm以上40nm以下の非晶質シリコン層を堆積し、
表示部となる画素領域と画素を駆動する周辺回路領域と
の少なくとも一方に、レーザなどのエネルギービームを
照射して前記非晶質シリコン層を多結晶シリコン層に変
換した後、非晶質シリコン層を形成し、次に、ソース領
域,ドレイン領域を形成することを特徴とする液晶表示
装置の製造方法。
7. A liquid crystal display device in which liquid crystal is sealed between transparent insulating substrates, and a thin film transistor is provided as a switching element on one side of the transparent insulating substrate, a gate electrode and a silicon nitride film are deposited on the insulating substrate. After that, the film thickness is 1
Deposit an amorphous silicon layer of 0 nm or more and 40 nm or less,
At least one of a pixel region which becomes a display portion and a peripheral circuit region which drives a pixel is irradiated with an energy beam such as a laser to convert the amorphous silicon layer into a polycrystalline silicon layer, and then the amorphous silicon layer. And a source region and a drain region are formed next, and a method for manufacturing a liquid crystal display device.
【請求項8】透明絶縁性基板間に液晶を封入し、前記透
明絶縁性基板の一方に薄膜トランジスタをスイッチング
素子として備えた液晶表示装置において、絶縁性基板上
にゲート電極を形成し、前記ゲート電極の一部を陽極化
成した後、窒化シリコン膜を堆積し、次に膜厚が10n
m以上40nm以下の非晶質シリコン層を堆積し、表示
部となる画素領域と画素を駆動する周辺回路領域との少
なくとも一方に、レーザなどのエネルギービームを照射
して前記非晶質シリコン層を多結晶シリコン層に変換し
た後、非晶質シリコン層を形成し、次に、ソース領域,
ドレイン領域を形成することを特徴とする液晶表示装置
の製造方法。
8. A liquid crystal display device in which liquid crystal is sealed between transparent insulating substrates, and a thin film transistor is provided as a switching element on one side of the transparent insulating substrate, a gate electrode is formed on the insulating substrate, and the gate electrode is formed. Is anodized, a silicon nitride film is deposited, and then the film thickness is 10n.
An amorphous silicon layer having a thickness of m or more and 40 nm or less is deposited, and at least one of a pixel region serving as a display portion and a peripheral circuit region for driving the pixel is irradiated with an energy beam such as a laser to form the amorphous silicon layer. After converting to a polycrystalline silicon layer, an amorphous silicon layer is formed, and then a source region,
A method of manufacturing a liquid crystal display device, which comprises forming a drain region.
【請求項9】請求項5または7において、前記エネルギ
ービームがエキシマレーザであることを特徴とする薄膜
半導体装置の製造方法。
9. The method of manufacturing a thin film semiconductor device according to claim 5, wherein the energy beam is an excimer laser.
【請求項10】請求項9において、前記エキシマレーザ
の照射エネルギーが130mJ/cm以上200m
J/cm以下であることを特徴とする薄膜半導体装
置の製造方法。
10. The irradiation energy of the excimer laser according to claim 9, wherein the irradiation energy is 130 mJ / cm 2 or more and 200 m.
A method for manufacturing a thin film semiconductor device, wherein the method is J / cm 2 or less.
【請求項11】請求項4において、ゲート絶縁膜がゲー
ト電極の一部を陽極化成した膜と窒化シリコン膜の二層
構造であり、かつ前記陽極化成膜形成後にレーザビーム
を照射することを特徴とする薄膜半導体装置の製造方
法。
11. The method according to claim 4, wherein the gate insulating film has a two-layer structure of a film in which a part of the gate electrode is anodized and a silicon nitride film, and a laser beam is irradiated after forming the anodized film. A method of manufacturing a thin-film semiconductor device characterized.
JP22395391A 1991-09-04 1991-09-04 Thin film semiconductor device, manufacture thereof and liquid crystal display device Pending JPH0563196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22395391A JPH0563196A (en) 1991-09-04 1991-09-04 Thin film semiconductor device, manufacture thereof and liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0563196A true JPH0563196A (en) 1993-03-12

Family

ID=16806287

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Country Status (1)

Country Link
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