KR20080047773A - Poly silicon thin film transistor substrate and manufacturing method thereof - Google Patents

Abstract

A poly-silicon TFT(Thin Film Transistor) substrate and a manufacturing method thereof are provided to form an etch stopper and an active pattern by using a mask, thereby simplifying the manufacturing process. A poly-silicon TFT(110) includes a gate electrode, a source electrode and a drain electrode. An active pattern is overlapped with the gate electrode and formed at the inside of the gate electrode. The poly-silicon TFT is used a switching device. An etch stopper(126) is overlapped with the active pattern and formed at the inside of the active pattern and protects the active pattern of the poly-silicon TFT. The etch stopper has a structure for exposing the edge of the active pattern as a circumference shape. The difference between the width of the active pattern of the poly-silicon TFT and the width of the etch stopper is the same as that between the length of the active pattern and the length of the etch stopper.

Description

POLY SILICON THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

1 is a plan view illustrating a conventional polysilicon thin film transistor substrate.

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

3 is a plan view illustrating a polysilicon thin film transistor substrate according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3.

5A to 5K are cross-sectional views for describing a first embodiment of the method for manufacturing the polysilicon thin film transistor substrate illustrated in FIG. 3.

6A to 6F are cross-sectional views for describing a second embodiment of the method for manufacturing the polysilicon thin film transistor substrate illustrated in FIG. 3.

{Description of symbols for main parts of the drawing}

110: polysilicon thin film transistor substrate 112: substrate

114: polysilicon thin film transistor 116: gate electrode

118: source electrode 120: drain electrode

122: active pattern 124: ohmic contact pattern

126: etch stopper 128: gate line

130: data line 132: pixel electrode

134: gate insulating film 136: protective film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a polysilicon thin film transistor substrate used in a flat panel display and a manufacturing method thereof.

Flat panel displays (FPDs), such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs), are switching devices for driving an active matrix (AM). And a thin film transistor substrate on which a thin film transistor (TFT) is formed. Here, any one of an amorphous silicon (a-Si) thin film transistor and a polysilicon (p-Si) thin film transistor is used as the thin film transistor.

The active pattern forming the channel of the amorphous silicon thin film transistor is formed of an amorphous silicon material. The active pattern has weak Si-Si bonds and dangling bonds due to disordered arrangement of silicon atoms. For this reason, since the active pattern is changed to a quasi-stable state when light irradiation or an electric field is applied, it may be a problem in terms of stability.

On the other hand, the active pattern forming the channel of the polysilicon thin film transistor is formed of a polysilicon material. The active pattern has a considerably higher mobility compared to an active pattern having an amorphous silicon material. For this reason, the polysilicon thin film transistor has an advantage that the device can be highly integrated. A polysilicon thin film transistor substrate having such a polysilicon thin film transistor will be described in detail with reference to FIGS. 1 and 2.

1 is a plan view illustrating a conventional polysilicon thin film transistor substrate, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

1 and 2, the conventional polysilicon thin film transistor substrate 10 includes a polysilicon thin film transistor 14 formed on the substrate 12. In addition, the polysilicon thin film transistor substrate 10 further includes a gate line 28, a data line 30, and a pixel electrode 32 formed on the substrate 12.

The polysilicon thin film transistor 14 is used as a switching element. To this end, the polysilicon thin film transistor 14 includes a gate electrode 16, a source electrode 18, a drain electrode 20, an active pattern 22, and an ohmic contact pattern 24. Here, the gate electrode 16 overlaps the source electrode 18 and the drain electrode 20 with the gate insulating film 34 interposed therebetween.

The gate line 28 provides the gate electrode 16 with a gate voltage provided from a gate driver connected to one side of the gate line 28.

The data line 30 provides the source electrode 18 with a data voltage provided from a data driver connected to one side of the data line 30.

The pixel electrode 32 receives a data voltage provided from the source electrode 18 to the drain electrode 20 via the active pattern 22. Here, the pixel electrode 32 is connected to the drain electrode 20 through the contact hole 38 penetrating through the passivation layer 36.

In the conventional polysilicon thin film transistor substrate 10 having the above configuration, the back channel portion of the active pattern 22 forming the channel is damaged during etching of the ohmic contact layer in which the ohmic contact pattern 24 is to be formed. Can be. That is, the active pattern 22 may be formed in a form in which the back channel portion of the active pattern 22 is etched.

For this reason, there is a problem in that the active pattern 22 needs to be formed very thick to secure the etching process margin. As a result, the crystallinity of the amorphous silicon layer on which the active pattern 22 is to be formed may be reduced, and device characteristics of the polysilicon thin film transistor 14 such as mobility and sub-threshold may be degraded. There is a problem that can be.

In addition, since the width of the active pattern 22 is generally larger than the width of the gate electrode 16 to secure a process margin, leakage due to light provided from the backlight unit disposed on the rear surface of the polysilicon thin film transistor substrate 10. There is a problem that the current is increased. That is, there is a problem that device characteristics of the polysilicon thin film transistor 14 may be degraded.

To prevent this, a structure employing an etch stopper may be applied.

However, in the case of the structure to which the etch stopper is applied, there is a problem in that a separate mask different from the case of forming the active pattern 22 is used to form the etch stopper. As a result, the manufacturing process of the polysilicon thin film transistor substrate 10 becomes complicated, and there is a problem that the manufacturing cost of the polysilicon thin film transistor substrate 10 increases.

In addition, since the active pattern 22 and the etch stopper are respectively formed using different masks as described above, a discontinuous interface between the active pattern 22 and the etch stopper may be formed. For this reason, deterioration of device characteristics of the polysilicon thin film transistor 14 such as leakage current, mobility, and sub-threshold may occur.

In addition, even if the etch stopper is employed, there is a problem in that the active pattern 22 should be large in consideration of the process margin.

Accordingly, an object of the present invention is to provide a polysilicon thin film transistor substrate and a method of manufacturing the same, which can simplify the manufacturing process and lower the manufacturing cost by forming an etch stopper and an active pattern using one mask.

In addition, another technical problem to be achieved by the present invention is to provide a polysilicon thin film transistor substrate that can improve the device characteristics of the polysilicon thin film transistor by forming an etch stopper and an active pattern using a single mask and a method of manufacturing the same. will be.

Further technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above are clearly understood by those skilled in the art from the following description. It can be understood.

According to an aspect of the present invention, a polysilicon thin film transistor substrate includes a gate electrode, a source electrode, a drain electrode, an active pattern formed inside the gate electrode overlapping the gate electrode with at least one insulating film interposed therebetween, and A polysilicon thin film transistor including an ohmic contact pattern and used as a switching element; And a structure overlapping the active pattern on the active pattern of the polysilicon thin film transistor, formed inside the active pattern to expose the edge of the active pattern in a border shape, and active pattern of the polysilicon thin film transistor. Includes an etch stopper to protect it.

On the other hand, the polysilicon thin film transistor substrate according to the present invention for achieving the above technical problem is a gate line formed on the substrate; A data line insulated from and intersecting the gate line with at least one insulating film interposed therebetween; An active pattern, an ohmic contact pattern, and the active pattern formed to be connected to the gate line and the data line and overlapping the gate electrode with a gate electrode, a source electrode, a drain electrode, and at least one insulating layer interposed therebetween. A polysilicon thin film transistor formed on the pattern to overlap the active pattern and including an etch stopper formed inside the active pattern to expose the edge of the active pattern in a border shape, and used as a switching element; And a pixel electrode formed to be connected to a drain electrode of the polysilicon thin film transistor, and receiving a data voltage provided to the drain electrode from a source electrode of the polysilicon thin film transistor via an active pattern of the polysilicon thin film transistor. .

On the other hand, a method for manufacturing a polysilicon thin film transistor substrate according to the present invention for achieving the above technical problem comprises the steps of (a) forming a gate insulating film and an amorphous silicon layer on the front surface of the substrate formed with a gate electrode; (b) crystallizing the amorphous silicon layer so that the amorphous silicon layer becomes a first polysilicon layer; (c) wet oxidation of the upper part of the first polysilicon layer so that an upper part of the first polysilicon layer is an oxide layer, and the rest of the first polysilicon layer except for the upper part is a second polysilicon layer. oxidation); And (d) the second polysilicon layer overlaps the gate electrode with the gate insulating layer interposed therebetween to form an active pattern formed inside the gate electrode, and the oxide layer overlaps the active pattern on the active pattern. And photoetching the second polysilicon layer and the oxide layer so as to be an etch stopper formed inside the active pattern to expose an edge of the active pattern in a border shape.

On the other hand, a method for manufacturing a polysilicon thin film transistor substrate according to the present invention for achieving the above technical problem comprises the steps of: (a) forming a gate insulating film, an amorphous silicon layer and an etch stopper layer on the front of the substrate formed with a gate electrode; (b) crystallizing the amorphous silicon layer such that the amorphous silicon layer is a polysilicon layer; And (c) the polysilicon layer overlaps the gate electrode with the gate insulating layer interposed therebetween to form an active pattern formed inside the gate electrode, and the etch stopper layer overlaps the active pattern on the active pattern. And photoetching the polysilicon layer and the etch stopper layer so as to be an etch stopper formed inside the active pattern and exposing the edge of the active pattern in an edge shape.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings.

Hereinafter, a polysilicon thin film transistor substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a polysilicon thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3.

3 and 4, the polysilicon thin film transistor substrate 110 according to the exemplary embodiment of the present invention includes a polysilicon thin film transistor 114 and an etch stopper 126 formed on the substrate 112. In addition, the polysilicon thin film transistor substrate 110 further includes a gate line 128, a data line 130, and a pixel electrode 132 formed on the substrate 112. Here, the substrate 112 may have a transparent material such as glass or plastic, or may have an opaque material such as stainless steel.

The polysilicon thin film transistor 114 is used as a switching element. To this end, the polysilicon thin film transistor 114 may include a gate electrode 116, a source electrode 118, a drain electrode 120, an active pattern 122, and an ohmic contact pattern 124. Here, the polysilicon thin film transistor 114 may further include an etch stopper 126.

The gate electrode 116 turns the polysilicon thin film transistor 114 on or off using a gate voltage provided from the gate line 128, for example, a gate on / off voltage. For this purpose, the gate electrode 116 may be formed to be connected to the gate line 128.

The gate electrode 116 is formed under the active pattern 122, and may be formed to overlap the active pattern 122 with at least one insulating layer, for example, the gate insulating layer 134 interposed therebetween. Here, the gate insulating layer 134 may be formed on the entire surface of the substrate 112 to cover the gate electrode 116 and the gate line 128.

The gate electrode 116 is made of a metal material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Cu or Cu alloy, Ti or Ti alloy, Ta or Ta alloy, for example. It may be formed to have at least one layer.

When the polysilicon thin film transistor 114 is turned on by the gate-on voltage provided from the gate electrode 116, the source electrode 118 receives the data voltage provided from the data line 130 via the active pattern 122. The drain electrode 120 is provided. For this purpose, the source electrode 118 may be formed to be connected to the data line 130. In addition, the source electrode 118 may be formed to overlap the gate electrode 116 with at least one insulating layer, for example, the gate insulating layer 134 interposed therebetween. In addition, the source electrode 118 may be formed to overlap the active pattern 122.

The source electrode 118 is made of a metal material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Cu or Cu alloy, Ti or Ti alloy, Ta or Ta alloy, for example. It may be formed to have at least one layer.

The drain electrode 120 provides the data voltage provided from the source electrode 118 to the pixel electrode 132 connected thereto via the active pattern 122. To this end, the drain electrode 120 may be formed of the same material as the source electrode 118 on the same plane as the source electrode 118. In addition, the drain electrode 120 is formed to be spaced apart from the source electrode 118 by a predetermined interval, and formed to overlap the gate electrode 116 with at least one insulating film, for example, the gate insulating film 134 interposed therebetween. Can be. In addition, the drain electrode 120 may be formed to overlap the active pattern 122.

The active pattern 122 forms a channel through which the data voltage can be provided from the source electrode 118 to the drain electrode 120, that is, the channel of the polysilicon thin film transistor 114. To this end, the active pattern 122 may be formed of a polysilicon material.

The active pattern 122 may be formed inside the gate electrode 116 by overlapping the gate electrode 116 with at least one insulating layer, for example, the gate insulating layer 134 interposed therebetween. In the liquid crystal display device employing the polysilicon thin film transistor substrate 110, this is to prevent leakage current by light provided from the backlight unit disposed on the back surface of the polysilicon thin film transistor substrate 110, but is not limited thereto.

The thickness of the active pattern 122 may be 100 mW to 1000 mW. This is because the back channel portion is formed in a flat shape without being etched by the etch stopper 126. Here, the back channel portion refers to a region overlapping the gate electrode 116 and adjacent to the upper surface of the active pattern 122, that is, the region adjacent to the etch stopper 126.

Specifically, the thickness of the active pattern 122 may be, for example, between 100 kPa and 800 kPa when the etch stopper 126 is formed through a wet oxidation process of the polysilicon layer. On the other hand, the thickness of the active pattern 122 may be, for example, 300 Å to 1000 Å when the etch stopper 126 is formed through a deposition process instead of through the wet oxidation process.

The ohmic contact pattern 124 is formed for ohmic contact of the source electrode 118 and the active pattern 122, and the drain electrode 120 and the active pattern 122, respectively. To this end, the ohmic contact pattern 124 may be formed such that its upper surface is in contact with the source electrode 118 and its lower surface is in contact with the active pattern 122. In addition, the ohmic contact pattern 124 may be formed such that its upper surface is in contact with the drain electrode 120 and its lower surface is in contact with the active pattern 122.

The ohmic contact pattern 124 may have an amorphous silicon material doped with n + -type impurities, but is not limited thereto.

The etch stopper 126 protects the active pattern 122 when the ohmic contact layer is etched in an area overlapping the back channel part. That is, as described above, the etch stopper 126 allows the back channel portion of the active pattern 122 to maintain a flat shape. For this reason, the etch stopper 126 may be included in the polysilicon thin film transistor 114.

The etch stopper 126 may be formed to overlap the active pattern 122 on the active pattern 122, and may be formed inside the active pattern 122 to expose the edge of the active pattern 122 in a border shape. have.

In this case, each of the width We and the length Le of the etch stopper 126 may be smaller than each of the width Wa and the length La of the active pattern 122. In this case, the difference between the width Wa of the active pattern 122 and the width We of the etch stopper 126, and the difference between the length La of the active pattern 122 and the length Le of the etch stopper 126 may be the same. .

Specifically, the difference between the width Wa of the active pattern 122 and the width We of the etch stopper 126 may be 0.2 μm to 2 μm. More specifically, the width W1 from one side of the active pattern 122 to one side of the etch stopper 126 may be 0.1 μm to 1 μm. In this case, since the width from the other side of the active pattern 122 to the other side of the etch stopper 126 may be 0.1 μm to 1 μm, the active pattern 122 and the etch stopper 126 may refer to the center of the etch stopper 126. It can be formed in a symmetrical form in the width direction.

In detail, the difference between the length La of the active pattern 122 and the length Le of the etch stopper 126 may be 0.2 μm to 2 μm. More specifically, the length L1 from one side of the active pattern 122 to one side of the etch stopper 126 may be 0.1 μm to 1 μm. In this case, since the length from the other side of the active pattern 122 to the other side of the etch stopper 126 may be 0.1 μm to 1 μm, the active pattern 122 and the etch stopper 126 may refer to the center of the etch stopper 126. It can be formed in a symmetrical form in the longitudinal direction.

The etch stopper 126 material may be at least one of silicon oxide and silicon nitride.

Specifically, the etch stopper 126 material may be, for example, silicon oxide when the etch stopper 126 is formed through a wet oxidation process of the polysilicon layer. On the other hand, the etch stopper 126 material may be, for example, at least one of silicon oxide and silicon nitride when the etch stopper 126 is formed through a deposition process instead of being formed through the wet oxidation process. .

The etch stopper 126 may have a thickness of 200 ns to 1000 ns.

Specifically, the etch stopper 126 thickness may be 200 kPa to 500 kPa, for example, when the etch stopper 126 is formed through a wet oxidation process of the polysilicon layer. On the other hand, the etch stopper 126 thickness may be, for example, 300 Å to 1000 경우 when the etch stopper 126 is formed through a deposition process instead of through the wet oxidation process.

Due to the above structure, the active pattern 122 may not be damaged by the etch stopper 126 when the ohmic contact layer is etched in the region overlapping the back channel part. In addition, the etch stopper 126 and the active pattern 122 may be formed using the same mask.

Accordingly, a continuous interface between the active pattern 122 and the etch stopper 126 may be formed. For this reason, the strain between the silicon lattice in the active pattern 122 and the silicon-si bonding in the active pattern 122 due to the discontinuous interface between the active pattern 122 and the etch stopper 126. It is possible to reduce the defects such as breaks in.

For this reason, device characteristics of the polysilicon thin film transistor 114 such as mobility and sub-threshold can be improved.

In addition, since the thickness of the active pattern 122 can be reduced, the leakage current according to the thickness of the active pattern 122 can be reduced. In addition, since the size of the active pattern 122 can be reduced, leakage current caused by the backlight unit can be reduced.

In addition, since the number of masks can be reduced while simplifying the process, not only can the productivity of the polysilicon thin film transistor substrate 110 be improved, but also the manufacturing cost can be reduced.

The gate line 128 provides a gate voltage provided from the gate driver, for example, a gate on / off voltage, to the gate electrode 116. To this end, one side of the gate line 128 may be extended to be connected to the gate driver. In addition, the gate line 128 may be formed to be connected to the gate electrode 116. In addition, the gate line 128 may be formed of the same material as the gate electrode 116 on the same plane as the gate electrode 116.

The data line 130 provides a data voltage provided from the data driver to the source electrode 118. To this end, one side of the data line 130 may be extended to be connected to the data driver. In addition, the data line 130 may be formed to be connected to the source electrode 118. In addition, the data line 130 may be formed of the same material as the source electrode 118 on the same plane as the source electrode 118, and may include at least one insulating layer, for example, a gate insulating layer 134. It may be formed to insulate and intersect the gate line 128.

The pixel electrode 132 receives a data voltage provided from the source electrode 118 to the drain electrode 120 via the active pattern 122. In this case, for example, when the polysilicon thin film transistor substrate 110 is employed in the liquid crystal display, the pixel electrode 132 applies the data voltage to the liquid crystal.

In order to receive the data voltage, the pixel electrode 132 may be formed to be connected to the source electrode 118 through at least one insulating layer, for example, a contact hole 138 penetrating through the passivation layer 136. It is not limited to this.

The pixel electrode 132 may be formed of a transparent metal material such as ITO, IZO, TO, and IZTO, but is not limited thereto.

5A to 5K are cross-sectional views for describing a first embodiment of the method for manufacturing the polysilicon thin film transistor substrate illustrated in FIG. 3. 5A to 5K are views for explaining a manufacturing method when the etch stopper is formed through a wet oxidation process of the polysilicon layer.

In order to manufacture the polysilicon thin film transistor substrate 110 according to the first embodiment of the present invention, first, as shown in FIG. 5A, a gate is formed on the front surface of the substrate 112 on which the gate electrode 116 is formed. The insulating film 134 and the amorphous silicon layer 140 are formed.

Specifically, for example, the gate electrode 116 is a metal such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Cu or Cu alloy, Ti or Ti alloy, Ta or Ta alloy The substrate 112 formed of at least one layer of a material is prepared. Here, the gate line 128 may be formed at the same time as the gate electrode 116 is formed.

Subsequently, the gate insulating layer 134 and the amorphous silicon layer 140 are continuously formed on the entire surface of the substrate 112.

Specifically, for example, the gate insulating film 134 having a predetermined thickness, for example, 500 ns to 5000 ns, on the entire surface of the substrate 112, and an amorphous material having a predetermined thickness, for example, 300 ns to 1000 ns. The silicon layer 140 is formed continuously. In this case, the gate insulating layer 134 may be formed of at least one of silicon oxide and silicon nitride. Here, any one of plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD) may be used to form the gate insulating layer 134 and the amorphous silicon layer 140, but is not limited thereto. .

Next, as shown in FIG. 5B, the amorphous silicon layer 140 is crystallized such that the amorphous silicon layer 140 becomes the first polysilicon layer 142.

Specifically, for example, the substrate 112 is introduced into a heat treatment apparatus using an alternating magnetic field crystallization (AMFC) method.

Subsequently, it heats so that the temperature in the said heat processing apparatus may be 700 to 1000 degreeC. As a result, the substrate 112 may be heated to 700 ° C to 1000 ° C. Here, the temperature in the heat treatment apparatus can be gradually heated to the above 700 ℃ to 1000 ℃. Alternatively, a heat treatment apparatus having a plurality of process chambers corresponding to stepwise rising temperatures may be used.

Subsequently, a magnetic field is formed around the substrate 112 using a magnetic core or the like disposed around the substrate 112. As a result, the substrate 112 is induction heated, and the amorphous silicon layer 140 formed on the substrate 112 is crystallized to form the first polysilicon layer 142.

Next, as shown in FIG. 5C, an upper portion of the first polysilicon layer 142 is an oxide layer 144, and a second polysilicon layer 146 is left except for the upper portion of the first polysilicon layer 142. ), The top of the first polysilicon layer 142 is wet oxidized.

Specifically, for example, while maintaining the temperature in the heat treatment apparatus at 700 ° C to 1000 ° C, oxygen and hydrogen gas are supplied into the heat treatment apparatus to form the oxygen and hydrogen gas atmosphere.

Then, Si-Si bonding and / or silicon and hydrogen bonding (Si-H bonding) of the first polysilicon layer 142 are broken and oxygen atoms enter the vacant places where the bonding is broken. do.

Accordingly, an upper portion of the first polysilicon layer 142 may be an oxide layer 144, and the rest of the first polysilicon layer 142 may be a second polysilicon layer 146.

The oxide layer 144 may be made of silicon oxide, and the thickness thereof may be 200 kPa to 500 kPa. Therefore, the thickness of the second polysilicon layer 146 may be 100 kPa to 800 kPa.

Next, as shown in FIGS. 5D to 5H, the second polysilicon layer 146 becomes the active pattern 122 and the oxide layer 144 becomes the etch stopper 126. 146 and the oxide layer 144 are photo-etched.

Specifically, for example, as shown in FIG. 5D, after forming a photoresist layer on the entire surface of the substrate 112, a photo process is performed to form the first photoresist pattern 154. Here, the photoresist layer may have positive photosensitivity, but is not limited thereto.

Subsequently, as illustrated in FIG. 5E, the first photoresist pattern formed through the photolithography process such that the second polysilicon layer 146 and the oxide layer 144 become the active pattern 122 and the oxide pattern 148, respectively. The second polysilicon layer 146 and the oxide layer 144 are first etched using 154 as a mask.

Specifically, for example, the second polysilicon layer 146 and the oxide layer 144 are first etched using the first photoresist pattern 154 as a mask. In this case, the first etching may be applied to any one of dry etching, wet etching, or a combination thereof in consideration of an etching selectivity. Then, the active pattern 122 and the oxide pattern 148 may be formed.

Subsequently, as illustrated in FIG. 5F, the first photoresist pattern 154 may be the second photoresist pattern 156 having a smaller size than the first photoresist pattern 154. Ashing

Specifically, for example, the substrate 112 is disposed in a dry etching apparatus, and then the first photoresist pattern 154 is etched using oxygen plasma or the like. Then, the second photoresist pattern 156 having a smaller size than the first photoresist pattern 154 may be formed.

Next, as illustrated in FIG. 5G, the oxide pattern 148 is secondly etched using the second photoresist pattern 156 as a mask so that the oxidation pattern 148 becomes the etch stopper 126.

Specifically, for example, the oxide pattern 148 is secondly etched using the second photoresist pattern 156 as a mask. In this case, the second etching may be applied to any one of dry etching, wet etching, or a combination thereof in consideration of an etching selectivity. Then, the etch stopper 126 may be formed.

Next, as shown in FIG. 5H, the surface of the etch stopper 126 is exposed to the outside by removing the second photoresist pattern 156 using a stripper or the like.

An etch stopper 126 may be formed inside the active pattern 122 to expose an edge of the active pattern 122 in a border shape through the series of processes described above.

In addition, since the active pattern 122 and the etch stopper 126 may be formed using one mask, the manufacturing process of the polysilicon thin film transistor substrate 110 may be simplified, productivity may be improved, and manufacturing cost may be reduced.

In addition, a continuous interface between the active pattern 122 and the etch stopper 126 may be formed.

Next, as shown in FIG. 5I, an ohmic contact pattern 124 in contact with the active pattern 122, and a source electrode 118 and a drain electrode 120 in contact with the ohmic contact pattern 124 are formed. do. Here, the data line 130 may be formed at the same time as the source electrode 118 and the drain electrode 120 are formed.

Specifically, for example, an amorphous silicon layer doped with n + impurities, that is, an ohmic contact layer, is formed to a predetermined thickness, for example, between 20 kPa and 500 kPa. Here, any one method such as PECVD and LPCVD may be used for forming the ohmic contact layer, but is not limited thereto.

Subsequently, at least the data metal layer is formed of a material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Cu or Cu alloy, Ti or Ti alloy, Ta or Ta alloy on the ohmic contact layer. It is formed by one or more layers. Here, a method such as sputtering may be used to form the data metal layer, but is not limited thereto. Meanwhile, the ohmic contact layer and the data metal layer may be continuously formed in the same process equipment.

Subsequently, the ohmic contact layer and the data metal layer are etched through a photolithography process. In this case, the etching process may be applied to any one of dry etching, wet etching, or a combination thereof in consideration of an etching selectivity.

During the etching process, the ohmic contact layer in the region overlapping the back channel part is etched. In this case, the back channel portion of the active pattern 122 may be protected without being etched by the etch stopper 126.

Through this series of processes, an ohmic contact pattern 124 contacting the active pattern 122, and a source electrode 118 and a drain electrode 120 contacting the ohmic contact pattern 124 may be formed.

Next, as shown in FIG. 5J, a protective film 136 having a contact hole 138 is formed on the entire surface of the substrate 112.

Specifically, for example, a photo and / or an etching process may be performed to form the passivation layer 136. The protective layer 136 may be formed of an organic material such as benzocyclobutene (BCB), polyimide, and acryl. Alternatively, the protective layer 136 may be formed of an inorganic material such as silicon oxide, silicon nitride, TEOS, or the like. Alternatively, the protective layer 136 may be a combination of the organic material and the inorganic material. Here, the passivation layer 136 may be formed of at least one layer. Here, the thickness of the protective film 136 may have a thickness of, for example, 1000 kPa to 30000 kPa.

Next, as illustrated in FIG. 5K, the pixel electrode 132 connected to the drain electrode 120 is formed through the contact hole 138.

Specifically, for example, a photolithography process may be performed to form the pixel electrode 132. The pixel electrode 132 may be made of a transparent metal material such as ITO, IZO, TO, and IZTO. Here, the thickness of the pixel electrode 132 may be, for example, 100 kPa to 2000 kPa.

6A to 6F are cross-sectional views illustrating a second embodiment of the method for manufacturing the polysilicon thin film transistor substrate illustrated in FIG. 3. 6A to 6F are views for explaining a manufacturing method when the etch stopper is formed through a deposition process. In the second embodiment of the method for manufacturing the polysilicon thin film transistor substrate shown in FIG. 3, the description overlapping with the first embodiment of the method for manufacturing the polysilicon thin film transistor substrate shown in FIG. 3 will be omitted, and only its features will be described. .

In order to manufacture the polysilicon thin film transistor substrate 110 according to the second embodiment of the present invention, first, as shown in FIG. 6A, a gate is formed on the front surface of the substrate 112 on which the gate electrode 116 is formed. The insulating film 134, the amorphous silicon layer 140, and the etch stopper layer 150 are formed.

Specifically, for example, the substrate 112 on which the gate electrode 116 is formed is prepared. Since this is the same as described above, the detailed description thereof will be omitted.

Subsequently, the gate insulating layer 134, the amorphous silicon layer 140, and the etch stopper layer 150 are continuously formed on the entire surface of the substrate 112.

Specifically, for example, the gate insulating film 134 having a predetermined thickness, for example, 500 Å to 5000 Å, on the entire surface of the substrate 112, and an amorphous silicon layer having a predetermined thickness, eg, Å 300 Å to 1000 Å 140, and an etch stopper layer 150 having a predetermined thickness, for example, between 300 mm and 1000 mm thick.

In this case, the gate insulating layer 134 and the etch stopper layer 150 may be formed of at least one of silicon oxide and silicon nitride. Here, any one method such as PECVD and LPCVD may be used to form the gate insulating layer 134, the amorphous silicon layer 140, and the etch stopper layer 150, but is not limited thereto.

Next, as shown in FIG. 6B, the amorphous silicon layer 140 is crystallized such that the amorphous silicon layer 140 becomes a polysilicon layer 142.

Specifically, for example, a heat treatment apparatus using the magnetic field crystallization method as described above is used. And, the temperature in the heat treatment apparatus also crystallizes the amorphous silicon layer 140 in the same state as described above 700 ~ 1000 ℃.

In this case, even if the etch stopper layer 150 is formed on the amorphous silicon layer 140, the amorphous silicon layer 140 may be crystallized. This is due to the heat treatment device characteristics. That is, when the heat treatment apparatus is used, since the etch stopper layer 150 formed on the amorphous silicon layer 140 does not affect the crystallinity of the amorphous silicon layer 140, the polysilicon is crystallized to crystallize the polysilicon layer 140. The silicon layer 142 may be formed.

Next, as shown in FIGS. 6C-6F, the polysilicon layer 142 such that the polysilicon layer 142 becomes the active pattern 122 and the etch stopper layer 150 becomes the etch stopper 126. And etching the etch stopper layer 150.

Specifically, for example, as shown in FIG. 6C, after forming a photoresist layer on the entire surface of the substrate 112, a photo process is performed to form the first photoresist pattern 154. Here, the photoresist layer may have positive photosensitivity, but is not limited thereto.

Subsequently, as illustrated in FIG. 6D, the first silicon layer 142 and the etch stopper layer 150 may be the active pattern 122 and the etch stopper bulb pattern 152, respectively. The polysilicon layer 142 and the etch stopper layer 150 are first etched using the photoresist pattern 154 as a mask. Here, the first etching may be applied to any one of dry etching, wet etching, or a combination thereof in consideration of an etching selectivity. Then, the active pattern 122 and the etch stopper bulb pattern 152 may be formed.

Subsequently, as shown in FIG. 6E, the first photoresist pattern 154 may be the second photoresist pattern 156 having a smaller size than the first photoresist pattern 154. Ashing Since this is the same as described above, the detailed description thereof will be omitted. Then, the second photoresist pattern 156 may be formed.

Next, as illustrated in FIG. 6F, the etch stopper bulb pattern 152 is secondly etched using the second photoresist pattern 156 as a mask so that the etch stopper bulb pattern 152 becomes the etch stopper 126. . Here, the second etching may be applied to any one of dry etching, wet etching, or a combination thereof in consideration of an etching selectivity. Then, the etch stopper 126 may be formed.

Next, the surface of the etch stopper 126 is exposed to the outside by removing the second photoresist pattern 156 using a stripper or the like.

An etch stopper 126 may be formed inside the active pattern 122 to expose an edge of the active pattern 122 in a border shape through the series of processes described above.

In addition, since the active pattern 122 and the etch stopper 126 may be formed using one mask, the manufacturing process of the polysilicon thin film transistor substrate 110 may be simplified, productivity may be improved, and manufacturing cost may be reduced.

In addition, a continuous interface between the active pattern 122 and the etch stopper 126 may be formed.

Next, an ohmic contact pattern 124 in contact with the active pattern 122, and a source electrode 118 and a drain electrode 120 in contact with the ohmic contact pattern 124 are formed. Next, the passivation layer 136 having the contact hole 138 is formed on the entire surface of the substrate 112. Next, the pixel electrode 132 connected to the drain electrode 120 is formed through the contact hole 138. Since this is the same as described above, a detailed description thereof will be omitted.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

According to the present invention, the etch stopper and the active pattern can be formed using one mask. For this reason, the manufacturing process of a polysilicon polysilicon thin film transistor substrate can be simplified, and manufacturing cost can be reduced.

In addition, when the ohmic contact layer is etched in the region overlapping the back channel part, the active pattern may not be damaged by the etch stopper, and the thickness of the active pattern may be reduced, and the size of the active pattern may be reduced. In addition, it is possible to form a continuous interface between the active pattern and the etch stopper. Because of this, device characteristics of polysilicon thin film transistors such as mobility, sub-threshold and leakage current can be improved.

Claims (48)

A polysilicon thin film transistor including a gate electrode, a source electrode, a drain electrode, an active pattern formed inside the gate electrode overlapping the gate electrode with at least one insulating layer interposed therebetween, and an ohmic contact pattern, the polysilicon thin film transistor being used as a switching element; And It is formed to overlap the active pattern on the active pattern of the polysilicon thin film transistor, and is formed inside the active pattern to expose the edge of the active pattern in a border shape, and the active pattern of the polysilicon thin film transistor Etch stopper to protect Polysilicon thin film transistor substrate comprising a. The method of claim 1, And the difference between the active pattern width and the etch stopper width of the polysilicon thin film transistor and the difference between the active pattern length and the etch stopper length are the same. The method of claim 1, A polysilicon thin film transistor substrate, wherein a difference between an active pattern width and an etch stopper width of the polysilicon thin film transistor is 0.2 µm to 2 µm. The method of claim 3, The polysilicon thin film transistor substrate, wherein a width from one side of the active pattern of the polysilicon thin film transistor to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 1, The difference between the active pattern length and the etch stopper length of the polysilicon thin film transistor is 0.2 µm to 2 µm. The method of claim 5, The polysilicon thin film transistor substrate of claim 1, wherein a length from one side of the active pattern of the polysilicon thin film transistor to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 1, An active pattern thickness of said polysilicon thin film transistor is 100 kV to 1000 kV, The polysilicon thin film transistor substrate characterized by the above-mentioned. The method of claim 1, The etch stopper material is at least one of silicon oxide and silicon nitride, polysilicon thin film transistor substrate. The method of claim 1, The etch stopper thickness is 200 kPa to 1000 kPa, polysilicon thin film transistor substrate. The method of claim 1, The gate electrode of the polysilicon thin film transistor, the polysilicon thin film transistor substrate, characterized in that formed under the active pattern of the polysilicon thin film transistor. The method of claim 1, A gate line formed to be connected to a gate electrode of the polysilicon thin film transistor and providing a gate voltage to the gate electrode; A data line formed to be connected to a source electrode of the polysilicon thin film transistor and providing a data voltage to the source electrode; And A pixel electrode formed to be connected to a drain electrode of the polysilicon thin film transistor and receiving the data voltage provided to the drain electrode from a source electrode of the polysilicon thin film transistor via an active pattern of the polysilicon thin film transistor Polysilicon thin film transistor substrate further comprising. A gate line formed on the substrate; A data line insulated from and intersecting the gate line with at least one insulating film interposed therebetween; An active pattern, an ohmic contact pattern, and the active pattern formed to be connected to the gate line and the data line and overlapping the gate electrode with a gate electrode, a source electrode, a drain electrode, and at least one insulating layer interposed therebetween. A polysilicon thin film transistor formed on the pattern to overlap the active pattern and including an etch stopper formed inside the active pattern to expose the edge of the active pattern in a border shape, and used as a switching element; And A pixel electrode formed to be connected to a drain electrode of the polysilicon thin film transistor and receiving a data voltage provided to the drain electrode from a source electrode of the polysilicon thin film transistor via an active pattern of the polysilicon thin film transistor Polysilicon thin film transistor substrate comprising a. The method of claim 12, And the difference between the active pattern width and the etch stopper width of the polysilicon thin film transistor and the difference between the active pattern length and the etch stopper length are the same. The method of claim 12, A polysilicon thin film transistor substrate, wherein a difference between an active pattern width and an etch stopper width of the polysilicon thin film transistor is 0.2 µm to 2 µm. The method of claim 14, The polysilicon thin film transistor substrate, wherein a width from one side of the active pattern of the polysilicon thin film transistor to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 12, The difference between the active pattern length and the etch stopper length of the polysilicon thin film transistor is 0.2 µm to 2 µm. The method of claim 16, The polysilicon thin film transistor substrate of claim 1, wherein a length from one side of the active pattern of the polysilicon thin film transistor to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 12, An active pattern thickness of said polysilicon thin film transistor is 100 kV to 1000 kV, The polysilicon thin film transistor substrate characterized by the above-mentioned. The method of claim 12, The etch stopper material of the polysilicon thin film transistor is at least one of silicon oxide and silicon nitride. The method of claim 12, An etch stopper thickness of said polysilicon thin film transistor is 200 mW to 1000 mW. The method of claim 12, The gate electrode of the polysilicon thin film transistor, the polysilicon thin film transistor substrate, characterized in that formed under the active pattern of the polysilicon thin film transistor. (a) forming a gate insulating film and an amorphous silicon layer on the entire surface of the substrate on which the gate electrode is formed; (b) crystallizing the amorphous silicon layer so that the amorphous silicon layer becomes a first polysilicon layer; (c) wet oxidation of the upper part of the first polysilicon layer so that an upper part of the first polysilicon layer is an oxide layer, and the rest of the first polysilicon layer except for the upper part is a second polysilicon layer. oxidation); And (d) the second polysilicon layer overlaps the gate electrode with the gate insulating layer interposed therebetween to become an active pattern formed inside the gate electrode, and the oxide layer is formed to overlap the active pattern on the active pattern; Photo-etching the second polysilicon layer and the oxide layer so as to be an etch stopper formed inside the active pattern to expose an edge of the active pattern in a border shape. Method of manufacturing a polysilicon thin film transistor substrate comprising a. The method of claim 22, The thickness of the amorphous silicon layer of the step (a) is 300 Å to 1000 Å, the method of manufacturing a polysilicon thin film transistor substrate. The method of claim 22, Wherein (b) and (c) is a method of manufacturing a polysilicon thin film transistor substrate, characterized in that the step is performed in a heat treatment apparatus using an alternating magnetic field crystallization (AMFC) method. The method of claim 24, Step (b) and (c) is a method of manufacturing a polysilicon thin film transistor substrate, characterized in that the step is performed within a temperature range of 700 ℃ to 1000 ℃. The method of claim 25, wherein step (c) comprises: Supplying oxygen and hydrogen gas into the heat treatment apparatus to form the oxygen and hydrogen gas atmosphere Method of manufacturing a polysilicon thin film transistor substrate comprising a. The method of claim 26, The method of manufacturing a polysilicon thin film transistor substrate, characterized in that the oxide layer material of step (c) is silicon oxide. The method of claim 26, The thickness of the oxide layer in the step (c) is 200 kPa to 500 kPa, a method for producing a polysilicon thin film transistor substrate. The method of claim 22, wherein step (d) (d-1) The second polysilicon layer and the oxide layer are formed by using a first photoresist pattern formed through the photolithography process as a mask such that the second polysilicon layer and the oxide layer become the active pattern and the oxide pattern, respectively. First etching; (d-2) ashing the first photoresist pattern such that the first photoresist pattern is a second photoresist pattern having a smaller size than the first photoresist pattern; (d-3) second etching the oxide pattern using the second photoresist pattern as a mask so that the oxide pattern becomes an etch stopper; And (d-4) removing the second photoresist pattern Method of manufacturing a polysilicon thin film transistor substrate comprising a. The method of claim 22, And the difference between the active pattern width and the etch stopper width in step (d) and the difference between the active pattern length and the etch stopper length are the same. The method of claim 22, The difference between the active pattern width and the etch stopper width in the step (d) is 0.2 µm to 2 µm. The method of claim 31, wherein A method of manufacturing a polysilicon thin film transistor substrate, wherein a width from one side of the active pattern in step (d) to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 22, The difference between the active pattern length and the etch stopper length in the step (d) is 0.2 µm to 2 µm. The method of claim 33, wherein And a length from one side of the active pattern in the step (d) to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 22, (e) forming an ohmic contact pattern in contact with the active pattern and a source electrode and a drain electrode in contact with the ohmic contact pattern Method for producing a polysilicon thin film transistor substrate further comprising. (a) forming a gate insulating film, an amorphous silicon layer, and an etch stopper layer on the entire surface of the substrate on which the gate electrode is formed; (b) crystallizing the amorphous silicon layer such that the amorphous silicon layer is a polysilicon layer; And (c) the polysilicon layer overlaps the gate electrode with the gate insulating layer interposed therebetween to become an active pattern formed inside the gate electrode, and the etch stopper layer is formed to overlap the active pattern on the active pattern; Photo-etching the polysilicon layer and the etch stopper layer so as to be an etch stopper formed inside the active pattern and exposing the edge of the active pattern in an edge shape. Method of manufacturing a polysilicon thin film transistor substrate comprising a. The method of claim 36, The thickness of the amorphous silicon layer of the step (a) is 300 Å to 1000 Å, the method of manufacturing a polysilicon thin film transistor substrate. The method of claim 36, The material of the etch stopper layer of step (a) is at least one or more of silicon oxide and silicon nitride. The method of claim 36, The thickness of the etch stopper layer in the step (a) is 300 kPa to 1000 kPa, the polysilicon thin film transistor substrate manufacturing method. The method of claim 36, The step (b) is a method of manufacturing a polysilicon thin film transistor substrate, characterized in that the step is performed in a heat treatment apparatus using an alternating magnetic field crystallization (AMFC) method. The method of claim 40, The step (b) is a method for producing a polysilicon thin film transistor substrate, characterized in that the step performed in the temperature range of 700 ℃ to 1000 ℃. The method of claim 36, wherein step (c) comprises: (c-1) The polysilicon layer and the etch using a first photoresist pattern formed through the photolithography process as a mask such that the polysilicon layer and the etch stopper layer become the active pattern and the etch stopper bulb pattern, respectively. First etching the stopper layer; (c-2) ashing the first photoresist pattern such that the first photoresist pattern is a second photoresist pattern having a smaller size than the first photoresist pattern; (c-3) second etching the etch stopper bulb pattern using the second photoresist pattern as a mask so that the etch stopper bulb pattern becomes the etch stopper; And (c-4) removing the second photoresist pattern Method of manufacturing a polysilicon thin film transistor substrate comprising a. The method of claim 36, And (c) the difference between the active pattern width and the etch stopper width, and the difference between the active pattern length and the etch stopper length are the same. The method of claim 36, The difference between the active pattern width and the etch stopper width in the step (c) is 0.2 µm to 2 µm. The method of claim 44, A method of manufacturing a polysilicon thin film transistor substrate, wherein a width from one side of the active pattern in step (c) to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 36, The difference between the active pattern length and the etch stopper length in the step (c) is 0.2 µm to 2 µm. 47. The method of claim 46 wherein And a length from one side of the active pattern in the step (d) to one side of the etch stopper is 0.1 μm to 1 μm. The method of claim 36, (d) forming an ohmic contact pattern in contact with the active pattern and a source electrode and a drain electrode in contact with the ohmic contact pattern Method for producing a polysilicon thin film transistor substrate further comprising.

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