KR20070040017A - Thin film transistor and fabrication method of the same - Google Patents

Abstract

The present invention relates to a thin film transistor having improved leakage current characteristics and a method of manufacturing the same.

According to the present invention, a thin film transistor and a method of manufacturing the same may be formed by forming an active layer on a substrate, and stacking the active layer on the active layer so that the side surface of the active layer is thicker than the rest of the active layer. Forming a multi-layered gate insulating film having a difference, forming a gate electrode on the gate insulating film, forming an interlayer insulating film on the gate insulating film and the gate electrode, and forming a source electrode and a drain electrode on the interlayer insulating film. It characterized in that it comprises a step of forming.

Description

Thin film transistor and its manufacturing method {THIN FILM TRANSISTOR AND FABRICATION METHOD OF THE SAME}

1 is a cross-sectional view of a thin film transistor using a conventional polycrystalline silicon.

2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the thin film transistor substrate taken along the line II ′ in FIG. 2.

4A through 4H are cross-sectional views illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 3.

<Description of Main Parts of Drawing>

30,130; thin film transistor 32, 132; active layer

34,134; gate electrode 36,136; source electrode

37,137; drain electrode 51,151; gate insulating film

141; source contact hole 143; drain contact hole

145; pixel contact hole 152; first gate insulating film

153; second gate insulating film 154; third gate insulating film

156; interlayer insulating film 138; pixel electrode

158; shield

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor having improved leakage current characteristics and a method for manufacturing the same.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display has a resolution, It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors. In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly. The lower substrate of the liquid crystal display device includes a thin film transistor which is a switching element. In general, an active layer used in the thin film transistor is made of amorphous silicon (a-Si: H). This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature. On the other hand, recently, liquid crystal display devices employing thin film transistors using polycrystalline silicon (poly-Si) have been researched and developed. Since the polycrystalline silicon has a field effect mobility of about 100 to 200 times greater than that of amorphous silicon, the response speed is fast and the stability to temperature and light is excellent. In addition, there is an advantage that the driving circuit can be formed on the same substrate.

Hereinafter, a thin film transistor using polycrystalline silicon will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a thin film transistor using a conventional polycrystalline silicon.

As shown in FIG. 1, the polycrystalline silicon thin film transistor 30 generally includes an active layer 32, a gate electrode 34, source / drain electrodes 36 and 37, and an active layer 32 and a gate electrode ( A gate insulating film 52 positioned between the 34 and an interlayer insulating film 56 positioned between the gate electrode 34 and the source / drain electrodes 36 and 37.

In the circuit using the thin film transistor 30, there is a tendency to increase the thickness of the active layer 32 in order to improve the field effect mobility, and to lower the threshold voltage of the thin film transistor 30 in order to implement a high speed operation. It is required. The threshold voltage of the thin film transistor 30 has a close relationship with the thickness of the gate insulating film 52. In order to lower the threshold voltage, the gate insulating film 52 is thinly formed. However, as the gate insulating film 52 becomes thinner, when the electric field between the gate electrode 34 and the active layer 32 is increased, the dielectric breakdown voltage characteristic, which is the maximum electric field until the gate insulating film 52 is destroyed, is deteriorated. do. In addition, there is a problem that leakage current occurs in the off state. In particular, as the thickness of the active layer 32 becomes thicker or the slope of the inclined taper area A on the side surface of the active layer 32 increases, the gate insulating film 52 in the taper area A becomes thinner. It is difficult to form thin enough to prevent dielectric breakdown voltage and leakage current of the gate insulating film 52. This increases leakage current, causes malfunction of the thin film transistor 30, and displays such as point defects, line defects, and luminance unevenness in the display device using the thin film transistor 30. It may cause a defect.

The present invention provides a thin film transistor having improved leakage current characteristics and a method of manufacturing the same.

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises the steps of forming an active layer on a substrate, laminated on the active layer, the side of the active layer is thicker than the remaining area of the active layer Forming a multi-layered gate insulating film having a thickness difference according to a position to be thick, forming a gate electrode on the gate insulating film, forming an interlayer insulating film on the gate insulating film and the gate electrode, and forming the interlayer insulating film And forming a source electrode and a drain electrode thereon.

The forming of the gate insulating film may include sequentially stacking first to third gate insulating films on the substrate on which the active layer is formed, and exposing the top surface of the second gate insulating film. And removing a part.

The removing of the third gate insulating layer may be performed by a CMP process.

The second gate insulating layer may be formed of a material having a stronger strength than the first and third gate insulating layers.

The first gate insulating film may be formed of a silicon oxide film, the second gate insulating film may be formed of a silicon nitride film, and the third gate insulating film may be formed of a silicon oxide film.

On the other hand, the gate insulating film is characterized in that the inorganic material.

In order to achieve the above object, the thin film transistor according to the present invention forms an active layer formed on a substrate and forms a channel, and is formed on the active layer, and the side surface of the active layer is larger than the thickness of the remaining region of the active layer. It characterized in that it comprises a gate insulating film formed in multiple layers having a thickness difference depending on the position to be thick.

The gate insulating layer may be formed to sequentially cover the active layer, the first and second gate insulating layers having convex portions in a region corresponding to the active layer, and the remaining regions except for the convex portions of the second gate insulating layer. And a third gate insulating film formed on the second gate insulating film to planarize the substrate.

The second gate insulating layer may be formed of a material having a stronger strength than the first and third gate insulating layers.

The first gate insulating film may be formed of a silicon oxide film, the second gate insulating film may be formed of a silicon nitride film, and the third gate insulating film may be formed of a silicon oxide film.

On the other hand, a gate electrode connected to the gate line, a source electrode connected to the data line intersecting the gate line and the interlayer insulating film therebetween to form a pixel region, and a drain electrode connected to the pixel electrode formed in the pixel region It characterized in that it further comprises.

Then, the thin film transistor obtained by the manufacturing method of the said thin film transistor is provided.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate taken along the line Ι-Ι 'of FIG. 2.

2 and 3, a gate line 102 extends and extends in a first direction on a substrate, and a data line 104 intersecting with the gate line 102 to define a pixel region P is provided. It extends in a 2nd direction. In the pixel region P defined by the intersection of the gate wiring 102 and the data wiring 104, the thin film transistor 130 connected to the gate line 102 and the data line 104 according to the present invention is provided. . Here, although the thin film transistor 130 is formed of an N type or a P type, only a case where the thin film transistor is formed of an N type will be described below.

 The thin film transistor 130 charges the video signal to the pixel electrode 138 formed in the pixel region P. FIG. To this end, the thin film transistor 130 includes a gate electrode 134 formed by branching from the gate line 102, a source electrode 136 formed by branching from the data line 104, and a pixel contact penetrating through the passivation layer 158. The drain electrode 137 connected to the pixel electrode 138 through the hole 145 and the active layer 132 forming a channel between the source electrode 136 and the drain electrode 137 by the gate electrode 134. It includes. In addition, the semiconductor device may further include insulating layers 151 and 156 made of an inorganic insulating material for insulating each metal layer and the active layer 132.

The active layer 132 is formed of polycrystalline silicon on the substrate 114 while being connected from the bottom of the source electrode 136 to the bottom of the drain electrode 137. The gate electrode 134 connected to the gate line 102 overlaps the channel region 132C of the active layer 132 with the first and second gate insulating layers 152 and 153 interposed therebetween. The source electrode 136 and the drain electrode 137 are formed to be insulated from each other with the gate electrode 134 and the interlayer insulating layer 156 therebetween. The source electrode 136 and the drain electrode 137 are formed through the source contact hole 141 and the drain contact hole 143 which pass through the interlayer insulating layer 156 and the first and second gate insulating layers 152 and 153, respectively. The n + impurity is connected to each of the source region 132a and the drain region 132b of the active layer 132. In addition, the active layer 132 (Lightly Doped Drain (LDD) region (not shown) implanted with n- impurity between the channel region 132c and the source and drain regions 132a and 132b to reduce the off current. ) May be further provided.

The insulating layers 151 and 156 include an interlayer insulating layer 156 formed between the gate electrode 134 and the source / drain electrodes 136 and 137, and a gate insulating layer 151 formed between the interlayer insulating layer 156 and the substrate. The gate insulating film 151 may include a first gate insulating film 152 covering the top and side surfaces of the active layer 132, a second gate insulating film 153 formed on the first gate insulating film 152, and a second gate insulating film ( And a third gate insulating layer 154 formed on the 153.

An inorganic material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx) is used as the gate insulating film, and the first gate insulating film 152 and the third gate insulating film 154 preferably use a silicon oxide film (SiOx). Do. This is because polycrystalline silicon thin film transistors are easily induced by parasitic transistors due to coupling between gate and source / drain electrodes due to the incorporation of a driving circuit, because the parasitic transistor values are lower because the dielectric constant of silicon oxide is lower than that of silicon nitride. In addition, the silicon oxide film at the time of crystallization or activation has a wide energy gap, there is an advantage that there is no absorption for the laser beam. As the second gate insulating film 153, it is preferable to use a silicon nitride film having a stronger strength than that of the silicon oxide film so as to withstand the mechanical chemical polishing process to be described later. However, it is not limited thereto.

Here, the first gate insulating film 152 is formed of a silicon oxide film of 400 GPa or more, and the second gate insulating film 153 is formed of a silicon nitride film of 400 GPa or more, which is stronger than the first gate insulating film 152. The third gate insulating film 154 is formed of a silicon oxide film of 1000 Å or more, which is weaker than the second gate insulating film 153. The third gate insulating layer 154 is formed such that the top surface of the second gate insulating layer 153 is exposed without exposing the side inclined surface of the second gate insulating layer 153 to the outside in order to planarize after stacking. In this way, the gate insulating film 151 of the tapered region B is formed to be equal to or larger than the thickness of the other region of the gate insulating film, thereby ensuring sufficient breakdown voltage. In addition, the amount of charge in the tapered region B is less than the amount of charge in the upper portion of the channel portion 132C, thereby preventing the increase of the hump and the leakage current caused by the parasitic transistor. That is, even if the thickness of the active layer 132 increases and the inclination of the tapered region B increases, the third gate insulating layer 154 compensates for the gate insulating layer 151 that can be thinned in the tapered region B, thereby tapering. Insulation breakdown of the gate insulating film 130 in the region B can be prevented. As a result, the dielectric breakdown voltage characteristic of the gate insulating film is improved, the parasitic transistor effect can be reduced, and an increase in leakage current can be prevented, thereby solving all problems. This gate insulating film is not limited to three layers.

The second and third gate insulating layers 152 and 153 and the interlayer insulating layer 156 described above are source / drain contact holes 141 and 143 exposing the source region 132a and the drain region 132b doped with impurities of the active layer 132. )

The passivation layer 158 is formed over the interlayer insulating layer 156 and the entire surfaces of the source and drain electrodes 136 and 137, and the passivation layer 158 has the pixel contact hole 145 exposing the drain electrode 137. A pixel electrode 138 made of a transparent conductive material is formed in the pixel region on the passivation layer 158 through the pixel contact hole 145.

Next, the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention described above will be described in detail with reference to FIGS. 4A to 4H.

First, as shown in FIG. 4A, after depositing amorphous silicon on the front surface of the substrate 114 and performing a dehydrogenation process, the amorphous silicon layer is subjected to Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), and metal induced (MIC). By crystallization using Crystallization) or MILC (Matal Induced Lateral Crystallization) method to form a polycrystalline silicon layer. It is preferable that the polycrystalline silicon layer has a thickness of 500 kPa. The active layer 132 is formed by patterning the polycrystalline silicon layer by a photolithography process and an etching process. At this time, the tapered region B is formed so that the side surface of the active layer 132 is inclined, and when the slope of the tapered region B is gentle, the resistance may increase on the side surface of the active layer 132 so that the tapered region B may be increased. It is preferable that the inclination of) is 30 degrees or more. In addition, the etching of the polycrystalline silicon layer is preferably performed using dry etching which is excellent in etching uniformity and has low etching line width loss.

Subsequently, as shown in FIG. 4B, one or more gate insulating films including the first gate insulating film 152, the second gate insulating film 153, and the third gate insulating film 154 are sequentially deposited on the entire surface of the substrate 114. Deposition by the method.

Next, the third gate insulating film 154 is removed by the thickness of the convex portion 154S until the upper surface of the second gate insulating film 153 is exposed, and as shown in FIG. 4C, the third gate insulating film 154 is removed. Planarize the surface. In order to planarize the surface of the third gate insulating film 154, a method such as chemical mechanical polishing (hereinafter, referred to as CMP process) is used.

An inorganic material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx) is used as the gate insulating film, and the first gate insulating film 152 and the third gate insulating film 154 preferably use a silicon oxide film (SiOx). Do. This is because polycrystalline silicon thin film transistors are easily induced by parasitic transistors due to coupling between gate and source / drain electrodes due to the incorporation of a driving circuit, because the parasitic transistor values are lower because the dielectric constant of silicon oxide is lower than that of silicon nitride. In addition, the silicon oxide film at the time of crystallization or activation has a wide energy gap, there is an advantage that there is no absorption for the laser beam. As the second gate insulating film 153, it is preferable to use a silicon nitride film having a stronger strength than that of the silicon oxide film so as to withstand the mechanical chemical polishing process to be described later. However, it is not limited thereto.

Here, the thickness of the first gate insulating film 152 is 400 kPa or more, the thickness of the second gate insulating film 153 is 400 kPa or more, and the thickness of the third gate insulating film 154 is preferably 1000 kPa or more. After stacking the third gate insulating layer 154, the third gate insulating layer 154 is planarized to the uppermost surface of the second gate insulating layer 153 so that the side surface of the second gate insulating layer 153 is not exposed to the outside through the CMP process. The tapered region B is allowed to have a predetermined thickness. By doing so, the tapered region B is not formed thinner than the thickness of the other regions of the gate insulating film, thereby ensuring sufficient breakdown voltage. In addition, the amount of charge in the tapered region B is less than the amount of charge in the upper portion of the channel portion 132C, thereby preventing the increase of the hump and the leakage current caused by the parasitic transistor. That is, even if the thickness of the active layer 132 increases and the inclination of the tapered region B increases, the third gate insulating layer 154 compensates for the gate insulating layer 151 that can be thinned in the tapered region B, thereby tapering. Insulation breakdown of the gate insulating film 130 in the region B can be prevented. As a result, the dielectric breakdown voltage characteristic of the gate insulating film is improved, the parasitic transistor effect can be reduced, and an increase in leakage current can be prevented, thereby solving all problems. This gate insulating film is not limited to three layers.

Next, as shown in FIG. 4D, a gate metal layer such as Al or Al alloy is formed on the second gate insulating film 153, and then the gate metal layer is patterned by a photolithography process and an etching process to form an active layer 132. The gate electrode 134 is formed in the region overlapping with the gate electrode 134.

In addition, ion doping for implanting n + impurities into the active layer 132 is performed using the gate electrode 134 as a mask. The source region 132a and the drain region 132b of the non-overlapping active layer 132 are formed by ion doping. The source and drain regions 132a and 132b of the active layer 132 overlap with the gate electrode 134 to face the channel region 132c that is not ion-doped therebetween. Thereafter, the activation process of the doped active layer 132 is performed. This is because the active layer structure of the doped source / drain regions 132a and 132b is changed to amorphous due to the ion doping energy during ion doping, so as to restore it to the polycrystalline silicon state.

Next, as shown in FIG. 4E, an inorganic insulating material such as a silicon oxide film or a silicon nitride film is deposited on the active layer 132 and the gate electrode 134 subjected to the doping and activation processes to form the interlayer insulating film 156. Form. Subsequently, a mask process is performed to interlayer the first gate insulating layer and the second gate insulating layer 152 and 153 to expose a portion of the source / drain regions 132a and 132b in contact with the source and drain electrodes 136 and 137 of the active layer 132. Source / drain contact holes 141 and 143 are formed in the insulating layer 156 by dry etching or wet etching such as reactive etching, reactive ion beam etching, or the like.

Subsequently, as shown in FIG. 4F, a metal material such as Al or Cr is deposited on the entire surface of the interlayer insulating film 156, and a mask process is performed to form the source electrode 136 and the drain electrode 137. In this case, the source and drain electrodes 136 and 137 come into contact with the source / drain regions 132a and 132b of the active layer 132 through the source / drain contact holes 141 and 143, respectively. In this way, the polycrystalline silicon thin film transistor 130 is completed.

Thereafter, as illustrated in FIG. 4G, an inorganic material or an organic material is deposited on the entire surface of the substrate 114 on which the source and drain electrodes 136 and 137 are formed to form a protective film 158, and a mask process is performed to form a protective film ( The pixel contact hole 145 exposing the drain electrode 137 under the 158 is formed. Next, a transparent conductive material such as ITO is deposited on the passivation layer 158 including the pixel contact hole 145, and then a mask process is performed to form the pixel electrode 138 as illustrated in FIG. 4H. In this case, the pixel electrode 138 is connected to the drain electrode 137 through the pixel contact hole 145.

Meanwhile, although the thin film transistor according to the present invention has been described using a polycrystalline silicon thin film transistor as an example, the thin film transistor may be applied to an amorphous silicon thin film transistor. In addition, although the thin film transistor according to the present invention has been described using a thin film transistor for pixel switching as an example, the thin film transistor can be applied to a thin film transistor for a driving circuit, and the present invention can be applied to all flat panel display devices such as electroluminescent devices as well as liquid crystal display devices. It is possible.

As described above, the thin film transistor and the method of manufacturing the same according to the present invention are laminated with the multilayer insulating film in sequence, and the uppermost insulating film is flattened until the lower insulating film appears by the CMP process. Accordingly, the thickness of the gate insulating film in the tapered region is equal to or greater than the thickness of the other region, so that a sufficient breakdown voltage can be ensured, so that the breakdown of the gate insulating film in the tapered region can be prevented. In addition, the dielectric breakdown voltage characteristics of the gate insulating film can be improved, and the parasitic transistor effect can be reduced, thereby preventing an increase in the leakage current.

As a result, it is possible to prevent malfunction of the thin film transistor and to prevent display defects such as point defects, line defects, and luminance unevenness in the display device using the thin film transistors.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

Forming an active layer over the substrate; Stacking on the active layer to form a gate insulating film having a thickness difference according to a position such that a side surface of the active layer is thicker than the remaining area of the active layer; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film on the gate insulating film and the gate electrode; Forming a source electrode and a drain electrode on the interlayer insulating film. The method of claim 1, The forming of the gate insulating film may include sequentially stacking first to third gate insulating films on the substrate on which the active layer is formed; And removing a portion of the third gate insulating film to expose the top surface of the second gate insulating film. The method of claim 2, Removing a portion of the third gate insulating layer is a CMP process. The method of claim 2, And the second gate insulating film is formed of a material having a stronger strength than the first and third gate insulating films. The method of claim 4, wherein The first gate insulating film is made of a silicon oxide film, The second gate insulating film is made of a silicon nitride film, And the third gate insulating film is formed of a silicon oxide film. The method of claim 1, And the gate insulating film is made of an inorganic material. An active layer forming a channel and formed on the substrate; And a gate insulating layer formed on the active layer, the gate insulating layer having a thickness difference according to a position such that a side surface of the active layer is thicker than a thickness of the remaining area of the active layer. The method of claim 7, wherein First and second gate insulating layers formed to sequentially cover the active layer and having convex portions in a region corresponding to the active layer; And a third gate insulating film formed on the second gate insulating film in the remaining region excluding the convex portion of the second gate insulating film to planarize the substrate. The method of claim 8, The second gate insulating film is formed of a material having a stronger strength than the first and third gate insulating film. The method of claim 8, The first gate insulating film is made of a silicon oxide film, The second gate insulating film is made of a silicon nitride film, And the third gate insulating film is formed of a silicon oxide film. The method of claim 7, wherein A gate electrode connected to the gate line; A source electrode connected to the data line crossing the gate line with the interlayer insulating layer interposed therebetween to form a pixel region; And a drain electrode connected to the pixel electrode formed in the pixel region. The thin film transistor obtained by the method of any one of Claims 1-6.

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