JPH0575125A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH0575125A JPH0575125A JP23291791A JP23291791A JPH0575125A JP H0575125 A JPH0575125 A JP H0575125A JP 23291791 A JP23291791 A JP 23291791A JP 23291791 A JP23291791 A JP 23291791A JP H0575125 A JPH0575125 A JP H0575125A
- Authority
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- Prior art keywords
- film
- active layer
- silicon
- silicon nitride
- deposited
- Prior art date
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタに関
する。FIELD OF THE INVENTION The present invention relates to thin film transistors.
【0002】[0002]
【従来の技術】エレクトロルミネッセンス,発光ダイオ
−ド,プラズマ,蛍光表示,液晶等を用いた表示デバイ
スは、表示部の薄型化が可能であるため、計測機器,事
務機器やコンピュ−タ等の端末表示装置或いは特殊な表
示装置への用途として要求が高まっている。これらの中
で、近年、薄膜トランジスタ(TFT)をスイッチング
素子として用いたアクティブマトリックス型液晶表示装
置が注目されている。このような液晶表示装置では、一
般に、画面が対角10インチ以上の大画面となると、ガ
ラス基板を用いてTFT−LCDを作成し、生産コスト
の上昇を抑制している。このため、TFTの活性層とし
ては低温での成膜が可能なアモルファスシリコン(a‐
Si)膜が用いられている。2. Description of the Related Art A display device using electroluminescence, light emitting diode, plasma, fluorescent display, liquid crystal or the like can have a thin display portion, and is therefore a terminal for measuring instruments, office equipment, computers and the like. There is an increasing demand for use as a display device or a special display device. Among these, in recent years, an active matrix type liquid crystal display device using a thin film transistor (TFT) as a switching element has been receiving attention. In such a liquid crystal display device, generally, when the screen becomes a large screen with a diagonal of 10 inches or more, a TFT-LCD is produced using a glass substrate to suppress an increase in production cost. Therefore, as the active layer of the TFT, amorphous silicon (a-
Si) film is used.
【0003】しかしながら、活性層としてa‐Si膜を
用いたTFT−LCDは、大画面化や高精細化には不向
きであるという問題があった。これはTFT−LCDの
大画面化や高精細化には高速動作のTFTを必要とする
からである。即ち、活性層としてa‐Si膜を用いたT
FTは、その電界効果移動度が、活性層として単結晶膜
や高温で成膜した多結晶シリコン膜を用いたTFTのそ
れに比べて小さいという欠点があった。However, the TFT-LCD using an a-Si film as an active layer has a problem that it is not suitable for a large screen and high definition. This is because the TFT-LCD requires a high-speed operation in order to have a large screen and high definition. That is, T using an a-Si film as an active layer
The FT has a drawback that its field effect mobility is smaller than that of a TFT using a single crystal film or a polycrystalline silicon film formed at high temperature as an active layer.
【0004】また、a‐Si膜の代わりに、微細結晶シ
リコン膜を活性層に用いた低温でのTFTの形成方法が
提案されているが(J.Kanicki et a
l.:Mat.Res.Soc.Symp.Proc.
Vol.149,p.173)、その電界効果移動度は
活性層としてa‐Siを用いたTFTのそれと同程度で
あるため、このようなTFTを用いてもTFT−LCD
の大画面化や高精細化にはつながらなかった。A method of forming a TFT at a low temperature using a microcrystalline silicon film as an active layer instead of the a-Si film has been proposed (J. Kanicki et a.
l. : Mat. Res. Soc. Symp. Proc.
Vol. 149, p. 173), since its field effect mobility is similar to that of a TFT using a-Si as an active layer, even if such a TFT is used, a TFT-LCD
It did not lead to a larger screen or higher definition.
【0005】[0005]
【発明が解決しようとする課題】上述の如く、活性層と
してa‐Si膜や微細結晶シリコン膜を用いた従来のT
FTでは、電界効果移動度が小さく、TFT−LCDの
大画面化や高精細化が困難であるという問題があった。
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、電界効果移動度が大きいTFTを提
供することにある。As described above, the conventional T using the a-Si film or the fine crystalline silicon film as the active layer is used.
The FT has a problem that the field effect mobility is small and it is difficult to increase the screen size and the definition of the TFT-LCD.
The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a TFT having a large field effect mobility.
【0006】[0006]
【課題を解決するための手段】本発明の骨子は、通常現
われない電子の波動性が強く見られように、活性層の電
子(正孔)状態を量子化することにある。The essence of the present invention is to quantize the electron (hole) state of the active layer so that the wave nature of the electron, which normally does not appear, is strongly observed.
【0007】即ち、上記の目的を達成するために、本発
明のTFTは、基板上に形成された微結晶或いは多結晶
シリコンからなる薄膜とバンドギャップが前記薄膜のそ
れより大きい薄膜とが交互に積層されてなる活性層と、
この活性層に接合するソ−ス・ドレイン電極と、前記活
性層の上部又は下部にゲ−ト絶縁膜を介して配設された
ゲ−ト電極とを備えていることを特徴とする。In other words, in order to achieve the above-mentioned object, the TFT of the present invention comprises thin films made of microcrystalline or polycrystalline silicon formed on a substrate and thin films having a band gap larger than that of the thin films. An active layer formed by stacking,
A source / drain electrode joined to the active layer and a gate electrode disposed above or below the active layer via a gate insulating film are provided.
【0008】また、上記TFTの製造方法は、基板上に
形成された活性層と、この活性層に接合するソ−ス・ド
レイン電極と、前記活性層の上部又は下部にゲ−ト絶縁
膜を介して配設されたゲ−ト電極とを有する薄膜トラン
ジスタの製造方法において、光CVD法を用いて微結晶
或いは多結晶シリコンからなる薄膜とバンドギャップが
前記薄膜のそれより大きい薄膜とを交互に基板上に堆積
して多層膜を形成する工程と、この多層膜をパタ−ニン
グして前記活性層を形成する工程とを備えていることが
望ましい。Further, in the above-mentioned TFT manufacturing method, an active layer formed on a substrate, a source / drain electrode joined to the active layer, and a gate insulating film above or below the active layer. In a method of manufacturing a thin film transistor having a gate electrode arranged via a substrate, a thin film made of microcrystalline or polycrystalline silicon and a thin film having a bandgap larger than that of the thin film are alternately formed on a substrate by using a photo-CVD method. It is desirable to include a step of forming a multilayer film by depositing the multilayer film and a step of patterning the multilayer film to form the active layer.
【0009】[0009]
【作用】本発明では、活性層として微結晶或いは多結晶
シリコンからなる薄膜とバンドギャップが前記薄膜のそ
れより大きい薄膜とが交互に積層された多層膜を用いて
いる。この結果、活性層のキャリアが電子の場合、電子
は、微結晶或いは多結晶シリコンの伝導帯より高いエネ
ルギ−レベルに形成された新たなエネルギ−準位を走行
するため、粒界で捕獲されたり、散乱される確率が小さ
くなり、電界効果移動度が改善される。同様に活性層の
キャリアが正孔の場合、正孔は、微結晶或いは多結晶シ
リコンの価電子帯より低いエネルギ−レベルに形成され
た新たなエネルギ−準位を走行するため、電界効果移動
度が改善される。In the present invention, a multilayer film in which thin films made of microcrystalline or polycrystalline silicon and thin films having a band gap larger than that of the thin film are alternately laminated is used as the active layer. As a result, when the carrier in the active layer is an electron, the electron travels in a new energy level formed at an energy level higher than the conduction band of microcrystalline or polycrystalline silicon, so that the electron is trapped at the grain boundary. , The probability of scattering is reduced, and the field effect mobility is improved. Similarly, when the carrier of the active layer is a hole, the hole travels to a new energy level formed at an energy level lower than the valence band of microcrystalline or polycrystalline silicon, so that the field effect mobility is increased. Is improved.
【0010】[0010]
【実施例】以下、図面を参照しながら実施例を説明す
る。図1,図2は本発明の一実施例に係るTFTの製造
工程断面図である。Embodiments will be described below with reference to the drawings. 1 and 2 are cross-sectional views of manufacturing steps of a TFT according to an embodiment of the present invention.
【0011】まず、図1(a)に示す如く、ガラス等か
らなる透光性絶縁基板1上に厚さ約200nmのTa膜
或いはMoTa合金膜等の金属からなるゲ−ト電極2を
形成する。First, as shown in FIG. 1A, a gate electrode 2 made of a metal such as a Ta film or a MoTa alloy film having a thickness of about 200 nm is formed on a transparent insulating substrate 1 made of glass or the like. ..
【0012】次に図1(b)に示す如く、プラズマCV
D法を用い、第1のゲ−ト絶縁膜となる厚さ約300n
mのシリコン酸化膜3をゲ−ト電極2が覆われるように
基板1上に堆積し、続いて、同方法で第2のゲ−ト絶縁
膜となる厚さ約50nmのシリコン窒化膜4をシリコン
酸化膜3上に堆積する。Next, as shown in FIG. 1B, plasma CV
Using method D, the thickness of the first gate insulating film is about 300 n.
m of silicon oxide film 3 is deposited on the substrate 1 so as to cover the gate electrode 2, and then a silicon nitride film 4 having a thickness of about 50 nm to be a second gate insulating film is formed by the same method. Deposit on the silicon oxide film 3.
【0013】次に図1(c)に示す如く、光CVD法を
用い、活性層となる厚さ約2.5nmのアンド−プ微結
晶シリコン膜5aと厚さ約5nmのシリコン窒化膜5b
とをシリコン窒化膜4上に交互に積層し、10層程度の
多層膜を形成する。次いで光CVD法或いはプラズマC
VD法を用い、第1の保護膜となる厚さ約50nmのシ
リコン窒化膜6a,第2の保護膜となる厚さ約100n
mのシリコン酸化膜6bを多層膜上に順次堆積する。Next, as shown in FIG. 1C, an AND microcrystalline silicon film 5a having a thickness of about 2.5 nm and a silicon nitride film 5b having a thickness of about 5 nm to be an active layer are formed by using a photo-CVD method.
Are alternately laminated on the silicon nitride film 4 to form a multilayer film of about 10 layers. Then, photo CVD method or plasma C
Using the VD method, a silicon nitride film 6a having a thickness of about 50 nm to be a first protective film and a thickness of about 100 n to be a second protective film.
m silicon oxide film 6b is sequentially deposited on the multilayer film.
【0014】なお、活性層となるアンド−プ微結晶シリ
コン膜5a,シリコン窒化膜5bの成膜は、プラズマC
VD法を用いて行なっても良い。ただし、膜のダメ−ジ
の低減化の観点からは、光CVD法のほうが望ましい。The formation of the AND-microcrystalline silicon film 5a and the silicon nitride film 5b, which will be the active layers, is performed by plasma C
Alternatively, the VD method may be used. However, the photo-CVD method is more preferable from the viewpoint of reducing the damage of the film.
【0015】次に図2(a)に示す如く、シリコン窒化
膜6a,シリコン酸化膜6bをパタ−ニングして保護膜
6a,6bを形成した後、ケミカルドライエッチング
(CDE)等の等方性エッチングを用い、基板1側にい
くにつれて幅が大きくなるようにアンド−プ微結晶シリ
コン膜5aとシリコン窒化膜5bとの多層膜を加工し、
テ−パ状の活性層7を形成する。Next, as shown in FIG. 2A, the silicon nitride film 6a and the silicon oxide film 6b are patterned to form protective films 6a and 6b, and thereafter, isotropic properties such as chemical dry etching (CDE) are performed. By using etching, a multilayer film of the AND-microcrystalline silicon film 5a and the silicon nitride film 5b is processed so that the width becomes larger toward the substrate 1 side,
A taper-shaped active layer 7 is formed.
【0016】次に図2(b)に示す如く、例えば、プラ
ズマCVD法を用い、オ−ミックコンタクト層となる厚
さ約50nmのn+ 微結晶シリコン膜8を全面に堆積す
る。次いでスパッタリング法を用いて厚さ約50nmの
Mo膜,厚さ約500nmのAl膜をn+ 微結晶シリコ
ン膜8上に順次堆積してソ−ス・ドレイン電極となる積
層金属膜9を形成する。最後に、n+ 微結晶シリコン膜
8,積層金属膜9をパタ−ニングしてオ−ミックコンタ
クト層8,ソ−ス・ドレイン電極9を形成してTFTが
完成する。Next, as shown in FIG. 2 (b), for example, a plasma CVD method is used to form n + with a thickness of about 50 nm to be an ohmic contact layer. The microcrystalline silicon film 8 is deposited on the entire surface. Then, using a sputtering method, a Mo film with a thickness of about 50 nm and an Al film with a thickness of about 500 nm are n + A laminated metal film 9 to be a source / drain electrode is formed by sequentially depositing on the microcrystalline silicon film 8. Finally, n + The microcrystalline silicon film 8 and the laminated metal film 9 are patterned to form an ohmic contact layer 8 and a source / drain electrode 9 to complete a TFT.
【0017】以上の方法で得られたTFTの電界効果移
動度を調べたところ、活性層としてa‐Si膜を用いた
従来のTFTのそれより、約5倍大きかった。このよう
な結果が得られたのは次のように考えられる。When the field effect mobility of the TFT obtained by the above method was examined, it was about 5 times larger than that of the conventional TFT using an a-Si film as an active layer. The reason why such a result is obtained is considered as follows.
【0018】従来のTFTでは、活性層中の粒界に多数
のトラップが存在し、しかもバンド構造も単結晶のSi
膜のそれより複雑になっているので、粒界でキャリアが
捕獲されたり、散乱され易いので、電界効果移動度が小
さくなる。In the conventional TFT, a large number of traps exist at the grain boundaries in the active layer, and the band structure is single crystal Si.
Since the film is more complicated than that of the film, carriers are easily trapped or scattered at the grain boundaries, and the field effect mobility is reduced.
【0019】一方、本実施例のTFTでは、薄いアンド
−プ微結晶シリコン膜5aとシリコン窒化膜5bとの積
層膜を活性層7に用いているので、微結晶シリコン膜5
aの伝導帯よりも高いエネルギ−レベルに新たなエネル
ギ−準位が形成される。この結果、電子は、新たなエネ
ルギ−準位を走行し、粒界で捕獲されたり、散乱される
確率が小さくなる。即ち、電子は波動として振る舞うよ
うになり、この結果、粒界等の障壁を通り越すのでその
影響を受けなくなり、電界効果移動度が大きくなる。On the other hand, in the TFT of this embodiment, since the laminated film of the thin AND-microcrystalline silicon film 5a and the silicon nitride film 5b is used for the active layer 7, the microcrystalline silicon film 5 is formed.
A new energy level is formed at an energy level higher than the conduction band of a. As a result, the electron travels to a new energy level, and the probability of being trapped or scattered at the grain boundary is reduced. That is, the electron behaves as a wave, and as a result, the electron passes through a barrier such as a grain boundary and is not affected by it, so that the field effect mobility increases.
【0020】更に、本実施例では、活性層7のソ−ス・
ドレイン電極側の端面形状をテ−パ状にしたので、活性
層7の厚み及びチャネル幅が従来のそれと同じであって
も、活性層7とオ−ミックコンタクト層8との接触面
積、即ち、活性層7とソ−ス・ドレイン電極9との実効
的な接触面積が大きくなるため、オ−ミックコンタクト
特性が改善されるという利点がある。次に本発明の他の
実施例に係るTFTについて説明する。本実施例のTF
Tが先の実施例のそれと異なる点は、シリコン窒化膜の
代わりにp型のアモルファスSiC膜を用いて多層膜を
形成したことにある。Further, in this embodiment, the source of the active layer 7
Since the end face shape on the drain electrode side is tapered, even if the active layer 7 has the same thickness and channel width as those of the conventional one, the contact area between the active layer 7 and the ohmic contact layer 8, that is, Since the effective contact area between the active layer 7 and the source / drain electrode 9 becomes large, there is an advantage that the ohmic contact characteristics are improved. Next, a TFT according to another embodiment of the present invention will be described. TF of this embodiment
The difference of T from that of the previous embodiment is that a p-type amorphous SiC film was used instead of the silicon nitride film to form the multilayer film.
【0021】このような構成のTFTでも、p型のアモ
ルファスSiC膜のバンドギャップの方が微結晶シリコ
ン膜のそれより大きいため、先の実施例と同様な効果が
得られる。Even in the TFT having such a structure, the band gap of the p-type amorphous SiC film is larger than that of the microcrystalline silicon film, so that the same effect as that of the previous embodiment can be obtained.
【0022】更に、本実施例では、見かけ上活性層全体
がp型の半導体層となるため、オ−ミックコンタクト層
と活性層とがpn接合を形成し、これによりオフ電流が
小さくなるという利点がある。Further, in this embodiment, since the entire active layer apparently becomes a p-type semiconductor layer, an pn junction is formed between the ohmic contact layer and the active layer, which has the advantage of reducing the off current. There is.
【0023】なお、本発明は上述した実施例に限定され
るものではない。例えば、上記実施例では、活性層に微
結晶シリコン膜を用いたが、その代わりに多結晶シリコ
ン膜を用いて活性層を形成しても良い。また、上記実施
例では逆スタガ−型のTFTの場合について説明した
が、本発明は、スタガ−型やコプレ−ナ型などのTFT
にも適用できる。その他、本発明の要旨を逸脱しない範
囲で、種々変形して実施できる。The present invention is not limited to the above embodiment. For example, although the microcrystalline silicon film is used for the active layer in the above embodiment, a polycrystal silicon film may be used for forming the active layer instead. In addition, in the above embodiment, the case of the inverted stagger type TFT has been described, but the present invention is a stagger type or coplanar type TFT.
Can also be applied to. Besides, various modifications can be made without departing from the scope of the present invention.
【0024】[0024]
【発明の効果】以上詳述したように本発明によれば、微
結晶或いは多結晶シリコンからなる薄膜とバンドギャッ
プが前記薄膜のそれより大きい薄膜との積層膜を活性層
に用いている。この結果、活性層中の電子は、微結晶或
いは多結晶シリコンの伝導帯より高いエネルギ−レベル
に形成された新たなエネルギ−準位を走行する。したが
って、粒界で捕獲されたり、散乱される確率が小さくな
るため、電界効果移動度の大きいTFTが得られる。As described above in detail, according to the present invention, a laminated film of a thin film made of microcrystalline or polycrystalline silicon and a thin film having a band gap larger than that of the thin film is used as an active layer. As a result, the electrons in the active layer travel to a new energy level formed at an energy level higher than the conduction band of microcrystalline or polycrystalline silicon. Therefore, the probability of being trapped or scattered at the grain boundaries is reduced, and a TFT having a high field effect mobility can be obtained.
【図1】本発明の一実施例に係るTFTの製造工程断面
図。FIG. 1 is a sectional view of a manufacturing process of a TFT according to an embodiment of the present invention.
【図2】本発明の一実施例に係るTFTの製造工程断面
図。FIG. 2 is a sectional view of a manufacturing process of a TFT according to an embodiment of the present invention.
1…透光性絶縁基板、2…ゲ−ト電極、3…シリコン酸
化膜(第1のゲ−ト絶縁膜)、4…シリコン窒化膜(第
2のゲ−ト絶縁膜)、5a…アンド−プ微結晶シリコン
膜、5b…シリコン窒化膜、6a…シリコン窒化膜(第
1の保護膜)、6b…シリコン酸化膜(第2の保護
膜)、7…活性層、8…n+ 微結晶シリコン膜(オ−ミ
ックコンタクト層)、9…積層金属膜(ソ−ス・ドレイ
ン電極)。1 ... Transparent insulating substrate, 2 ... Gate electrode, 3 ... Silicon oxide film (first gate insulating film), 4 ... Silicon nitride film (second gate insulating film), 5a ... AND -P microcrystalline silicon film, 5b ... Silicon nitride film, 6a ... Silicon nitride film (first protective film), 6b ... Silicon oxide film (second protective film), 7 ... Active layer, 8 ... N + Microcrystalline silicon film (ohmic contact layer), 9 ... Laminated metal film (source / drain electrode).
Claims (1)
リコンからなる薄膜とバンドギャップが前記薄膜のそれ
より大きい薄膜とが交互に積層されてなる活性層と、 この活性層に接合するソ−ス・ドレイン電極と、 前記活性層の上部又は下部にゲ−ト絶縁膜を介して配設
されたゲ−ト電極とを有することを特徴とする薄膜トラ
ンジスタ。1. An active layer formed by alternately laminating thin films made of microcrystalline or polycrystalline silicon formed on a substrate and thin films having a bandgap larger than that of the thin film, and a soft layer bonded to the active layer. -A thin film transistor having a source / drain electrode and a gate electrode disposed above or below the active layer via a gate insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23291791A JPH0575125A (en) | 1991-09-12 | 1991-09-12 | Thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23291791A JPH0575125A (en) | 1991-09-12 | 1991-09-12 | Thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0575125A true JPH0575125A (en) | 1993-03-26 |
Family
ID=16946868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23291791A Pending JPH0575125A (en) | 1991-09-12 | 1991-09-12 | Thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0575125A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100657387B1 (en) * | 1999-10-18 | 2006-12-19 | 샤프 가부시키가이샤 | Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor |
JP2007511907A (en) * | 2003-11-14 | 2007-05-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Low-power multichannel CMOSFET with fully depleted quantum well |
WO2009063606A1 (en) * | 2007-11-15 | 2009-05-22 | Sharp Kabushiki Kaisha | Thin film transistor, method for manufacturing thin film transistor, and display device |
CN102308389A (en) * | 2009-02-04 | 2012-01-04 | 夏普株式会社 | Semiconductor device |
-
1991
- 1991-09-12 JP JP23291791A patent/JPH0575125A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100657387B1 (en) * | 1999-10-18 | 2006-12-19 | 샤프 가부시키가이샤 | Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor |
JP2007511907A (en) * | 2003-11-14 | 2007-05-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Low-power multichannel CMOSFET with fully depleted quantum well |
WO2009063606A1 (en) * | 2007-11-15 | 2009-05-22 | Sharp Kabushiki Kaisha | Thin film transistor, method for manufacturing thin film transistor, and display device |
CN102308389A (en) * | 2009-02-04 | 2012-01-04 | 夏普株式会社 | Semiconductor device |
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