JPH02250037A - Production of active matrix substrate and production of display device - Google Patents

Abstract

PURPOSE:To allow the use of an exposing machine with does not require a registering mechanism, etc., and is more inexpensive and to reduce costs by executing photolithography with gate electrodes or the gate electrodes and island-shaped conductor layers as a mask. CONSTITUTION:The formation of the semiconductor layers is executed by depositing the semiconductor layer of about <=1,500Angstrom thickness on an insulator layer 22, applying a positive type photoresist 24 on this semiconductor layer 23, and further, irradiating the resist with light from the rear surface of a substrate 20, developing the resist, and selectively removing the exposed parts of the semiconductor layer. The photolithography is, therefore, executable with the gate electrodes 21 or the gate electrodes 21 and the island-shaped conductor layers 24 as the mask at the time of forming the patterns of the semiconductor layers. The use of the more inexpensive exposing machine which does not require the registering mechanism, etc., is allowed in this way and the lower cost and the higher yield are obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a display device used in a liquid crystal television for video display, a display for a computer terminal, etc., and a method for manufacturing the same, and particularly relates to an active matrix substrate used therein and a method for manufacturing the same. It is something.

Conventional technology In recent years, expectations for flat image display devices have been increasing.
In particular, research and development in the field of flat displays using liquid crystals is extremely active. Among these, active matrix type liquid crystal display elements, which combine an active matrix substrate in which active elements are arranged in a two-dimensional matrix and a liquid crystal, are being commercialized and are viewed as promising. FIG. 9 shows its equivalent circuit, and 18 is an M I S (Metal
-1nsulator-Se1conductor)
) transistor, 19 is a liquid crystal cell, 4 is a scanning signal line, 10
is the video signal line. A gate signal is sequentially applied to the scanning signal line 4 so that the MIS transistor 18 is turned on, and a video signal corresponding to the gate 1 line is written from the video signal line 10 to the liquid crystal cell 19. Line sequential scanning provides the same function as a CRT. The transistor 18 is manufactured using single crystal silicon, polycrystalline silicon, amorphous silicon, a compound semiconductor, or the like as a semiconductor layer. Here, a method for manufacturing an active matrix substrate and a liquid crystal display device will be described in which amorphous silicon, which is said to be relatively easy to reduce cost and increase in area, is used as a semiconductor layer. FIG. 7 shows a plan view of this conventional example, and FIG. 8 is a schematic cross-sectional view of a unit picture element of an active matrix liquid crystal display device. It also serves as a linear sectional view.

First, as a transparent conductive layer 2 which becomes a picture element electrode on a glass plate IA, for example, ITO (Indlum-TIn-Oxi) is used.
de) is selectively deposited, and then silicon oxide, for example, is deposited over the entire surface as a first transparent insulating layer 3.

Next, a first metal layer 4 serving as a gate electrode and a scanning signal line is formed.
For example, Cr is selectively deposited. Thereafter, for example, a silicon nitride layer is formed as a second transparent insulating layer 5 which becomes a gate insulating layer on the entire surface by plasma CVD method, and a first semiconductor layer which is mainly composed of amorphous silicon and contains almost no impurity as a donor or acceptor. 6 is deposited on the entire surface, and then a silicon nitride layer is selectively deposited as a semiconductor protective layer 7 by plasma CVD.

In order to improve the ohmic properties of the electrical connection between the first semiconductor layer 6 and the second metal layer 10.12, the main component is amorphous silicon, and a high concentration of impurities such as P or As as a donor or acceptor is added. A second semiconductor layer 8 is deposited over the entire surface.

Then, the first and second semiconductor layers are subjected to ordinary photolithography using the same mask to form a resist pattern, and patterned into island shapes by etching. Furthermore, a resist pattern of openings 9 is formed on the silicon nitride layer 5 as the second transparent insulating layer and the silicon oxide layer 3 as the first transparent insulating layer by a normal photolithography method, and a resist pattern is formed using, for example, a parallel plate type glue. Part of the first transparent conductive layer 2 is exposed by active ion etching. At this time, although not shown, an opening is also formed in the silicon nitride layer 5 on the scanning signal line 4 at the end of the thin film transistor array. A second metal layer 10 that also serves as the source of the video signal line and the MIS) transistor, and a second metal layer 12 that connects the drain of the MIS) transistor and the first transparent conductive layer 2 via the opening 9 For example, Al is selectively deposited.

At this time, the lead electrode of the scanning signal line 2 is also formed simultaneously through the opening at the end of the thin film transistor array described above.

Finally, using the second metal layers 10 and 12 as a mask, only the second semiconductor layer is selectively removed using a fluoro-nitric acid based etching solution to complete the active matrix substrate.

After that, a polyimide resin is applied as a liquid crystal alignment film 14 to both the above-mentioned active matrix substrate and the glass substrate IB on which the second transparent electrode 15 is coated, and after hardening, an alignment treatment is performed. A liquid crystal display device is completed by sealing, for example, a twisted nematic liquid crystal between the two substrates as the liquid crystal 16, and further arranging polarizing plates 17 above and below.

Problems to be Solved by the Invention In order to manufacture the above active matrix substrate, 5 to 6 or more photolithography steps are required.
Moreover, it is necessary to prepare a photomask for each process and perform precise alignment. The manufacture of active matrix substrates for display devices requires microfabrication, so incidental equipment such as exposure machines and alignment mechanisms that have the same level of performance as those used for semiconductor processes are used. Therefore, the more times photolithography is performed using a mask, the more times a high-performance and expensive exposure machine is used, which increases the cost of the active matrix substrate. In addition, the more times photolithography is performed, the more
Yield also decreases.

In view of the above problems, the present invention provides a method of manufacturing an active matrix substrate at a lower cost by reducing the number of photolithography steps.

Means for Solving the Problems A step of forming a first conductive layer in which a non-transparent conductive material is selectively deposited on a transparent substrate; An active matrix substrate comprising a step of covering a conductive layer with an insulating layer, a step of covering a specific region on the insulating layer with a semiconductor layer, and a step of forming a pair of second conductive layers partially overlapping with the semiconductor layer. In the manufacturing method, the step of forming the semiconductor layer includes a step of depositing a semiconductor layer having a thickness of approximately 1500A or less on the insulator layer, a step of applying a positive photoresist on the semiconductor layer, and a step of applying a positive photoresist on the semiconductor layer; This is performed by a step of irradiating light from the back surface of the substrate (hereinafter referred to as a back surface exposure step), a step of developing the resist, and a step of selectively removing and forming the exposed portion of the semiconductor layer.

Effect According to the above method, when forming a pattern of a semiconductor layer, photolithography can be performed using the gate electrode or the gate electrode and the island-like conductor layer as a mask, so there is no need for an alignment mechanism, etc. An inexpensive exposure machine can be used, and the long exposure time, which is a major drawback of back side exposure, can be shortened. Furthermore, since it is possible to reduce the number of times of photolithography in some cases, it is possible to reduce the cost and increase the yield of the active matrix substrate.

Example The present invention will be described in detail below with reference to the drawings.

Embodiment 1 FIG. 1 shows a first embodiment of the present invention step by step.

A conductive thin film such as CR is deposited on a light-transmissive substrate, such as a #7°59 glass substrate 20 manufactured by Corning Co., by sputtering, and a desired patterning is performed to form a gate electrode 21 (see Fig. 1). a)). By the plasma CVD method, for example, silicon nitride (hereinafter abbreviated as SiN) is used as the gate insulator layer 22, and amorphous silicon (hereinafter abbreviated as a-8i) is used as the first semiconductor layer 23 containing almost no impurities. The film is deposited to a thickness of 1000A, and then, as the second semiconductor layer 24 containing impurities, a-8T (hereinafter abbreviated as n◆-a-8i) doped with phosphorus is continuously deposited to a thickness of 500A. After that, a positive photoresist 29 is applied (FIG. 1(b)). After pre-bataizing the resist, ultraviolet light 25 is irradiated from the back surface of the transparent substrate 1 using the gate electrode 21 as a mask to expose the resist. However, the ultraviolet light transmittance of a-8i is extremely low, and moreover, the light absorption rate increases exponentially with the film thickness. Therefore, the biggest problem with back side exposure is the time required for the exposure. Therefore, when mass production is taken into account, throughput is the biggest issue. In order to improve the throughput, the present inventors conducted detailed studies on three points: (a) the wavelength of the light source, (b) optimization of the resist film thickness, and (c) optimization of the a-8t film thickness.

Regarding (a), in the case of exposure from the back side, the resist is exposed and exposed to ultraviolet light through the glass substrate or the a-8t semiconductor layer. FIG. 3 shows the spectral transmittance of #7059 glass substrate manufactured by Corning Inc. and a-8i as an example of the glass substrate. From this spectral transmittance curve, it is desirable to use ultraviolet light with a wavelength as long as possible as the exposure light source wavelength. In addition, considering the efficiency of using ultraviolet light, we used 438 nm (g-line), 405 nm from the long wavelength side of a high-pressure mercury lamp as an exposure light source.
A three-wavelength mixed light source (power: 250 W) of 365 nm (tX-ray) and 365 nm (i-line) was used.

As the resist material in (b), 0FPR-800 manufactured by Tokyo Ohka Co., Ltd. was used as an example. FIG. 4 shows the dependence of resist film thickness and exposure time. From this result, it was found that the resist film thickness and the time required for exposure are almost proportional. The resist film thickness was selected to be about 1.3 μm in consideration of resist pinholes and the like.

Regarding the a-8i film thickness in (C), since the transmittance decreases exponentially with respect to the film thickness, a slight difference in film thickness greatly affects the exposure time. Therefore, it is desirable to make the a-8i film thickness as thin as possible. However, in the two-mask configuration, the active layer of phosphorus atoms (n''-a-8i;
n・-a-8i formed by diffusion of P into 1-a-8i
It is necessary to ensure that the final layer (including the layer) is removed reliably. Therefore, the concentration and activation rate of phosphorus atoms diffused from n·-a-8t into 1-a-8t, and the OFF current at that time were investigated.

FIG. 5 shows the results of measuring and quantifying the diffusion of phosphorus atoms in n◆-a-8i into 1-a-3i by secondary ion mass spectrometry (SIMS). From this experiment, it was found that phosphorus atoms diffuse by about 1000A. Further, FIG. 6 shows the results of examining changes in the OFF current of the transistor by changing the phosphorus concentration in the channel portion by changing the etching depth of 1-a-81 in the channel portion. From the study of the OFF characteristics of this transistor, 1-a-8
The activation rate of phosphorus diffused in t is 1/104 or less compared to that in n"-a-8t, and even if phosphorus atoms diffused in 1-a-8i remain, the characteristics of the device are affected. It was found that the a-8i did not significantly deteriorate the
The 1-a-8i film thickness was determined to be 10 by taking into account process margins such as variations in film thickness and dry etching uniformity.
It was set to about 00A.

Also, the film thickness of n◆-a-8t is about 500A,
Alternatively, it is preferable to set the current to about 200 A, as it is stated in Proceedings of the 1988 Spring Academic Conference of the Japan Society of Applied Physics, 30p-ZG-13, that the characteristics of the element will not deteriorate if the current is 20 OA or more. Therefore, a in this example
As the total film thickness of -8t film thickness, n・-a-8t/I-a-8
i=200A/1000A.

When the back side exposed substrate is developed as described above, the resist other than the portion corresponding to the gate electrode 21 is removed.

After the resist is boss-baked, the exposed portions of the first semiconductor layer 23 and the second semiconductor layer 24 are removed by etching using the resist as a mask (FIG. 1(C)). After removing the resist, for example ITO (Indlum-T
A thin film made of a transparent conductive material such as ln-Oxlde) is deposited and patterned to form a source electrode 26, a drain electrode 27, and a pixel electrode 28 all at once (see FIG. 1).
d)). Finally, n''''-a-8t in the channel portion is removed by reactive dry etching (hereinafter abbreviated as RIE) (FIG. 1(e)), and an active matrix substrate is completed. In this case, 1-a-8i is also about 50
The RIB is used to dig down to a depth of 0Afi.

As shown in this embodiment, by performing photolithography using the gate electrode 21 as a mask when forming the pattern of the semiconductor layer, a cheaper exposure machine that does not require an alignment mechanism etc. can be used. In addition, it is possible to reduce the number of photolithography operations.

In this embodiment, the picture element electrode, the source electrode, and the drain electrode are formed at the same time, but they may be formed separately.

In the above embodiment, Cr was used as the material for the gate electrode 21, but Ta, T 1% Mo, Ni
Any material used for the gate electrode of TPT, such as 1Ni-Cr alloy or silicides of these metals, can be used. Further, as the material for the gate insulator layer 22, silicon nitride, silicon oxide, metal oxide, etc. are also used.

Furthermore, although amorphous silicon was used as the material for the first and second semiconductor layers, polycrystalline silicon or recrystallized silicon may also be used without any problem.

Furthermore, as the material of the picture element electrode, In20a, Snu
Transparent conductive materials such as G or mixtures thereof can be used.

In addition, when forming the source electrode, the drain electrode, and the picture element electrode at the same time, a transparent conductive material such as n203.5n02 or a mixture thereof can be used as the material for the source and drain electrodes. When forming the source electrode and drain electrode and the picture element electrode separately, the material of the source electrode and the drain electrode is Al1Mo,
Ta1 Ti5Cr and silicides of these metals can be used. Note that in this case, the source and drain electrodes can be formed not only in a single layer but also in multiple layers to add redundancy.

Furthermore, the adhesion of the resist can be improved by using a resist adhesion enhancer such as hexamethyldisilazane (HMDS) before applying the positive photoresist.

Example 2 In this example, the film thickness of 1-a-8i in Example 1 was changed to 8
00A, n◆-a-8i with a film thickness of 20OA (not shown). After forming the source, drain and picture element electrodes all at once in the same manner as in Example 1, n''-
A's i and a part of 1-a-8t are to be removed, but in this case, since the film thickness of 1-a-8t is quite thin, a highly uniform etching is desired. In this example, a mixed gas of SF6 and CaCI Fs was used as the etching gas, the degree of vacuum was 70rs, the high frequency power was 5
Etched at 0W. At this time, the etching uniformity was ±6%, which was a sufficiently good uniformity. The etching amount is 30OA for all n-a-8i and 1-a-8i.
Etched.

In the above Example 2, SFa and C2 are used as the etching gas.
Although a mixed gas of CIF6 was used, as long as uniformity of about ±5% can be maintained, the above gases may be used alone, or CFJ, CHF5, CaFe, CCIa, C2C
A carbon fluoride gas or a carbon chloride gas such as I 2F may be used alone, or a mixed gas containing them may be used.

Example 3 FIG. 2 shows a cross-sectional view of a third embodiment of the invention.

First, an active matrix substrate is created in the same manner as in Example 1 or Example 2.

The above active matrix substrate and the opposing transparent electrode 31
A liquid crystal alignment film 32 made of polyimide, silicon oxide, etc. is formed on the opposing glass substrate 3o on which a sealing material 33 is deposited.
and a glass fiber or the like (not shown), and liquid crystal 34 is injected between them. Next, the opposing glass substrate 3o
Using as a mask, unnecessary gate insulator layer 22 on gate electrode 21 is removed, and finally polarizing plates 35 are placed before and behind both plates to complete the liquid crystal display device.

In the above embodiment, only the dielectric layer on the gate electrode was removed, but if the active matrix substrate is covered with a passivation layer, the source layer is removed on the gate electrode 21 at the same time using the same method. The passivation layer on pole 26 may also be removed.

Effects of the Invention According to the method for manufacturing an active matrix substrate of the present invention, by performing photolithography using the gate electrode or the gate electrode and the island-like conductive layer as a mask, a cheaper exposure machine that does not require an alignment mechanism etc. can be used. In addition, it is possible to reduce the number of photolithography steps, so it is possible to reduce costs, which is the biggest issue in active matrix liquid crystal display devices.

[Brief explanation of drawings]

Figure 1 shows the active material in the first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a liquid crystal display device using an active matrix substrate obtained in the first or second embodiment of the present invention, and FIG.
8i and Corning #7059 glass substrate, Figure 4 is a diagram showing the correlation between resist film thickness and backside exposure time, and Figure 5 is a diagram showing the correlation between resist film thickness and backside exposure time. Figure 6 is a diagram showing the correlation between the phosphorus concentration diffused into 1-a-8i and the OFF current of the transistor, and Figure 7 is a diagram showing the correlation between the phosphorus concentration diffused into 1-a-8i and the OFF current of the transistor. FIG. 8 is a schematic sectional view of an active matrix type liquid crystal display device constructed with a conventional active matrix substrate, and FIG. 9 is an equivalent circuit diagram of the same device. Glass substrate, IB... counter glass substrate, 2... picture element electrode, 3... first transparent insulating layer,
4...First metal layer (scanning signal line), 5...Second transparent insulating layer (gate insulating layer), 8...First semiconductor layer, 7...Semiconductor Protective layer, 8... Second semiconductor layer, 9... Opening, 10... Second metal layer (source and video signal line), 11... Transparent conductive layer (
source and video signal line), 12... second metal layer (
drain electrode), 13...transparent conductive layer (pixel electrode)
, 14... Alignment film, 15... Second transparent conductive layer, 16... Liquid crystal layer, 17... Polarizing plate, 18...
... MIS) transistor, 19 ... liquid crystal cell, 20
...Glass (transparent substrate), 21...Cr (gate electrode), 22...SiNx (gate insulator layer), 23...1-a-3t (first semiconductor layer),
24·-n”-a-8i (second semiconductor layer), 25··
...Ultraviolet light, 26...Source electrode, 27...Drain electrode, 28...Picture element electrode, 29...Positive photoresist) 30...Counter glass substrate, 31
...Counter transparent electrode, 32...Alignment film, 33...
...Sealing material, 34...Liquid crystal, 35...Polarizing plate. Name of agent Patent attorney Shigetaka Awano and one other person Engraving of Figure 1, page 7 Resist waist circumference (μm) Figure Too. Depth (λ) r00 Raw i Figure Figure 1! /l (cm-Reference diagram for funeral diagram procedure amendment writing method) Display of the case Patent application No. 70891 of 1999, Name of the invention Relationship between the person who amends the manufacturing method of an active matrix substrate and the manufacturing method of a display device Case Special person applying for permission

Claims (8)

[Claims] (1) Forming a first conductive layer on a transparent substrate by selectively depositing a non-transparent conductive material, and insulating the exposed surface of the substrate and the first conductive layer. A method for manufacturing an active matrix substrate comprising the steps of: covering a specific region on the insulating layer with a semiconductor layer; and forming a pair of second conductive layers that partially overlap the semiconductor layer. , the step of forming the semiconductor layer includes a step of depositing a semiconductor layer with a thickness of approximately 1500A or less on the insulator layer, a step of applying a positive photoresist on the semiconductor layer, and a step of applying light from the back surface of the substrate. A method for manufacturing an active matrix substrate, comprising the steps of irradiating, developing the resist, and selectively removing exposed portions of the semiconductor layer. (2) The step of forming a semiconductor layer covers a first semiconductor layer containing almost no impurities and a second semiconductor layer containing at least one element among P, As, B, or Al as impurities. and, after selectively depositing the second conductive layer, selectively removing an exposed portion of the second semiconductor layer and a portion of the first semiconductor layer. 2. The method of manufacturing an active matrix substrate according to claim 1. (3) Manufacturing the active matrix substrate according to claim 1, wherein the first semiconductor layer has a thickness of approximately 1000A or less, and the second semiconductor layer has a thickness of approximately 500A or less. Method. (4) The method for manufacturing an active matrix substrate according to claim 1, wherein in the light irradiation step, the wavelength of the light source used for light irradiation is at least one of 436 nm, 405 nm, and 365 nm. (5) The method for manufacturing an active matrix substrate according to claim 1, wherein the film thickness after removing a portion of the first semiconductor layer is approximately 300A or more. (6) The method of manufacturing an active matrix substrate according to claim 1, wherein the step of removing a part of the first semiconductor layer and the second semiconductor layer is performed by dry etching. (7) Dry etching is CF_4, CHF_3, CC
l_4, C_2F_6, C_2ClF_5, C_2Cl
Claim 6 characterized in that the reaction is carried out using a reaction gas containing at least one type of gas selected from _2F_4 and SF_6.
A method for manufacturing an active matrix substrate as described in . (8) A step of sandwiching a material having optical anisotropy between the active matrix substrate manufactured by the manufacturing method according to claim 1 and a counter substrate having a transparent electrode, and providing a polarizing plate on at least one of the two substrates. 1. A method of manufacturing a display device including a step of arranging the active matrix substrate, the method comprising a step of etching an exposed portion of an insulator layer of the active matrix substrate using the counter substrate as a mask.