JPS62143028A - Liquid crystal displaying device - Google Patents

Liquid crystal displaying device

Info

Publication number
JPS62143028A
JPS62143028A JP60284788A JP28478885A JPS62143028A JP S62143028 A JPS62143028 A JP S62143028A JP 60284788 A JP60284788 A JP 60284788A JP 28478885 A JP28478885 A JP 28478885A JP S62143028 A JPS62143028 A JP S62143028A
Authority
JP
Japan
Prior art keywords
insulating film
spacer
line
substrate
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60284788A
Other languages
Japanese (ja)
Other versions
JPH0612387B2 (en
Inventor
Koji Anada
幸治 穴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60284788A priority Critical patent/JPH0612387B2/en
Publication of JPS62143028A publication Critical patent/JPS62143028A/en
Publication of JPH0612387B2 publication Critical patent/JPH0612387B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To prevent the disconnection and shorting accident of both lines at a spacer position by extending an inter-layer insulating film on a substrate up to the position to overlap with a spacer in the vicinity of the substrate and leading out a gate line and a drain line respectively directly or a through hole from under the inter-layer insulating film at the spacer position to the external part. CONSTITUTION:An insulating film 12, which functions as the inter-layer insulating film of a drain line 15 and a gate electrode and acts as the gate insulating film of Tr, is extended up to the position of a spacer 40. A gate line 18 exists under the insulating film 12, led out from the edge of the insulating film 12 of the spacer 40 and forms a gate terminal GP. On the other hand, the drain line 15 is connected to a lower layer drain line 15' formed under the insulating film 12 through a contact hole H of the insulating film 12 at the terminal place of a displaying part surrounded by the spacer 40. The line 15' is led out from the lower direction of the insulating film 12 of the position of the spacer 40 and forms a drain terminal DP.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はマトリックス状の表示セグメントを有する液晶
表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a liquid crystal display device having a matrix of display segments.

(ロ)従来の技術 マトリックス状の表示セグメントを有する表示装置とし
ては、日経エレクトロニクス1984年1 月2日号の
記事「文書と画像表示をねらうフラット・バ、ネル・デ
ィスプレイ、に開示きれている様に液晶表示器、を用い
たもの、エレクトロ・ルミネッセンス表示器を用いたも
の、等各種の表示装置が存在するが、現在は低消費電力
大容量化が可能である点で液晶表示器の将来性が高く評
価されている。
(b) Conventional technology A display device having display segments in the form of a matrix is disclosed in an article in the January 2, 1984 issue of Nikkei Electronics titled "Flat panel display aimed at displaying documents and images." There are various display devices such as those using liquid crystal displays and those using electroluminescence displays, but currently the future potential of liquid crystal displays is that they can achieve low power consumption and large capacity. is highly rated.

斯様な液晶表示tA置の要部の平面図を第3図(a)に
示し、同図(b)にそのX−X線断面図を示す、これ等
の図に於いて、(10)は第1のガラス基板、 (11
)・・・は第1のガラス基板(10)上に窒化シリコン
からなる絶縁膜(12)を介して行列配!(約250x
600)された透明なITOからなるセグメント電極で
ある。 (13)・・・は上記セグメント電極(11)
(11)間隙の絶縁膜(12)上に縦方向に複数本並列
配置したアモルファスシリコン膜ラインであり、各セグ
メント電極(11)(11)・・・の左下方のスペース
に突設した半導体動作領域(14>(14)・・・が設
けられている。 (15)・・・は各アモルファスシリ
コン膜ライン(13)・・・上に配置されたアルミニウ
ム膜からなるドレインラインであり、上記各半導体動作
領域(14)(14)の左側辺上に重畳したドレイン電
極(16)(16)が突設されている。 (17)(1
7)・・・は各半導体動作領域(14)(14>・・・
の右側辺上に一部重畳したアルミニウム膜からなるソー
ス電極であり、その右側辺は絶縁膜(12)上で対応す
る各セグメント電極(11)(11)・・・の左下端部
と接続されている。 (18)・・・は上記セグメント
電極(1t)(U)・・・間隙位置を横方向に複数本並
列配置されて上記第1のガラス基板(10)と絶縁膜(
12)との居間に形成された金とクロムの2層膜からな
るゲートラインであり、該ライン(18)・・・には上
記各ソース電極(17)・・・とドレイン電極(16)
・・・との間隙位置の半導体動作領域(14)下のゲー
ト・電極(19)・・・が一体に突設きれている。即ち
、図中りで示すドレイン電M(16)・・・と、Sで示
すソース電極(17)・・・と、Gで示すゲート電極(
19)・・・と、これ等電極り、S、Gに結合している
アモルファスシーリフン膜からなる半導体動作領域(1
4)・・・箇所とに依って薄膜FET構成のスイッチン
グトランジスタが行列配置きれており、各セグメント(
11)(11)・・・は夫々に対応したこのスイッチン
グトランジスタを介してドレインライン(15)・・・
に接続されるのである。 (100)は上記各セグメン
ト電極(11)(11)・・・上記ドレインライン(1
5)・・・及び上記スイ・シチングトランジスタ箇所を
一面に被覆した配向膜である。
FIG. 3(a) shows a plan view of the main parts of such a liquid crystal display tA, and FIG. 3(b) shows a cross-sectional view taken along the line X-X. is the first glass substrate, (11
)... are arranged in rows and columns on the first glass substrate (10) via an insulating film (12) made of silicon nitride! (about 250x
600) is a segment electrode made of transparent ITO. (13) ... is the above segment electrode (11)
(11) Amorphous silicon film lines arranged vertically in parallel on the insulating film (12) in the gap, and a semiconductor film line protruding into the space at the lower left of each segment electrode (11) (11)... A region (14>(14)... is provided. (15)... is a drain line made of an aluminum film disposed on each amorphous silicon film line (13)... Overlapping drain electrodes (16) (16) are provided protrudingly on the left side of the semiconductor operating regions (14) (14). (17) (1
7)... are each semiconductor operating region (14) (14>...
The source electrode is made of an aluminum film that partially overlaps the right side of the electrode, and the right side is connected to the lower left end of the corresponding segment electrode (11) (11) on the insulating film (12). ing. (18)... are the segment electrodes (1t) (U)...a plurality of segment electrodes (1t) (U) are arranged in parallel in the lateral direction with respect to the first glass substrate (10) and the insulating film (
12) is a gate line made of a two-layer film of gold and chromium formed in the living room, and the line (18)... has the above-mentioned source electrodes (17)... and drain electrodes (16).
The gate/electrode (19) below the semiconductor operating region (14) at the gap position between the gate electrode and the gate electrode (19) is integrally provided in a protruding manner. That is, the drain electrode M (16) shown in the figure, the source electrode (17) shown S, and the gate electrode (G
19) ... and the semiconductor operating region (1
4)...Switching transistors with thin film FET configuration are arranged in rows and columns depending on the location, and each segment (
11) (11)... are connected to the drain line (15)... through the corresponding switching transistors.
It is connected to. (100) is each of the segment electrodes (11) (11)...the drain line (1
5)...and an alignment film that covers the entire area of the switching transistor.

一方、 (20)は第2のガラス基板であり、その下面
、即ち第1のガラス基板(10)と対向する面には一面
に共通電極(21)、配向膜(200)が順次形成され
ている。
On the other hand, (20) is a second glass substrate, and a common electrode (21) and an alignment film (200) are sequentially formed on the lower surface thereof, that is, the surface facing the first glass substrate (10). There is.

(30)は上記両基板(10)、(20)間即ち両配内
膜(100)、(200)間に封入された液晶物質であ
り、各マトリックスセグメント毎に上記スイッチングド
  ランジスタがONする事に依って表示信号、即ち液
晶励起電圧が印加される第1のガラス基板(10)のセ
グメント電極(11)箇所の液晶物質(30)が電気光
学効果を引き起こす事となる。
(30) is a liquid crystal substance sealed between the two substrates (10) and (20), that is, between the inner films (100) and (200), and the switching transistor is turned on for each matrix segment. Accordingly, the liquid crystal material (30) at the segment electrode (11) of the first glass substrate (10) to which the display signal, that is, the liquid crystal excitation voltage is applied, causes an electro-optic effect.

(ハ) 発明が解決しようとする問題点上述の如き液晶
表示装置は、カラーテレビ等の大型の表示装置に用いら
れる為に、第1及び第2の基板(10)(20)の各周
辺部の平坦度に歪みが生じやすい事から、この周辺部位
置で上記ゲートライン(18)並びにドレインライン(
15)の外部への引き出し線に断線事故や短絡事故が生
じる惧れがあった。具体的には、第4図のドレインライ
ン(15)に沿った断面図に示す、第1の基板(10)
の周囲にはドレインライン(15)あるいはゲートライ
ン〈18)を引き出して端子を形成する端子部(10’
)が延在しており、第2の基板(20〉の周辺部と第1
の基板(10)との間には両基板(10)(20)間の
間隔を規定すると共に液晶物質(30)を封入する為の
スペーサ(40)が設けられている。ここで、ドレイン
ライン(15)は上記端子部(10’)にまで延長きれ
ドレイン端子(DP)となるが、上記スペーサ(40)
位置では絶縁膜(12)、アモルファスシリコン膜ライ
ン(13)、並びに配向膜(200)は存在せず、露出
した状態でスペーサ(40)と接している。
(c) Problems to be Solved by the Invention Since the liquid crystal display device as described above is used for a large display device such as a color television, each peripheral portion of the first and second substrates (10) and (20) is Since distortion is likely to occur in the flatness of the gate line (18) and drain line (
15), there was a risk of a disconnection or short circuit occurring in the lead wire to the outside. Specifically, the first substrate (10) shown in the cross-sectional view along the drain line (15) in FIG.
There is a terminal part (10') around which a drain line (15) or gate line (18) is drawn out to form a terminal.
) extends between the periphery of the second substrate (20〉) and the first substrate (20〉).
A spacer (40) is provided between the substrate (10) and the substrate (10) to define the distance between the substrates (10) and (20) and to seal in the liquid crystal material (30). Here, the drain line (15) is extended to the terminal part (10') and becomes a drain terminal (DP), but the spacer (40)
At this position, the insulating film (12), the amorphous silicon film line (13), and the alignment film (200) are not present and are in contact with the spacer (40) in an exposed state.

一方、第2の基板(20)側に於いても、共通電極(2
1)が露出した状態でスペーサ(40)と接している。
On the other hand, also on the second substrate (20) side, the common electrode (2
1) is in contact with the spacer (40) in an exposed state.

従って、エポキシ系の接着剤からなるスペーサ(40)
にて、両基板(10)(20)を接着処理する際の加圧
時に、この箇所での両基板(10)(20)が接触し、
ドレインライン(15)と共通電極(21)とに剥離や
短絡事故が生じる惧れがあった。
Therefore, the spacer (40) made of epoxy adhesive
At this point, both substrates (10) and (20) come into contact during pressurization when bonding them together,
There was a risk that peeling or short-circuiting would occur between the drain line (15) and the common electrode (21).

(ニ)問題点を解決するための手段 本発明の液晶表示装置に於いては、ゲートラインとドレ
インラインを絶縁する為の層間絶縁膜は第1の基板の周
辺部のスペーサに重畳きれる位置まで延在され、上記ゲ
ートラインあるいはドレインラインの内の下層のライン
の端部をスペーサ位置の層間絶縁膜下から外部へ引き出
すと共に、上記ドレインラインあるいはゲートラインの
内の上層のラインの端部を層間絶縁膜のコンタクトホー
ルを介して層間絶縁膜下に延長し、スペーサ位置の層間
絶縁膜下から外部へ引き出される。
(d) Means for solving the problem In the liquid crystal display device of the present invention, the interlayer insulating film for insulating the gate line and the drain line extends to a position where it overlaps the spacer at the periphery of the first substrate. The end of the lower layer of the gate line or drain line is brought out from under the interlayer insulating film at the spacer position, and the end of the upper layer of the drain line or gate line is brought out between the layers. It extends under the interlayer insulating film through the contact hole of the insulating film, and is drawn out from under the interlayer insulating film at the spacer position.

(ホ) 作用 本発明の液晶表示装置によれば、第1の基板のゲートラ
インとドレインラインとの層間絶縁膜をこれ等両ライン
の保護膜としてスペーサ位置に介在せしめる事ができ、
このスペーサ位置でのこれ等両ラインの断線や短絡事故
を防止し得る。
(e) Function: According to the liquid crystal display device of the present invention, the interlayer insulating film between the gate line and drain line of the first substrate can be interposed at the spacer position as a protective film for both lines.
Disconnection or short-circuit accidents of both lines at this spacer position can be prevented.

(へ)実施例 第1図及び第2図に本発明の液晶表示装置の夫々異なる
要部断面図を示す、第1viAはドレインライン(15
)に沿った断面図、第2図はゲートライン(18)に沿
った断面図であり、第3図及び第4図と同一部分には同
一符号を付している。
(f) Embodiment FIGS. 1 and 2 show cross-sectional views of different main parts of the liquid crystal display device of the present invention.
), and FIG. 2 is a cross-sectional view along the gate line (18), and the same parts as in FIGS. 3 and 4 are given the same reference numerals.

これ等の図に於いて、第4図の従来例と異なる所は、ド
レインライン〈15〉とゲートライン(18)との居間
絶縁膜として働くと共に第3図に示す如く、スイッチン
グトランジスタのゲート絶縁膜として作用する絶縁膜(
12)をスペーサ(40)位置にまで延在している。そ
してゲートライン(18)は第2図に示す如く、第1の
基板(10)の絶縁膜(12)下に存在し、スペーサ(
40)位置の絶縁膜(12〉端辺から端子部(10’)
上に引き出され、スイッチングトランジスタをON、O
FF制御するタイミング信号供給用のゲート端子(GP
)を形成している。一方、ドレインライン(15)は第
3図に示されているような装置中央部の表示部では第1
の基板(10)の絶縁膜〈12)上にさらにアモルファ
スシリコン膜ライン(13)を介して形成されているが
、第1図に示す卯<、スペーサ(40)で囲まれた表示
部の端部箇所で絶縁膜〈12)のコンタクトホール(H
)を介して、予め絶縁膜(12)下に形成されている下
層ドしインライン(15’)に接続されている。そして
、このライン(15’)がスペーサ(40)位置の絶縁
膜(12)端辺から端子部(10’)上に引き出され、
表示2号供給用のドレイン端子(DP)を形成している
In these figures, the difference from the conventional example shown in Fig. 4 is that it acts as an insulating film between the drain line (15) and the gate line (18), and as shown in Fig. 3, the gate insulator of the switching transistor. An insulating film that acts as a film (
12) extends to the spacer (40) position. As shown in FIG. 2, the gate line (18) exists under the insulating film (12) of the first substrate (10), and the spacer (
40) Insulating film at position (12> From the edge to the terminal part (10')
It is pulled out and turns the switching transistor ON and OFF.
Gate terminal for supplying timing signal for FF control (GP
) is formed. On the other hand, the drain line (15) is connected to the first line in the display section in the center of the device as shown in Figure 3.
It is further formed on the insulating film (12) of the substrate (10) through an amorphous silicon film line (13), and as shown in FIG. Contact holes (H
) is connected to the lower layer in-line (15') formed in advance under the insulating film (12). Then, this line (15') is drawn out from the edge of the insulating film (12) at the spacer (40) position onto the terminal part (10'),
A drain terminal (DP) for supplying display No. 2 is formed.

尚、第1図の上記下層ドレインライン(15’)は、第
2図のゲートラインク18)と同一工程で金とクロムの
2層膜にて形成され得るので、新たな製造工程を必要と
しない。
Note that the lower drain line (15') in FIG. 1 can be formed of a two-layer film of gold and chromium in the same process as the gate line line 18) in FIG. 2, so a new manufacturing process is not required. do not.

上述の如き本発明の液晶表示装置は、ガラスからなる第
1及び第2のガラス基板(10)(20)の周辺部に設
けられるスペーサ(40)箇所では、下層ドレインライ
ン(15’)並びにゲートライン(18)上面は窒化シ
リコンからなる絶縁膜(12)にて保護される事となる
。従って、エポキシ系接着剤からなるスペーサにて両法
板(10)(20)を接着する際に、たとえ第2のガラ
ス基板(20)の周辺部の平坦度が歪んでいて、第1の
ガラス基板(10)側に接触したとしても、上記絶縁膜
(12)が両ライン(15’) (18)を保護してい
るので、これ等ライン(15’) (18)が損傷を受
けたり、第2のガラス基板(20)の共通電極(21)
と接触する事はない。
In the liquid crystal display device of the present invention as described above, the lower drain line (15') and the gate are located at the spacer (40) provided at the periphery of the first and second glass substrates (10) and (20) made of glass. The upper surface of the line (18) will be protected by an insulating film (12) made of silicon nitride. Therefore, when bonding the two substrates (10) and (20) with a spacer made of epoxy adhesive, even if the flatness of the peripheral part of the second glass substrate (20) is distorted, the first glass substrate Even if it comes into contact with the substrate (10) side, the insulating film (12) protects both lines (15') (18), so these lines (15') (18) will not be damaged or Common electrode (21) on second glass substrate (20)
There is no contact with.

尚、本発明は上述の実施例に限定されるものでなく、ゲ
ートライン(18)とドレインライン(15)との上下
関係が逆のものでもよい。
Note that the present invention is not limited to the above-described embodiment, and the vertical relationship between the gate line (18) and the drain line (15) may be reversed.

〈ト) 発明の効果 本発明の液晶表示装置によれば、ゲートラインとドレイ
ンラインとの層間絶縁膜をこれ等両ラインの保護膜とし
てスペーサ位置に介在せしめる事ができる。この為、第
1及び第2の基板をスペーサにて接着する際、第2の基
板がスペーサ位置の両ラインに直接接触するのを防止し
得る。従って大型の液晶表示装置に於いて第1及び第2
の基板の周辺部の平坦度の歪みが犬きくな−っていると
しても、スペーサ位置での両ラインの断線事故及び短絡
事故の惧れがない。
(G) Effects of the Invention According to the liquid crystal display device of the present invention, an interlayer insulating film between the gate line and the drain line can be interposed at the spacer position as a protective film for both lines. Therefore, when bonding the first and second substrates with the spacer, it is possible to prevent the second substrate from coming into direct contact with both lines of the spacer position. Therefore, in a large liquid crystal display device, the first and second
Even if the flatness of the peripheral portion of the substrate is severely distorted, there is no risk of disconnection or short-circuiting of both lines at the spacer position.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は夫々本発明の液晶表示装置の一実施
例の要部断面図、第3図(a)、及び(b)は一般的な
液晶表示装置の平面図、及びそのX−X線断面図、第4
図は従来の液晶表示装置の要部断面図である。 (10)・・・第1のガラス基板、(10’)・・・端
子部、(12)・・・絶縁膜、(13)・・・アモルフ
ァスシリコン膜うイン、(15)・・・ドレインライン
、(15’)・・・下層ドレインライン、(1g)・・
・ゲートライン、(20)・・・第2のfj5ス基板、
(30)・・・液晶物質、 (40)・・・スペーサ、
(DP)・・・ドレイン端子、(GP)・・・ゲート端
子。
1 and 2 are sectional views of essential parts of an embodiment of the liquid crystal display device of the present invention, and FIGS. 3(a) and 3(b) are plan views of a general liquid crystal display device, and its -X-ray cross-sectional view, 4th
The figure is a sectional view of a main part of a conventional liquid crystal display device. (10)...First glass substrate, (10')...Terminal portion, (12)...Insulating film, (13)...Amorphous silicon film lining, (15)...Drain Line, (15')...Lower drain line, (1g)...
・Gate line, (20)...second fj5 substrate,
(30)...Liquid crystal substance, (40)...Spacer,
(DP)...Drain terminal, (GP)...Gate terminal.

Claims (1)

【特許請求の範囲】 1)並列配置された複数本のゲートラインと該ゲートラ
インに層間絶縁膜を介して並列配置された複数本のドレ
インラインとが交差し、このマトリクス状の各交差点に
てFETからなるスイッチングトランジスタを構成し、
該各トランジスタのソース側に表示セグメント電極を結
合した第1の基板と、該第1の基板の各表示セグメント
電極に対向する共通電極を備えた第2の基板と、上記第
2の基板の周辺部に設けられ両基板間の間隔を規定する
スペーサーと、上記第1及び第2の基板間のスペーサ内
部箇所に封入された液晶物質と、からなる液晶表示装置
に於いて、 上記第1の基板の層間絶縁膜は第1の基板の周辺部のス
ペーサに重畳される位置まで延在され、上記ゲートライ
ンあるいはドレンラインの内の下層のラインの端部をス
ペーサ位置の層間絶縁膜下から外部へ引き出すと共に、
上記ドレンラインあるいはゲートラインの内の上層ライ
ンの端部を層間絶縁膜のコンタクトホールを介して層間
絶縁膜下に延長し、スペーサ位置の層間絶縁膜下から外
部へ引き出す事を特徴とした液晶表示装置。
[Claims] 1) A plurality of gate lines arranged in parallel intersect with a plurality of drain lines arranged in parallel with the gate lines via an interlayer insulating film, and at each intersection in this matrix, Configures a switching transistor consisting of an FET,
a first substrate having a display segment electrode coupled to the source side of each transistor; a second substrate having a common electrode facing each display segment electrode of the first substrate; and a periphery of the second substrate. In the liquid crystal display device, the liquid crystal display device comprises a spacer provided in the spacer to define a distance between the two substrates, and a liquid crystal substance sealed inside the spacer between the first and second substrates, The interlayer insulating film is extended to a position where it overlaps the spacer at the periphery of the first substrate, and the end of the lower layer of the gate line or drain line is extended from under the interlayer insulating film at the spacer position to the outside. As well as pulling out
A liquid crystal display characterized in that the end of the upper line of the drain line or gate line is extended below the interlayer insulating film through a contact hole in the interlayer insulating film, and drawn out from under the interlayer insulating film at the spacer position. Device.
JP60284788A 1985-12-17 1985-12-17 Liquid crystal display Expired - Lifetime JPH0612387B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60284788A JPH0612387B2 (en) 1985-12-17 1985-12-17 Liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60284788A JPH0612387B2 (en) 1985-12-17 1985-12-17 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPS62143028A true JPS62143028A (en) 1987-06-26
JPH0612387B2 JPH0612387B2 (en) 1994-02-16

Family

ID=17683027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60284788A Expired - Lifetime JPH0612387B2 (en) 1985-12-17 1985-12-17 Liquid crystal display

Country Status (1)

Country Link
JP (1) JPH0612387B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104025A (en) * 1986-10-21 1988-05-09 Matsushita Electric Ind Co Ltd Liquid crystal display device
JPH0242761A (en) * 1988-04-20 1990-02-13 Matsushita Electric Ind Co Ltd Manufacture of active matrix substrate
JPH02250037A (en) * 1989-03-23 1990-10-05 Matsushita Electric Ind Co Ltd Production of active matrix substrate and production of display device
JPH03116778A (en) * 1989-09-28 1991-05-17 Matsushita Electric Ind Co Ltd Manufacture of active matrix substrate and manufacture of display device
JPH03209777A (en) * 1990-01-11 1991-09-12 Matsushita Electric Ind Co Ltd Active matrix array and its manufacture and manufacture of display device
JPH03241320A (en) * 1990-02-20 1991-10-28 Fujitsu Ltd Liquid crystal display element
JPH06118432A (en) * 1992-10-09 1994-04-28 Seiko Epson Corp Liquid crystal display device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104025A (en) * 1986-10-21 1988-05-09 Matsushita Electric Ind Co Ltd Liquid crystal display device
JPH0242761A (en) * 1988-04-20 1990-02-13 Matsushita Electric Ind Co Ltd Manufacture of active matrix substrate
JPH02250037A (en) * 1989-03-23 1990-10-05 Matsushita Electric Ind Co Ltd Production of active matrix substrate and production of display device
JPH03116778A (en) * 1989-09-28 1991-05-17 Matsushita Electric Ind Co Ltd Manufacture of active matrix substrate and manufacture of display device
JPH03209777A (en) * 1990-01-11 1991-09-12 Matsushita Electric Ind Co Ltd Active matrix array and its manufacture and manufacture of display device
JPH03241320A (en) * 1990-02-20 1991-10-28 Fujitsu Ltd Liquid crystal display element
JPH06118432A (en) * 1992-10-09 1994-04-28 Seiko Epson Corp Liquid crystal display device

Also Published As

Publication number Publication date
JPH0612387B2 (en) 1994-02-16

Similar Documents

Publication Publication Date Title
JP4386862B2 (en) Liquid crystal display device and manufacturing method thereof
US6972750B2 (en) Liquid crystal panel device having a touch panel and method of fabricating the same
US10186526B2 (en) Display panel
JP2010066542A (en) Liquid crystal display device
KR20120094790A (en) Liquid crystal display
JPH06186580A (en) Liquid crystal display device
JPH06258661A (en) Liquid crystal display device
JP3806497B2 (en) Display device
JP2007024963A (en) Liquid crystal display device
JP3253383B2 (en) Liquid crystal display
JP2005301308A (en) Display apparatus and liquid crystal display device
JPS62143028A (en) Liquid crystal displaying device
JP3208909B2 (en) Liquid crystal display
JPH06289414A (en) Liquid crystal display device
US12066729B2 (en) Display panel and display device
JPH10268356A (en) Liquid crystal display device
JP2004004526A (en) Liquid crystal display
KR940022128A (en) LCD and its manufacturing method
KR101023284B1 (en) Liquid Crystal Display device and the fabrication method thereof
JPH11282386A (en) Manufacture of active matrix substrate device, active matrix substrate device, and electro-optical panel provided with it
JP4468626B2 (en) Display device substrate and display device including the same
JP2007024964A (en) Liquid crystal display
JPH10253991A (en) Liquid crystal display device
JP7446076B2 (en) semiconductor equipment
JP2007114662A (en) Liquid crystal display device

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term