JPH03209777A - Active matrix array and its manufacture and manufacture of display device - Google Patents

Abstract

PURPOSE:To obtain an active matrix array which is small in backgate effect and has an excellent TFT characteristic by specifying the relation between the dielectric constants and film thicknesses of a gate insulating and semiconductor protective layers. CONSTITUTION:The first conductive layer 2 which works as a gate electrode and scanning signal line are selectively formed on a glass substrate 1 by coating. Then the first insulating layer 3, amorphous silicon semiconductor layer which becomes a donor or acceptor, and semiconductor protective layer 5 are successively formed on the entire surface of the substrate 1 by coating. When the layer 3 is formed of silicon nitride and the layer 5 of a low-dielectric constant material, such as silicon oxide or silicon oxynitride, the semiconductor protective layer 5 can be reduced in thickness. Selection of these materials is made so that a relational expression, epsilon1/d1>=epsilon2/d2 can be met between the dielectric constant and film thickness of the insulating layer 3 and those of the protective layer 5. The epsilon1 and epsilon2 and d1 and d2 of the expression respectively represent the dielectric constants and film thicknesses of the layers 3 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix array used in liquid crystal televisions for video display, displays for computer terminals, etc., and a method for manufacturing the same and a method for manufacturing a display device.

Conventional technology In recent years, expectations for flat image display devices have been increasing.
In particular, research and development of flat displays using liquid crystals is extremely active. Among these, active matrix type liquid crystal display elements, which combine active matrix arrays in which active elements are arranged in a two-dimensional matrix, and liquid crystals, are being commercialized and are viewed as promising. Figure 4 shows its equivalent circuit, and 16 is a thin film transistor (T
17 is a liquid crystal cell, 18 is a scanning signal line,
19 is a video signal line. TFT 16 on scanning signal line 18
Apply gate signals sequentially so that the video signal v
A function equivalent to that of a CRT is provided by line sequential scanning in which a video signal corresponding to one gate line is written into the liquid crystal cell 17 from A19.

The TFT 16 often uses amorphous silicon as a semiconductor layer, which has a relatively low temperature and can be deposited over a large area. Here, a method for manufacturing a liquid crystal display using amorphous silicon as a TPT semiconductor layer will be described. FIG. 5 shows a schematic plan view of one pixel of an active matrix array for a liquid crystal display, and FIG. 6 shows a sectional view taken along line A' in the plan view shown in FIG.

First, a first conductive layer 2, which serves as a gate electrode and a scanning signal line, is selectively deposited on a glass substrate 1 using, for example, Cr. After that, as the first insulating layer 3, for example, a silicon nitride layer, an amorphous silicon semiconductor layer (hereinafter abbreviated as 1-a-3t) 4 containing almost no impurity that becomes a donor or acceptor, and a semiconductor protective layer 5 are formed. For example, a silicon nitride layer is selectively deposited by plasma CVD. Next, in order to improve the ohmic properties of the junction between the source/drain and the semiconductor layer, an amorphous silicon semiconductor layer 6 (hereinafter abbreviated as n"-a-3i) containing a large amount of phosphorus as an impurity serving as a donor is formed by plasma CVD. These semiconductor layers are deposited by a method and then turned into island shapes by ordinary photolithography and etching.Then, a second conductive layer 7 which serves as a video signal line and a source of the TPT, and a second conductive layer which serves as a drain of the TPT are formed. A conductive layer 8 is selectively deposited using, for example, At.
Etching is performed using i as the source/drain and the semiconductor protective layer as a mask. Finally, the first transparent conductive layer 9 that becomes the pixel bridge is made of ITO (Indium-Tin-O
xide) is selectively deposited so as to be connected to the drain to obtain an active matrix array.

After coating and curing polyimide resin on both the above-mentioned active matrix array and the counter glass substrate 10 on which the second transparent electrode layer 11 is coated, an alignment treatment is performed, and the liquid crystal 13 is formed by, for example, twisting. Nematic liquid crystal may be sealed between both substrates, and polarizing plates 15 may be placed above and below.

Problems to be Solved by the Invention However, in the above structure, an overlamp portion with the source (or drain) occurs on a portion of the semiconductor protective layer. Looking at the cross section of this part, the original source (or drain) can be regarded as the gate, and the semiconductor protective layer can be regarded as the gate insulating layer (that is, it can be regarded as a transistor with the original source as the back gate). Therefore,
Depending on the source potential, the 1-a-3i layer enters an accumulation state or a depletion state from the back gate side. As a result, there was a problem in that the TPT characteristics were affected by the source potential and the TPT characteristics deteriorated.

In view of the above, an object of the present invention is to provide an active matrix array and a method for manufacturing a display device that have good TPT characteristics with little back gate effect.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention sets the dielectric constant and film thickness of the gate insulating layer to ε1 and d1, respectively, and sets the dielectric constant and film thickness of the semiconductor protective layer to ε2. When d8, it is formed so as to satisfy the relational expression % expression %.

Operation When the present invention is manufactured with the above-described configuration, the back gate effect can be reduced, and an active matrix array with good TPT characteristics, a manufacturing method thereof, and a display device can be manufactured.

Embodiment FIG. 1 shows a sectional view of a semiconductor element in an embodiment of the present invention, and explanation will be given using this drawing.

First, a first conductive layer 2, which serves as a gate electrode and a scanning signal line, is selectively deposited on a glass substrate 1 using, for example, Cr. After that, for example, a silicon nitride layer is deposited as the first insulating layer 3 on the entire surface by plasma CVD method, for example, by 4000 layers, and an amorphous silicon semiconductor layer containing almost no impurities as donors or acceptors is deposited by 500 layers, and then the semiconductor is continuously protected. As layer 5, silicon nitride is deposited over the entire surface to a thickness of 5000 nm. Then, a desired resist pattern was formed by an ordinary photolithography method, and unnecessary portions were etched away by a reactive dry etching method, which is a type of dry etching, using CCl4 as an etching gas to form a semiconductor protective layer. Here, CC1 was used as the etching gas because CC1 was a
This is because the etching selectivity with respect to -3t is high, and since the etching is anisotropic, there is no taper and a nearly vertical side wall surface can be obtained. If isotropic etching such as wet etching is used, a large taper will be produced, and the film thickness at the tapered portion will be thinner than the deposited film thickness, increasing the back gate effect, so it is desirable to avoid this. Therefore,
Any material may be used as long as it can be anisotropically etched.

Then, the amorphous silicon semiconductor layer 4 is formed into islands by ordinary photolithography and etching. Next, a second conductive layer 7 that serves as the source of the video signal line and the MIS transistor, and a second metal layer 8 that serves as the drain of the MIS transistor are selectively deposited with, for example, AI to protect the source/drain and the semiconductor. layer as a mask, n”
- selectively remove a-3i. Finally, the active matrix array is completed by selectively depositing picture element electrodes using, for example, ITO as a transparent conductive layer.

Now, the transistor characteristics of the TPT created based on this example and the gate voltage dependence of the drain current of the conventional TPT are shown in FIG.
threshold) TP according to this embodiment in the fil area.
It can be seen that the characteristics of TPT are superior to those of conventional TPT.

In the above example, both the gate insulating layer and the semiconductor protective layer were formed of silicon nitride, but the gate insulating layer was made of a material with a high dielectric constant about four times that of silicon nitride, such as tantalum oxide, and the semiconductor protective layer was made of silicon nitride. If silicon nitride is used, the silicon nitride layer can be formed to have a thickness approximately 174 times that of the gate insulating layer, so the tapered shape of the semiconductor protective layer can be easily controlled. Furthermore, even if the gate insulating layer is formed of silicon nitride and the semiconductor protective layer is formed of a low dielectric constant material such as silicon oxide or silicon oxynitride, the thickness of the semiconductor protective layer can be similarly reduced, so the shape can be reduced. Easy to control. The selection of these materials is such that the dielectric constant and thickness of the gate insulating layer are ε1°d+, and the dielectric constant and thickness of the semiconductor protective layer are ε! Any material may be used as long as it satisfies the relational expression % when +L.

In addition, although Cr was used as the material of the gate electrode 2, Ta,
Any material used for the gate electrode of TPT, such as Ti, Mo, Ni, Ni-Cr alloy, or silicides of these metals, can be used.

Further, as the material for the gate insulator layer 3, silicon nitride, silicon oxide, metal oxide, etc. are also used.

Furthermore, although amorphous silicon is used as the material for the first and second semiconductor layers, polycrystalline silicon or recrystallized silicon may also be used without any problem.

Furthermore, as the material of the picture element electrode, In, 03SnO,
Alternatively, transparent conductive materials such as mixtures thereof can be used.

Further, when forming the source electrode, the drain electrode, and the picture element electrode at the same time, a transparent conductive material such as InzO3°Snug or a mixture thereof can be used as the material for the source electrode and the drain electrode. When forming the source electrode, the drain electrode, and the picture element electrode separately, the material for the source electrode and the drain electrode may be At or Mo.

Ta, Ti, Cr, and silicides of these metals can be used. Note that in this case, the source and drain electrodes can be formed not only in a single layer but also in multiple layers to add redundancy.

Further, in the above embodiment, a storage capacitor was not provided, but in order to improve image quality, one of the electrodes serving as a storage capacitor was provided at the same level as the first metal layer, and the first transparent insulating layer was interposed. A storage capacitor can also be added by using the picture element electrode as the other storage capacitor electrode.

Example 2 FIG. 3 shows a cross-sectional view of a third embodiment of the invention.

First, an active matrix array is created in the same manner as in Example 1 or Example 2.

The active matrix array described above and the opposing transparent electrode l
A liquid crystal alignment film 12 made of polyimide, silicon oxide, etc. is formed on the opposite glass substrate lO on which the sealing material 1 is applied.
2 and a glass fiber (not shown), and liquid crystal 14 is injected between them. Next, the opposing glass substrate 1
0 as a mask, unnecessary gate insulator layer 3 on gate bridge 2 is removed, and finally polarizing plates 15 are placed in front and behind both substrates to complete the liquid crystal display device.

As described in detail, according to the present invention, since the back gate effect can be reduced, active matrix arrays and display devices with good TST characteristics can be manufactured, and the practical effects thereof are significant.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an embodiment of an active matrix array according to the present invention, FIG. 2 is a comparison diagram of transistor characteristics according to an embodiment of the present invention and conventional transistor characteristics, and FIG. 3 is a liquid crystal display manufactured according to the present invention. 4 is an equivalent circuit diagram of a liquid crystal display device, FIG. 5 is a schematic plan view of one pixel of an active matrix array, and FIG. 6 is a schematic sectional view of one pixel of the same array. . ■... Glass substrate, 2... Gate electrode (first conductive layer), 3... Gate insulating layer (first insulating layer), 4... ... Semiconductor layer containing amorphous silicon as a main component (first semiconductor layer), 5 ... Semiconductor protective layer (second insulating layer), 6 ... Donor or acceptor and an amorphous silicon semiconductor layer containing impurities (second semiconductor layer), 7... source electrode (second conductive layer), 8... drain electrode (second conductive layer); ), 9... pixel electrode, 10... counter glass substrate, 11... counter transparent electrode, 12...
...Alignment film, 13...Liquid crystal, 14...
...Sealing material, 15...Polarizing plate, 16...
...Thin film transistor (TFT), 17...
Liquid crystal cell, 18...Scanning signal line, 19...
...Video signal line.

Claims (5)

[Claims] (1) A first conductive layer selectively formed on a transparent substrate, a first insulating layer formed to cover the first conductive layer, and a first insulating layer formed to cover the first conductive layer; a semiconductor layer selectively deposited on the first conductive layer via an insulating layer; a second insulating layer formed on a portion of the semiconductor layer; In an active matrix array comprising at least a semiconductor layer and a pair of second conductive layers selectively formed to partially overlap the first conductive layer with the first insulating layer interposed therebetween, the first insulating layer When the dielectric constant and thickness of the layer are ε_1 and d_1, respectively, and the dielectric constant and thickness of the second insulating layer are ε_2 and d_2, respectively,
An active matrix array characterized by satisfying the relational expression ε_1/d_1≧ε_2/d_2. (2) selectively forming a first conductive layer on a transparent substrate; forming a first insulating layer to cover the first conductive layer; a step of selectively depositing a semiconductor layer on the first conductive layer via an insulating layer; a step of selectively forming a second insulating layer on a portion of the semiconductor layer; a step of selectively forming a pair of second conductive layers that are selectively formed to partially overlap the first conductive layer through the insulating layer, the semiconductor layer, and the first insulating layer; In the method for manufacturing an active matrix array, the second insulating layer has a dielectric constant and a film thickness of the first insulating layer of ε_1 and d_, respectively.
1, and the dielectric constant and film thickness of the second insulating layer are respectively ε
When _2 and d_2, the resist is deposited on the entire surface of the substrate under conditions that satisfy the relational expression ε_1/d_1≧ε_2/d_2, then a desired resist pattern is formed, and the resist pattern is dry-etched using the resist pattern as a mask. A method for manufacturing an active matrix array. (3) The method for manufacturing an active matrix array according to claim (2), characterized in that a second semiconductor layer containing an impurity serving as a donor or acceptor is interposed between the semiconductor layer and the second conductive layer. (4) The active matrix according to claim (3), wherein the first insulating layer and the second insulating layer are made of at least silicon nitride, and the semiconductor layer is made of a non-single crystal semiconductor mainly composed of silicon. Array manufacturing method. (5) A step of sandwiching a material having optical anisotropy between the active matrix array substrate manufactured by the manufacturing method according to claim (2) and a counter substrate having a transparent electrode, and at least one of the two substrates. A method for manufacturing a display device including a step of arranging a polarizing plate, the method comprising a step of etching an exposed portion of an insulator layer of the active matrix array substrate using the counter substrate as a mask. .