JPH03209777A - Active matrix array and its manufacture and manufacture of display device - Google Patents
Active matrix array and its manufacture and manufacture of display deviceInfo
- Publication number
- JPH03209777A JPH03209777A JP2004159A JP415990A JPH03209777A JP H03209777 A JPH03209777 A JP H03209777A JP 2004159 A JP2004159 A JP 2004159A JP 415990 A JP415990 A JP 415990A JP H03209777 A JPH03209777 A JP H03209777A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- active matrix
- semiconductor
- matrix array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000003287 optical effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 58
- 239000011241 protective layer Substances 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 16
- 239000010408 film Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000000370 acceptor Substances 0.000 description 3
- 210000002858 crystal cell Anatomy 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- -1 tantalum oxide Chemical compound 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、映像表示用液晶テレビやコンピュータ端末用
デイスプレィ等に用いられるアクティブマトリクスアレ
ー及びその製造方法と表示装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix array used in liquid crystal televisions for video display, displays for computer terminals, etc., and a method for manufacturing the same and a method for manufacturing a display device.
従来の技術
近年、画像表示装置の平面化への期待が高まっており、
特に液晶を用いたフラットデイスプレィの研究開発は非
常に活発に行われている。その中でも能動素子を二次元
のマトリクス状に配置したアクティブマトリクスアレー
と液晶を組み合わせたアクティブマトリクス型液晶表示
素子は商品化も進められ有望視されている。第4図はそ
の等価回路を示しており、16は薄膜トランジスタ(T
hinFilm Transistor:T F Tと
以下略記する)、17は液晶セル、18は走査信号線、
19は映像信号線である。走査信号線18にTFT16
がONするように順次ゲート信号を印加し、映像信号v
A19よりゲート1ラインに対応した映像信号を液晶セ
ル17に書き込ませる線順次走査によってCRTと同等
の機能が賦与される。Conventional technology In recent years, expectations for flat image display devices have been increasing.
In particular, research and development of flat displays using liquid crystals is extremely active. Among these, active matrix type liquid crystal display elements, which combine active matrix arrays in which active elements are arranged in a two-dimensional matrix, and liquid crystals, are being commercialized and are viewed as promising. Figure 4 shows its equivalent circuit, and 16 is a thin film transistor (T
17 is a liquid crystal cell, 18 is a scanning signal line,
19 is a video signal line. TFT 16 on scanning signal line 18
Apply gate signals sequentially so that the video signal v
A function equivalent to that of a CRT is provided by line sequential scanning in which a video signal corresponding to one gate line is written into the liquid crystal cell 17 from A19.
TFT16は比較的低温で、大面積に堆積が可能な非晶
質シリコンを半導体層として用いる場合が多い。ここで
は非晶質シリコンをTPTの半導体層として用いた液晶
デイスプレィの製造方法について説明する。第5図は液
晶デイスプレィ用のアクティブマトリクスアレーの1画
素の概略平面図を示し、第6図は第5図に示された平面
図のAへ′線上の断面図を示している。The TFT 16 often uses amorphous silicon as a semiconductor layer, which has a relatively low temperature and can be deposited over a large area. Here, a method for manufacturing a liquid crystal display using amorphous silicon as a TPT semiconductor layer will be described. FIG. 5 shows a schematic plan view of one pixel of an active matrix array for a liquid crystal display, and FIG. 6 shows a sectional view taken along line A' in the plan view shown in FIG.
まず、ガラス基板1上にゲート電極と走査信号線を兼ね
る第一の導電層2を例えばCrで選択的に被着形成する
。その後、第一の絶縁層3として例えば窒化シリコン層
と、ドナーまたはアクセプターとなる不純物をほとんど
含まない非晶質シリコン半導体層(以下1−a−3tと
略記する)4と、半導体保護層5を例えば窒化シリコン
層をプラズマCVD法により選択的に被着形成する。次
に、ソース・ドレインと半導体層との接合のオーミック
性を改善するためドナーとなる不純物としてリンを多く
含む非晶質シリコン半導体層6(以下n”−a−3iと
略記する)をプラズマCVD法により堆積し、通常のフ
ォトリソグラフィー及びエツチングによりこれらの半導
体層を島状にノ々ターニングする。そして映像信号線と
TPTのソースを兼ねる第二の導電層7及びTPTのド
レインとなる第二の導電層8を例えばAtにより選択的
に被着形成する。そして、チャンネル部のn゛−a−3
iをソース・ドレイン、及び半導体保護層をマスクとし
てエツチング除去する。最後に画素電橋となる第一の透
明導電層9として、ITO(Indium−Tin−O
xide)をドレインと接続するように選択的に被着形
成してアクティブマトリクスアレーを得る。First, a first conductive layer 2, which serves as a gate electrode and a scanning signal line, is selectively deposited on a glass substrate 1 using, for example, Cr. After that, as the first insulating layer 3, for example, a silicon nitride layer, an amorphous silicon semiconductor layer (hereinafter abbreviated as 1-a-3t) 4 containing almost no impurity that becomes a donor or acceptor, and a semiconductor protective layer 5 are formed. For example, a silicon nitride layer is selectively deposited by plasma CVD. Next, in order to improve the ohmic properties of the junction between the source/drain and the semiconductor layer, an amorphous silicon semiconductor layer 6 (hereinafter abbreviated as n"-a-3i) containing a large amount of phosphorus as an impurity serving as a donor is formed by plasma CVD. These semiconductor layers are deposited by a method and then turned into island shapes by ordinary photolithography and etching.Then, a second conductive layer 7 which serves as a video signal line and a source of the TPT, and a second conductive layer which serves as a drain of the TPT are formed. A conductive layer 8 is selectively deposited using, for example, At.
Etching is performed using i as the source/drain and the semiconductor protective layer as a mask. Finally, the first transparent conductive layer 9 that becomes the pixel bridge is made of ITO (Indium-Tin-O
xide) is selectively deposited so as to be connected to the drain to obtain an active matrix array.
上述のアクティブマトリクスアレーと一生面上に第二の
透明電極層11を被着した対向ガラス基板10の両方に
ポリイミド樹脂を塗布し硬化させた後、′配向処理を行
い、液晶13として例えばツイスト・ネマチック液晶を
両基板間に封入し、さらに上下に偏光板15を配置すれ
ばよい。After coating and curing polyimide resin on both the above-mentioned active matrix array and the counter glass substrate 10 on which the second transparent electrode layer 11 is coated, an alignment treatment is performed, and the liquid crystal 13 is formed by, for example, twisting. Nematic liquid crystal may be sealed between both substrates, and polarizing plates 15 may be placed above and below.
発明が解決しようとする課題
しかしながら上記のような構成では、半導体保護層上の
一部にソース(あるいはドレイン)とのオーバーランプ
部分が発生する。この部分の断面を見ると、本来のソー
ス(あるいはドレイン)をゲート、半導体保護層をゲー
ト絶縁層とみなす(即ち、本来のソースをバックゲート
としたトランジスタとみなす)こともできる。従って、
ソース電位によっては1−a−3i層がバックゲート側
からアキュムレーション状態になったり、あるいはデプ
レッション状態になる。この結果、TPT特性がソース
電位によって影響を受け、TPT特性が劣化するという
課題を有していた。Problems to be Solved by the Invention However, in the above structure, an overlamp portion with the source (or drain) occurs on a portion of the semiconductor protective layer. Looking at the cross section of this part, the original source (or drain) can be regarded as the gate, and the semiconductor protective layer can be regarded as the gate insulating layer (that is, it can be regarded as a transistor with the original source as the back gate). Therefore,
Depending on the source potential, the 1-a-3i layer enters an accumulation state or a depletion state from the back gate side. As a result, there was a problem in that the TPT characteristics were affected by the source potential and the TPT characteristics deteriorated.
本発明はかかる点に鑑み、バックゲート効果の少ない良
好なTPT特性を持つアクティブマトリクスアレー並び
に表示装置の製造方法を提供することを目的とする。In view of the above, an object of the present invention is to provide an active matrix array and a method for manufacturing a display device that have good TPT characteristics with little back gate effect.
課題を解決するための手段
本発明は前述の課題を解決するため、ゲート絶縁層の誘
電率と膜厚をそれぞれε1、d1とし、半導体保護層の
誘電率と膜厚をそれぞれε2.d8としたとき、関係式
%式%
を満たすように形成する。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention sets the dielectric constant and film thickness of the gate insulating layer to ε1 and d1, respectively, and sets the dielectric constant and film thickness of the semiconductor protective layer to ε2. When d8, it is formed so as to satisfy the relational expression % expression %.
作用
本発明は前記した構成により製造すると、バックゲート
効果を減少させることができ、TPT特性の良好なアク
ティブマトリクスアレー及びその製造方法並びに表示装
置を製造することができる。Operation When the present invention is manufactured with the above-described configuration, the back gate effect can be reduced, and an active matrix array with good TPT characteristics, a manufacturing method thereof, and a display device can be manufactured.
実施例
第1図は本発明の一実施例における半導体素子の断面図
を示し、この図面を用いて説明する。Embodiment FIG. 1 shows a sectional view of a semiconductor element in an embodiment of the present invention, and explanation will be given using this drawing.
まず、ガラス基板1上にゲート電極と走査信号線を兼ね
る第一の導電層2を例えばCrで選択的に被着形成する
。その後例えばプラズマCVD法により全面に第一の絶
縁層3として例えば窒化シリコン層を4000人、ドナ
ーまたはアクセプタとなる不純物をほとんど含まない非
晶質シリコン半導体層を500人、引き続いて連続的に
半導体保護層5として窒化シリコンを5000人の膜厚
で全面に被着形成する。そして、通常のフォトリソグラ
フィー法で所望のレジストパターンを形成し、ドライエ
ツチングの一種であるリアクティブドライエツチング法
でCCl4をエツチングガスとして用いて不要な部分を
エツチング除去して半導体保護層を形成した。ここでエ
ツチングガスにCC1,を使用したのは、CC1,はa
−3tとの選択比が高く、しかも異方性エツチングとな
るのでテーバがつかず、はぼ垂直な側壁面が得られるか
らである。もし、ウェットエツチングのような等方性エ
ツチングを用いると大きなテーバがついてしまいテーバ
部は膜厚が堆積膜厚より薄くなりバックゲート効果が大
きくなってしまうため避けることが望ましい。従って、
異方性エツチングが可能ならば何でもよい。First, a first conductive layer 2, which serves as a gate electrode and a scanning signal line, is selectively deposited on a glass substrate 1 using, for example, Cr. After that, for example, a silicon nitride layer is deposited as the first insulating layer 3 on the entire surface by plasma CVD method, for example, by 4000 layers, and an amorphous silicon semiconductor layer containing almost no impurities as donors or acceptors is deposited by 500 layers, and then the semiconductor is continuously protected. As layer 5, silicon nitride is deposited over the entire surface to a thickness of 5000 nm. Then, a desired resist pattern was formed by an ordinary photolithography method, and unnecessary portions were etched away by a reactive dry etching method, which is a type of dry etching, using CCl4 as an etching gas to form a semiconductor protective layer. Here, CC1 was used as the etching gas because CC1 was a
This is because the etching selectivity with respect to -3t is high, and since the etching is anisotropic, there is no taper and a nearly vertical side wall surface can be obtained. If isotropic etching such as wet etching is used, a large taper will be produced, and the film thickness at the tapered portion will be thinner than the deposited film thickness, increasing the back gate effect, so it is desirable to avoid this. Therefore,
Any material may be used as long as it can be anisotropically etched.
そして、非晶質シリコン半導体層4を通常のフォトリソ
グラフィー法とエンチングにより島化する。次に映像信
号線とMISトランジスタのソースを兼ねる第二の導電
層7及びMISトランジスタのドレインとなる第二の金
属層8として例えばAIを選択的に被着形成し、このソ
ース・ドレイン及び半導体保護層をマスクとして、n”
−a−3iを選択的に除去する。最後に透明導電層とじ
て例えばITOで絵素電極を選択的に被着形成すればア
クティブマトリクスアレーが完成される。Then, the amorphous silicon semiconductor layer 4 is formed into islands by ordinary photolithography and etching. Next, a second conductive layer 7 that serves as the source of the video signal line and the MIS transistor, and a second metal layer 8 that serves as the drain of the MIS transistor are selectively deposited with, for example, AI to protect the source/drain and the semiconductor. layer as a mask, n”
- selectively remove a-3i. Finally, the active matrix array is completed by selectively depositing picture element electrodes using, for example, ITO as a transparent conductive layer.
さて本実施例に基づいて作成したTPTのトランジスタ
特性及び従来のTPTのドレイン電流のゲート電圧依存
性を第2図に示す特にサブ−スレッショルド(Sub−
threshold) fil域で本実施例によるTP
Tの特性が従来のTPTよりも優れていることが判る。Now, the transistor characteristics of the TPT created based on this example and the gate voltage dependence of the drain current of the conventional TPT are shown in FIG.
threshold) TP according to this embodiment in the fil area.
It can be seen that the characteristics of TPT are superior to those of conventional TPT.
なお、上記実施例では、ゲート絶縁層及び半導体保護層
を共に窒化シリコンで形成したが、ゲート絶縁層を酸化
タンタルのような窒化シリコンの約4倍の高誘電率材料
を用い、半導体保護層を窒化シリコンで形成すれば、窒
化シリコン層はゲート絶縁層の約174倍程度の厚みで
形成することができるので、半導体保護層のテーバ形状
を容易に制御できる。また、ゲート絶縁層は窒化シリコ
ンで形成し、半導体保護層を酸化シリコンやシリコンオ
キシナイトライドのような低誘電率材料で形成しても同
様に半導体保護層の膜厚を薄くできるので、形状を制御
しやすい。これらの材料の選択は、ゲート絶縁層の誘電
率と膜厚をそれぞれε1゜d+ とし、半導体保護層の
誘電率と膜厚をそれぞれε!+Lとしたとき、関係式
%式%
を満たすように形成すればどんな材料でもよい。In the above example, both the gate insulating layer and the semiconductor protective layer were formed of silicon nitride, but the gate insulating layer was made of a material with a high dielectric constant about four times that of silicon nitride, such as tantalum oxide, and the semiconductor protective layer was made of silicon nitride. If silicon nitride is used, the silicon nitride layer can be formed to have a thickness approximately 174 times that of the gate insulating layer, so the tapered shape of the semiconductor protective layer can be easily controlled. Furthermore, even if the gate insulating layer is formed of silicon nitride and the semiconductor protective layer is formed of a low dielectric constant material such as silicon oxide or silicon oxynitride, the thickness of the semiconductor protective layer can be similarly reduced, so the shape can be reduced. Easy to control. The selection of these materials is such that the dielectric constant and thickness of the gate insulating layer are ε1°d+, and the dielectric constant and thickness of the semiconductor protective layer are ε! Any material may be used as long as it satisfies the relational expression % when +L.
また、ゲート電極2の材料としてCrとしたが、Ta、
Ti、Mo、Ni、Ni−Cr合金やこれらの金属の珪
化物等、TPTのゲート電極の材料として使用されるも
のならばいずれも使用し得る。In addition, although Cr was used as the material of the gate electrode 2, Ta,
Any material used for the gate electrode of TPT, such as Ti, Mo, Ni, Ni-Cr alloy, or silicides of these metals, can be used.
また、ゲート絶縁体層3の材料としては、窒化シリコン
、酸化シリコンや金属酸化物なども用いられる。Further, as the material for the gate insulator layer 3, silicon nitride, silicon oxide, metal oxide, etc. are also used.
また、第一、第二の半導体層の材料として、非晶質シリ
コンを使用したが、多結晶シリコンや再結晶化したシリ
コンを用いても問題ない。Furthermore, although amorphous silicon is used as the material for the first and second semiconductor layers, polycrystalline silicon or recrystallized silicon may also be used without any problem.
さらに、絵素電極の材料としては、In、03SnO,
或いはこれらの混合物等の透明導電材料が使用できる。Furthermore, as the material of the picture element electrode, In, 03SnO,
Alternatively, transparent conductive materials such as mixtures thereof can be used.
また、ソース電極及びドレイン電極と絵素電極とを同時
に形成する場合にはソース電極及びドレイン電極の材料
として、InzO3゜Snug或いはこれらの混合物等
の透明導電材料が使用できる。ソース電極及びドレイン
電極と絵素電極とを別々に形成する場合には、ソース電
極及びドレイン電極の材料としては、At、Mo。Further, when forming the source electrode, the drain electrode, and the picture element electrode at the same time, a transparent conductive material such as InzO3°Snug or a mixture thereof can be used as the material for the source electrode and the drain electrode. When forming the source electrode, the drain electrode, and the picture element electrode separately, the material for the source electrode and the drain electrode may be At or Mo.
Ta、Ti、Crやこれらの金属の珪化物などが使用で
きる。なお、この場合ソース及びドレイン電極は、単層
のみならず複数層で形成して冗長性を付加することがで
きる。Ta, Ti, Cr, and silicides of these metals can be used. Note that in this case, the source and drain electrodes can be formed not only in a single layer but also in multiple layers to add redundancy.
また、上記実施例では蓄積容量を設けなかったが、画質
を向上させるために蓄積容量となる電極の一方を、例え
ば、第一の金属層と同レベルに設け、第一の透明絶縁層
を介して絵素電極をもう一方の蓄積容量電極とすること
により蓄積容量を付加することもできる。Further, in the above embodiment, a storage capacitor was not provided, but in order to improve image quality, one of the electrodes serving as a storage capacitor was provided at the same level as the first metal layer, and the first transparent insulating layer was interposed. A storage capacitor can also be added by using the picture element electrode as the other storage capacitor electrode.
実施例2 第3図に、本発明の第3の実施例の断面図を示す。Example 2 FIG. 3 shows a cross-sectional view of a third embodiment of the invention.
まず、実施例1或いは実施例2と同様にして、アクティ
ブマトリクスアレーを作成する。First, an active matrix array is created in the same manner as in Example 1 or Example 2.
上述のアクティブマトリクスアレーと、対向透明電極l
lを被着した対向ガラス基板lO上にポリイミドや酸化
珪素等よりなる液晶の配向膜12を形成し、シール材1
2及びグラスファイバ等(図示せず)を介して貼り合わ
せ、液晶14を間に注入する。次に、対向ガラス基板1
0をマスクとして、ゲート電橋2上の不要なゲート絶縁
体層3を除去して、最後に偏光板15を両基板の前後に
配置して液晶表示装置が完成する。The active matrix array described above and the opposing transparent electrode l
A liquid crystal alignment film 12 made of polyimide, silicon oxide, etc. is formed on the opposite glass substrate lO on which the sealing material 1 is applied.
2 and a glass fiber (not shown), and liquid crystal 14 is injected between them. Next, the opposing glass substrate 1
0 as a mask, unnecessary gate insulator layer 3 on gate bridge 2 is removed, and finally polarizing plates 15 are placed in front and behind both substrates to complete the liquid crystal display device.
発明の詳細
な説明したように、本発明によればバックゲート効果を
低減できるため、TST特性の良好なアクティブマトリ
クスアレー並びに表示装置が製造できて、その実用上の
効果は大きい。As described in detail, according to the present invention, since the back gate effect can be reduced, active matrix arrays and display devices with good TST characteristics can be manufactured, and the practical effects thereof are significant.
第1図は本発明によるアクティブマトリクスアレーの一
実施例の断面図、第2図は本発明の実施例によるトラン
ジスタ特性と従来のトランジスタ特性の比較図、第3図
は本発明により製造された液晶デイスプレィの要部概略
断面図、第4図は液晶表示装置の等価回路図、第5図は
アクティブマトリクスアレーの1画素の概略平面図、第
6図は同アレーの1画素の概略断面図である。
■・・・・・・ガラス基板、2・・・・・・ゲート電極
(第一の導電層)、3・・・・・・ゲート絶縁層(第一
の絶縁層)、4・・・・・・非晶質シリコンを主成分と
する半導体層(第一の半導体層)、5・・・・・・半導
体保護層(第二の絶縁層)、6・・・・・・ドナーまた
はアクセプタとなる不純物を含む非晶質シリコン半導体
層(第二の半導体層)、7・・・・・・ソース電極(第
二の導電層)、8・・・・・・ドレイン電極(第二の導
電層)、9・・・・・・画素電極、10・・・・・・対
向ガラス基板、11・・・・・・対向透明電極、12・
・・・・・配向膜、13・・・・・・液晶、14・・・
・・・シール材、15・・・・・・偏光板、16・・・
・・・薄膜トランジスタ(TFT)、17・・・・・・
液晶セル、18・・・・・・走査信号線、19・・・・
・・映像信号線。FIG. 1 is a cross-sectional view of an embodiment of an active matrix array according to the present invention, FIG. 2 is a comparison diagram of transistor characteristics according to an embodiment of the present invention and conventional transistor characteristics, and FIG. 3 is a liquid crystal display manufactured according to the present invention. 4 is an equivalent circuit diagram of a liquid crystal display device, FIG. 5 is a schematic plan view of one pixel of an active matrix array, and FIG. 6 is a schematic sectional view of one pixel of the same array. . ■... Glass substrate, 2... Gate electrode (first conductive layer), 3... Gate insulating layer (first insulating layer), 4... ... Semiconductor layer containing amorphous silicon as a main component (first semiconductor layer), 5 ... Semiconductor protective layer (second insulating layer), 6 ... Donor or acceptor and an amorphous silicon semiconductor layer containing impurities (second semiconductor layer), 7... source electrode (second conductive layer), 8... drain electrode (second conductive layer); ), 9... pixel electrode, 10... counter glass substrate, 11... counter transparent electrode, 12...
...Alignment film, 13...Liquid crystal, 14...
...Sealing material, 15...Polarizing plate, 16...
...Thin film transistor (TFT), 17...
Liquid crystal cell, 18...Scanning signal line, 19...
...Video signal line.
Claims (5)
導電層と、前記第一の導電層を被覆するように形成れた
第一の絶縁層と、前記第一の絶縁層を介して前記第一の
導電層上に選択的に被着形成された半導体層と、前記半
導体層上の一部に形成された第二の絶縁層と前記第二の
絶縁層と前記半導体層と前記第一の絶縁層を介して前記
第一の導電層と一部重なり合うように選択的に形成され
た一対の第二の導電層から少なくともなるアクティブマ
トリクスアレーにおいて、前記第一の絶縁層の誘電率と
膜厚をそれぞれε_1、d_1とし、前記第二の絶縁層
の誘電率と膜厚をそれぞれε_2、d_2としたとき、
関係式 ε_1/d_1≧ε_2/d_2 を満たすことを特徴とするアクティブマトリクスアレー
。(1) A first conductive layer selectively formed on a transparent substrate, a first insulating layer formed to cover the first conductive layer, and a first insulating layer formed to cover the first conductive layer; a semiconductor layer selectively deposited on the first conductive layer via an insulating layer; a second insulating layer formed on a portion of the semiconductor layer; In an active matrix array comprising at least a semiconductor layer and a pair of second conductive layers selectively formed to partially overlap the first conductive layer with the first insulating layer interposed therebetween, the first insulating layer When the dielectric constant and thickness of the layer are ε_1 and d_1, respectively, and the dielectric constant and thickness of the second insulating layer are ε_2 and d_2, respectively,
An active matrix array characterized by satisfying the relational expression ε_1/d_1≧ε_2/d_2.
る工程と、前記第一の導電層を被覆するように第一の絶
縁層を形成する工程と、前記第一の絶縁層を介して前記
第一の導電層上に半導体層を選択的に被着形成する工程
と、前記半導体層上の一部に第二の絶縁層を選択的に形
成する工程と前記第二の絶縁層と前記半導体層と前記第
一の絶縁層を介して前記第一の導電層と一部重なり合う
ように選択的に形成された一対の第二の導電層を選択的
に形成する工程から少なくともなるアクティブマトリク
スアレーの製造方法において、前記第二の絶縁層は、前
記第一の絶縁層の誘電率と膜厚をそれぞれε_1、d_
1とし、前記第二の絶縁層の誘電率と膜厚をそれぞれε
_2、d_2としたとき、関係式 ε_1/d_1≧ε_2/d_2 を満たす条件で基板全面に堆積後、所望のレジストパタ
ーンを形成し、前記レジストパターンをマスクとしてド
ライエッチングする工程から製造することを特徴とする
アクティブマトリクスアレーの製造方法。(2) selectively forming a first conductive layer on a transparent substrate; forming a first insulating layer to cover the first conductive layer; a step of selectively depositing a semiconductor layer on the first conductive layer via an insulating layer; a step of selectively forming a second insulating layer on a portion of the semiconductor layer; a step of selectively forming a pair of second conductive layers that are selectively formed to partially overlap the first conductive layer through the insulating layer, the semiconductor layer, and the first insulating layer; In the method for manufacturing an active matrix array, the second insulating layer has a dielectric constant and a film thickness of the first insulating layer of ε_1 and d_, respectively.
1, and the dielectric constant and film thickness of the second insulating layer are respectively ε
When _2 and d_2, the resist is deposited on the entire surface of the substrate under conditions that satisfy the relational expression ε_1/d_1≧ε_2/d_2, then a desired resist pattern is formed, and the resist pattern is dry-etched using the resist pattern as a mask. A method for manufacturing an active matrix array.
クセプタとなる不純物を含む第二の半導体層を介在させ
ることを特徴とする請求項(2)記載のアクティブマト
リクスアレーの製造方法。(3) The method for manufacturing an active matrix array according to claim (2), characterized in that a second semiconductor layer containing an impurity serving as a donor or acceptor is interposed between the semiconductor layer and the second conductive layer.
リコンからなり、半導体層はシリコンを主成分とする非
単結晶半導体からなることを特徴とする請求項(3)記
載のアクティブマトリクスアレーの製造方法。(4) The active matrix according to claim (3), wherein the first insulating layer and the second insulating layer are made of at least silicon nitride, and the semiconductor layer is made of a non-single crystal semiconductor mainly composed of silicon. Array manufacturing method.
ィブマトリクスアレー基板と、透明電極を有する対向基
板間に光学異方性を有する材料を挟持する工程と前記両
基板の少なくとも一方には偏光板を配置する工程を含む
表示装置の製造方法において、前記対向基板をマスクと
して前記アクティブマトリクスアレー基板の絶縁体層の
露出部を食刻する工程を含むことを特徴とする表示装置
の製造方法。(5) A step of sandwiching a material having optical anisotropy between the active matrix array substrate manufactured by the manufacturing method according to claim (2) and a counter substrate having a transparent electrode, and at least one of the two substrates. A method for manufacturing a display device including a step of arranging a polarizing plate, the method comprising a step of etching an exposed portion of an insulator layer of the active matrix array substrate using the counter substrate as a mask. .
Priority Applications (1)
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---|---|---|---|
JP415990A JP2797584B2 (en) | 1990-01-11 | 1990-01-11 | Active matrix array, method of manufacturing the same, and method of manufacturing a display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP415990A JP2797584B2 (en) | 1990-01-11 | 1990-01-11 | Active matrix array, method of manufacturing the same, and method of manufacturing a display device |
Publications (2)
Publication Number | Publication Date |
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JPH03209777A true JPH03209777A (en) | 1991-09-12 |
JP2797584B2 JP2797584B2 (en) | 1998-09-17 |
Family
ID=11576967
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JP415990A Expired - Fee Related JP2797584B2 (en) | 1990-01-11 | 1990-01-11 | Active matrix array, method of manufacturing the same, and method of manufacturing a display device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
US5888855A (en) * | 1994-12-14 | 1999-03-30 | Kabushiki Kaisha Toshiba | Method of manufacturing active matrix display |
Citations (4)
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---|---|---|---|---|
JPS59228289A (en) * | 1983-06-09 | 1984-12-21 | 富士通株式会社 | Composing of liquid crystal display panel |
JPS62143028A (en) * | 1985-12-17 | 1987-06-26 | Sanyo Electric Co Ltd | Liquid crystal displaying device |
JPS63119256A (en) * | 1986-11-06 | 1988-05-23 | Matsushita Electric Ind Co Ltd | Manufacture of active matrix substrate |
JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
-
1990
- 1990-01-11 JP JP415990A patent/JP2797584B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59228289A (en) * | 1983-06-09 | 1984-12-21 | 富士通株式会社 | Composing of liquid crystal display panel |
JPS62143028A (en) * | 1985-12-17 | 1987-06-26 | Sanyo Electric Co Ltd | Liquid crystal displaying device |
JPS63119256A (en) * | 1986-11-06 | 1988-05-23 | Matsushita Electric Ind Co Ltd | Manufacture of active matrix substrate |
JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5888855A (en) * | 1994-12-14 | 1999-03-30 | Kabushiki Kaisha Toshiba | Method of manufacturing active matrix display |
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
US6297862B1 (en) | 1996-10-16 | 2001-10-02 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6388721B1 (en) | 1996-10-16 | 2002-05-14 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6573955B2 (en) | 1996-10-16 | 2003-06-03 | Seiko Epson Corporation | Capacitance substrate for a liquid crystal device and a projection type display device |
CN1294451C (en) * | 1996-10-16 | 2007-01-10 | 精工爱普生株式会社 | Base plate for liquid crystal apparatus, liquid crystal apparatus and projecting display device |
Also Published As
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JP2797584B2 (en) | 1998-09-17 |
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