JPH03257829A - Manufacture of transparent insulating layer and indicator - Google Patents
Manufacture of transparent insulating layer and indicatorInfo
- Publication number
- JPH03257829A JPH03257829A JP5530490A JP5530490A JPH03257829A JP H03257829 A JPH03257829 A JP H03257829A JP 5530490 A JP5530490 A JP 5530490A JP 5530490 A JP5530490 A JP 5530490A JP H03257829 A JPH03257829 A JP H03257829A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- insulating layer
- transparent
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000011159 matrix material Substances 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910000077 silane Inorganic materials 0.000 claims abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 5
- 239000001257 hydrogen Substances 0.000 claims abstract description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 238000000354 decomposition reaction Methods 0.000 claims abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 1
- 229910003437 indium oxide Inorganic materials 0.000 claims 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims 1
- 229910001887 tin oxide Inorganic materials 0.000 claims 1
- XKMRRTOUMJRJIA-UHFFFAOYSA-N ammonia nh3 Chemical compound N.N XKMRRTOUMJRJIA-UHFFFAOYSA-N 0.000 abstract 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract 1
- 239000012495 reaction gas Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 210000002858 crystal cell Anatomy 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、表示装置や受光素子等に広く用いられ、特に
ラクティプマトリクス型液晶表示装置等の透明導電層上
への絶縁層の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is widely used in display devices, light-receiving elements, etc., and particularly relates to a method for manufacturing an insulating layer on a transparent conductive layer of a lactiper matrix type liquid crystal display device, etc. It is.
従来の技術
アクティブマトリクス型液晶表示装置（以下ではＡＭ−
ＬＣＤと略記する）は高画質フラットデイスプレィを実
現するデバイスとして最も有望であり、その研究開発は
非常に活発に行われている。Conventional technology active matrix liquid crystal display device (hereinafter referred to as AM-
(abbreviated as LCD) is the most promising device for realizing a high-quality flat display, and its research and development is being carried out very actively.
また、一部商品化も進められている。第３図はその等価
回路を示しておシ、１６は薄膜トランジスｐ （Ｔｈ１
ｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ ： Ｔ Ｆ Ｔ
と以下略記する）、１７は液晶セル、１８は走査信号線
（ゲートパスライン）、１９は映像信号線（ソースパス
ライン）である。走査信号線１８にＴＦＴ１６がＯＮす
るように順次ゲート信号を印加し、映像信号線１９よシ
ゲート１ラインに対応した映像信号を液晶セル１７に書
き込ませる線順次走査によってＣＲＴと同等の機能が賦
与される。Commercialization of some products is also underway. Figure 3 shows the equivalent circuit. 16 is a thin film transistor p (Th1
n Film Transistor: T F T
17 is a liquid crystal cell, 18 is a scanning signal line (gate pass line), and 19 is a video signal line (source pass line). A function equivalent to that of a CRT is provided by line sequential scanning in which a gate signal is sequentially applied to the scanning signal line 18 so that the TFT 16 is turned on, and a video signal corresponding to one line of gates is written from the video signal line 19 to the liquid crystal cell 17. Ru.
発明が解決しようとする課題
しかしながら上記のような構成の場合、ゲート電極とド
レイン電極との重な９部分には寄生容量ＣＧＤが生じる
。この画素にかかわる全容量をＣｔｏｔａｌｓゲート電
位の変化分をΔｖＧとすると、この寄生容量ＣＧＤによ
りゲートがＯＮ状態からＯＦＦ状態になった時に、
ΔＶ＝ΔｖＧ ” ＣＧＤ ／ Ｃｔｏｔａｌだけドレ
イン電位、即ち、画素電位が下がる。しかも、このΔＶ
はアクティブマトリクスアレイ製造プロセス上のばらつ
きにより基板間はもちろんのこと同一基板内でもばらつ
くため、単純に対向電位にあるオフセント電位全与えて
も直流成分を完全に排除することはできない。従って、
液晶セルには必ずある直流電位が印加されるので、液晶
セルの劣化が加速され、表示素子としての信頼性が不充
分であるという課題を有していた。Problems to be Solved by the Invention However, in the case of the above structure, a parasitic capacitance CGD occurs in the 9 parts where the gate electrode and the drain electrode overlap. If the total capacitance related to this pixel is Ctotals, and the change in gate potential is ΔvG, then when the gate changes from the ON state to the OFF state due to this parasitic capacitance CGD, the drain potential, that is, the pixel potential, increases by CGD/Ctotal. decreases.Moreover, this ΔV
Because of variations in the active matrix array manufacturing process, not only between substrates but also within the same substrate, the direct current component cannot be completely eliminated simply by applying the entire offset potential at the opposing potential. Therefore,
Since a certain direct current potential is always applied to a liquid crystal cell, there has been a problem in that the deterioration of the liquid crystal cell is accelerated and its reliability as a display element is insufficient.
本発明はかかる点に鑑み、かかる直流成分を排除するこ
とにより信頼性が高く、高品質の表示装置の製造方法を
提供することを目的とする。In view of this point, it is an object of the present invention to provide a method for manufacturing a highly reliable and high quality display device by eliminating such direct current components.
課題を解決するための手段
本発明は、前述の課題を解決するため、アクティブマト
リクスアレイ全面に、少なくともシラン。Means for Solving the Problems The present invention solves the above-mentioned problems by applying at least silane to the entire surface of an active matrix array.
アンモニア、窒素及び水素を含む反応ガスを透明導電層
の形成温度以下でグロー放電分解により絶縁層となる窒
化シリコンを形成し、直流成分を排除する。Silicon nitride, which will become an insulating layer, is formed by glow discharge decomposition of a reactive gas containing ammonia, nitrogen, and hydrogen at a temperature below the formation temperature of the transparent conductive layer, and direct current components are eliminated.
作 用
本発明は前記した方法により製造すると、液晶セルに印
加される直流成分を排除することができ、信頼性の高い
高品質の表示装置を製造することができる。Operation When the present invention is manufactured by the method described above, the direct current component applied to the liquid crystal cell can be eliminated, and a highly reliable and high quality display device can be manufactured.
実施例
第２図は本発明の一実施例における液晶表示素子用のア
クティブマトリクスアレイの１画素の概略平面図を示し
、第１図は第２図に示された平面図のＡ−Ａ’縁線上断
面図を示している。これらの図面を用いて説明する。Embodiment FIG. 2 shows a schematic plan view of one pixel of an active matrix array for a liquid crystal display device according to an embodiment of the present invention, and FIG. 1 shows the AA' edge of the plan view shown in FIG. A line cross-sectional view is shown. This will be explained using these drawings.
まず、ガラス基板１上にゲート電極と走査信号線を兼ね
る第一の導電層２を例えばＣｒで選択的に被着形成する
。その後、第一の絶縁層３として例えば窒化シリコンと
、ドナーまたはアクセプターとなる不純物をほとんど含
まない非晶質シリコン半導体層（以下１−ａ−９ｉと略
記する）４と半導体保護層５を例えば窒化シリコンをプ
ラズマＣＶＤ法により選択的に被着形成する。次に、ソ
ース・ドレインと半導体層との接合のオーミック性を改
善するためドナーとなる不純物としてリンを多く含む非
晶質シリコン半導体層６（以下、ｎ” −ａ −Ｓｉと
略記する）をプラズマＣＶＤ法により堆積し、通常のフ
ォトリソグラフィー及びエツチングによりこれらの半導
体層を島状にパターニングする。そして映像信号線とＴ
ＰＴのソースを兼ねる第二の導電層７及びＴＰＴのドレ
インとなる第二の導電層８を例えばＡｌにより選択的に
被着形成する。そして、チャンネル部のｎ”−ａ−８ｉ
をソース・ドレイン及び半導体保護層をマスクとしてエ
ツチング除去する。最後に画素電極となる第一の透明導
電層９としてＩ Ｔ Ｏ（Ｉｎｄｉｕｍｅ−Ｔｉｎ−０
ｘｉｄｅ ）を基板温度２００ ”Ｃでスパッタ法によ
り、ドレインと接続するように選択的に被着形成する。First, a first conductive layer 2, which serves as a gate electrode and a scanning signal line, is selectively deposited on a glass substrate 1 using, for example, Cr. Thereafter, a first insulating layer 3 made of, for example, silicon nitride, an amorphous silicon semiconductor layer (hereinafter abbreviated as 1-a-9i) 4 containing almost no impurity serving as a donor or acceptor, and a semiconductor protective layer 5 made of, for example, nitride. Silicon is selectively deposited by plasma CVD. Next, in order to improve the ohmic properties of the junction between the source/drain and the semiconductor layer, an amorphous silicon semiconductor layer 6 (hereinafter abbreviated as n"-a-Si) containing a large amount of phosphorus as an impurity serving as a donor is deposited using plasma. These semiconductor layers are deposited by the CVD method and patterned into island shapes by ordinary photolithography and etching.Then, video signal lines and T
A second conductive layer 7 which also serves as the source of the PT and a second conductive layer 8 which serves as the drain of the TPT are selectively deposited using, for example, Al. And channel part n”-a-8i
is removed by etching using the source/drain and semiconductor protective layer as a mask. Finally, ITO (Indium-Tin-0) is used as the first transparent conductive layer 9 which becomes the pixel electrode.
xide) is selectively deposited by sputtering at a substrate temperature of 200''C so as to be connected to the drain.
そして、基板温度１５０〜２００″Ｃ，シラン＝１ｇｓ
ｃｃＭ、アンモニア＝ｓｃｓＳＣＣＭ、水素＝１ｓｏｓ
ｃｃＭ、ｉｌ素＝１５０８ＣＣＭの流量で圧力＝０．９
Ｔｏｒｒ 、ＲＦ （１３，５６ＭＨｚ）パワー＝３
００Ｗの条件で窒化シリコン層１ｏを４０００人堆積し
、アクティブマトリクスアレイを得る。And, substrate temperature 150~200''C, silane = 1gs
ccM, ammonia = scsSCCM, hydrogen = 1sos
ccM, il element = 1508 CCM flow rate and pressure = 0.9
Torr, RF (13,56MHz) power = 3
4000 silicon nitride layers 1o are deposited under the condition of 00W to obtain an active matrix array.
上述のアクティブマトリクスアレイと一生面上に第二の
透明導電層１２を被着した対向ガラス基板１１の両方に
ポリイミド樹脂を塗布し硬化させた後、配向処理を行っ
て配向膜１３を形成した後液晶１４として、例えばツイ
スト・ネマチック液晶を両基板間に封入し、さらに上下
に偏光板１５を配置すればよい。After coating and curing polyimide resin on both the active matrix array described above and the counter glass substrate 11 on which the second transparent conductive layer 12 is coated, an alignment treatment is performed to form an alignment film 13. As the liquid crystal 14, for example, twisted nematic liquid crystal may be sealed between both substrates, and polarizing plates 15 may be placed above and below.
ソースパスライン電極及びゲートバヌライン電極の取シ
呂しは窒化シリコン層１ｏ堆積後、通常のフォトエツチ
ングにより取り出しても良いし、または液晶セル組立後
、対向ガラス基板をマスクとして窒化シリコン層１ｏを
エツチングして電極をとシだしても良い。The source pass line electrode and gate vane line electrode may be removed by normal photoetching after depositing the silicon nitride layer 1o, or by etching the silicon nitride layer 1o using the opposing glass substrate as a mask after assembling the liquid crystal cell. You can also pull out the electrode.
尚、本実施例では、窒化シリコン層１ｏはアクティブマ
トリクスアレイ上のみに堆積したが、液晶セルへの直流
成分をよシ完壁に排除するために、対向基板上にも同様
に窒化シリコン層を堆積してもよい。In this example, the silicon nitride layer 1o was deposited only on the active matrix array, but in order to completely eliminate the direct current component to the liquid crystal cell, a silicon nitride layer was also deposited on the opposing substrate. May be deposited.
また、本実施例では、ゲート電極２の材料としてＣｒと
したが、Ｔａ 、 Ｔ ｉ 、 Ｍｏ 、 Ｎｉ 、
Ｎｉ −Ｏｒ金合金これらの金属の珪化物等、ＴＰＴの
ゲート電極の材料として使用されるものならばいずれも
使用し得る。また、ゲート絶縁体層３の材料としては、
窒化シリコン、酸化シリコンや金属醸化物なども用いら
れる。Further, in this example, Cr was used as the material of the gate electrode 2, but Ta, Ti, Mo, Ni,
Any material used as a material for the gate electrode of TPT can be used, such as Ni--Or gold alloy, silicides of these metals, etc. Furthermore, the material for the gate insulator layer 3 is as follows:
Silicon nitride, silicon oxide and metal compounds are also used.
また、第一、第二の半導体層の材料として、非晶質シリ
コンを使用したが、多結晶シリコンや再結晶化したシリ
コンを用いても問題ない。Furthermore, although amorphous silicon is used as the material for the first and second semiconductor layers, polycrystalline silicon or recrystallized silicon may also be used without any problem.
さらに、絵素電極の材料としては、Ｉｎ２ｏ３゜Ｓｎ○
２或はこれらの混合物等の透明導電材料が使用できる。Furthermore, the material for the picture element electrode is In2o3゜Sn○
Transparent conductive materials such as 2 or a mixture thereof can be used.
また、ソース電極及びドレイン電極と絵素電極とを同時
に形成する場合には、ソース電極及びドレイン電極の材
料として、Ｉｎ２ｏ３．Ｓ！１ｏ２或はこれらの混合物
等の透明導電材料が使用できる。ソース電極及びドレイ
ン電極と絵素電極とを別々に形成する場合には、ソース
電極及びドレイン電極の材料としては、Ａｌ、Ｍｏ、Ｔ
ａ、Ｔｉ。In addition, when forming the source electrode, the drain electrode, and the picture element electrode at the same time, In2o3. S! Transparent conductive materials such as 1o2 or mixtures thereof can be used. When forming the source electrode and drain electrode and the picture element electrode separately, the material of the source electrode and the drain electrode is Al, Mo, T.
a.Ti.
Ｏｒやこれらの金属の珪化物などが使用できる。Or, silicides of these metals, etc. can be used.
なお、この場合、ソース及びドレイン電極は、単層のみ
ならず複数層で形成して冗長性を付加することができる
。Note that in this case, the source and drain electrodes can be formed not only in a single layer but also in multiple layers to add redundancy.
また、本実施例では蓄積容量を設けなかったが、画質を
向上させるために蓄積容量となるＮ、極の一方を、例え
ば、第一の金属層と同レベルに設け、第一の透明絶縁層
を介して絵素電極をもう一方の蓄積容量電極とすること
により蓄積容量を付加することもできる。Further, in this example, no storage capacitor was provided, but in order to improve image quality, one of the N and poles serving as the storage capacitor was provided at the same level as the first metal layer, and the first transparent insulating layer was It is also possible to add a storage capacitor by using the picture element electrode as the other storage capacitor electrode.
発明の詳細
な説明したように、本発明によれば液晶セルに印加され
る直流電圧成分を排除できるため、信頼性が向上し、高
品質の表示素子が製造でき、その実用上の効果は大きい
。As described in detail, according to the present invention, since the DC voltage component applied to the liquid crystal cell can be eliminated, reliability is improved and high quality display elements can be manufactured, and its practical effects are significant. .
第１図、は本発明の一実施例による液晶表示装置のアク
ティブマトリクヌアレイ部の１画素の概略断面図、第２
図は同装置の１画素の概略平面図、第３図は液晶表示装
置の等価回路図である。
１・・・・・・ガラス基板、２・・・・・・第一の導電
層、３・・・・・・第一の絶縁層、４・・・・・・非晶
質シリコン半導体層、６・・・・・・半導体保護層（第
二の絶縁層）、６・・・・・・非晶質シリコン半導体層
ｖ７，８・・・・・・第二の導電層、９・・・・・・第
一の透明導電層、１０・・・・・・窒化シリコン層、１
１・・・・・・対向ガラス基板、１２・・・・・・第二
の透明導電層、１３・・・・・・配向膜、１４−・・・
液晶、１６・・・・・・偏光板。FIG. 1 is a schematic cross-sectional view of one pixel of an active matrix array portion of a liquid crystal display device according to an embodiment of the present invention, and FIG.
The figure is a schematic plan view of one pixel of the device, and FIG. 3 is an equivalent circuit diagram of the liquid crystal display device. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... First conductive layer, 3... First insulating layer, 4... Amorphous silicon semiconductor layer, 6... Semiconductor protective layer (second insulating layer), 6... Amorphous silicon semiconductor layer v7, 8... Second conductive layer, 9... ...First transparent conductive layer, 10...Silicon nitride layer, 1
DESCRIPTION OF SYMBOLS 1... Counter glass substrate, 12... Second transparent conductive layer, 13... Alignment film, 14-...
Liquid crystal, 16...Polarizing plate.
Claims (7)
ズあるいはその両方を少なくとも含む透明導電層上に窒
化シリコンからなる透明絶縁層を製造する方法であって
、前記透明絶縁層を少なくともシラン、アンモニア、窒
素及び水素を含む反応ガスを前記透明導電層の形成温度
以下でグロー放電分解により形成することを特徴とする
透明絶縁層の製造方法。(1) A method for manufacturing a transparent insulating layer made of silicon nitride on a transparent conductive layer containing at least indium oxide, tin oxide, or both formed on a substrate, the transparent insulating layer being made of at least silane, ammonia, etc. A method for producing a transparent insulating layer, characterized in that a reactive gas containing nitrogen and hydrogen is formed by glow discharge decomposition at a temperature below the formation temperature of the transparent conductive layer.
１，Ｎ＿２とすると、次の関係式 １／６≦Ｎ＿１／Ｎ＿２≦１／２ を満たすことを特徴とする請求項１に記載の透明絶縁層
の製造方法。(2) The flow rate of silane and the flow rate of ammonia are each N_
1, N_2, the following relational expression 1/6≦N_1/N_2≦1/2 is satisfied.
と、前記第一の導電層を被覆するように形成された第一
の絶縁層と、前記第一の絶縁層を介して前記第一の導電
層上に選択的に被着形成された半導体層と、前記半導体
層と前記第一の絶縁層を介して前記第一の導電層と一部
重なり合うように選択的に形成された対となる第二の導
電層と前記対となる第二の導電層の一方に電気的に接触
するように選択的に形成された第一の透明電極から少な
くともなるアクティブマトリクスアレイ上に、請求項１
に記載の製造方法で窒化シリコン層を形成したアクティ
ブマトリクスアレイ基板と第二の透明電極を有する対向
基板間に光学異方性を有する材料を挟持する工程と前記
両基板の少なくとも一方には偏光板を配置する工程を含
むことを特徴とする表示装置の製造方法。(3) A first conductive layer selectively formed on a transparent substrate, a first insulating layer formed to cover the first conductive layer, and a first insulating layer. a semiconductor layer selectively deposited on the first conductive layer through the semiconductor layer; and a semiconductor layer selectively deposited on the first conductive layer through the semiconductor layer and the first insulating layer so as to partially overlap with the first conductive layer. on an active matrix array comprising at least a pair of second conductive layers formed and a first transparent electrode selectively formed so as to be in electrical contact with one of the second conductive layers; , claim 1
A step of sandwiching a material having optical anisotropy between an active matrix array substrate on which a silicon nitride layer is formed by the manufacturing method described in , and a counter substrate having a second transparent electrode, and a polarizing plate on at least one of the two substrates. 1. A method for manufacturing a display device, comprising the step of arranging.
と、前記第一の導電層を被覆するように形成された第一
の絶縁層と、前記第一の絶縁層を介して前記第一の導電
層上に選択的に被着形成された半導体層と、前記半導体
層と前記第一の絶縁層を介して前記第一の導電層と一部
重なり合うように選択的に形成された対となる第一の透
明電極から少なくともなるアクティブマトリクスアレイ
上に、請求項１に記載の製造方法で窒化シリコン層を形
成したアクティブマトリクスアレイ基板と第二の透明電
極を有する対向基板間に光学異方性を有する材料を挟持
する工程と前記両基板の少なくとも一方には偏光板を配
置する工程を含むことを特徴とする表示装置の製造方法
。(4) A first conductive layer selectively formed on a transparent substrate, a first insulating layer formed to cover the first conductive layer, and a first insulating layer. a semiconductor layer selectively deposited on the first conductive layer through the semiconductor layer; and a semiconductor layer selectively deposited on the first conductive layer through the semiconductor layer and the first insulating layer so as to partially overlap with the first conductive layer. Between an active matrix array substrate in which a silicon nitride layer is formed by the manufacturing method according to claim 1 on an active matrix array consisting of at least first transparent electrodes forming a pair, and a counter substrate having a second transparent electrode. A method for manufacturing a display device, comprising the steps of sandwiching a material having optical anisotropy between the two substrates, and arranging a polarizing plate on at least one of the two substrates.
またはアクセプタとなる不純物を含む第二の半導体層を
介在させることを特徴とする請求項３または４に記載の
表示装置の製造方法。(5) Manufacturing a display device according to claim 3 or 4, characterized in that a second semiconductor layer containing an impurity serving as a donor or an acceptor is interposed between the semiconductor layer and the second conductive layer. Method.
も窒化シリコンからなり、前記半導体層はシリコンを主
成分とする非単結晶半導体からなることを特徴とする請
求項３または４に記載の表示装置の製造方法。(6) The first insulating layer and the second insulating layer are made of at least silicon nitride, and the semiconductor layer is made of a non-single crystal semiconductor containing silicon as a main component. A method of manufacturing the described display device.
リクスアレー基板の絶縁体層の露出部を食刻する工程を
含むことを特徴とする請求項３または４に記載の表示装
置の製造方法。(7) The method for manufacturing a display device according to claim 3 or 4, further comprising the step of etching an exposed portion of an insulator layer of the active matrix array substrate using the counter substrate as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5530490A JPH03257829A (en) | 1990-03-07 | 1990-03-07 | Manufacture of transparent insulating layer and indicator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5530490A JPH03257829A (en) | 1990-03-07 | 1990-03-07 | Manufacture of transparent insulating layer and indicator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03257829A true JPH03257829A (en) | 1991-11-18 |
Family
ID=12994831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5530490A Pending JPH03257829A (en) | 1990-03-07 | 1990-03-07 | Manufacture of transparent insulating layer and indicator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03257829A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100577781B1 (en) * | 1999-04-23 | 2006-05-10 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing passivation layer in LCD device |
| US10222674B2 (en) | 2016-04-19 | 2019-03-05 | Sage Electrochromics, Inc. | Electrochromic device including a transparent conductive oxide layer and a bus bar and a process of forming the same |
| US11714327B2 (en) | 2017-09-12 | 2023-08-01 | Sage Electrochromics, Inc. | Non-light-emitting variable transmission device and a method of forming the same |
-
1990
- 1990-03-07 JP JP5530490A patent/JPH03257829A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100577781B1 (en) * | 1999-04-23 | 2006-05-10 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing passivation layer in LCD device |
| US10222674B2 (en) | 2016-04-19 | 2019-03-05 | Sage Electrochromics, Inc. | Electrochromic device including a transparent conductive oxide layer and a bus bar and a process of forming the same |
| US10788724B2 (en) | 2016-04-19 | 2020-09-29 | Sage Electrochromics, Inc. | Electrochromic device including a transparent conductive oxide layer and a bus bar and a process of forming the same |
| US11714327B2 (en) | 2017-09-12 | 2023-08-01 | Sage Electrochromics, Inc. | Non-light-emitting variable transmission device and a method of forming the same |
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