JP2505662B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2505662B2 JP2505662B2 JP3174186A JP17418691A JP2505662B2 JP 2505662 B2 JP2505662 B2 JP 2505662B2 JP 3174186 A JP3174186 A JP 3174186A JP 17418691 A JP17418691 A JP 17418691A JP 2505662 B2 JP2505662 B2 JP 2505662B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- thin film
- film transistor
- manufacturing
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 title claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜トランジスタの製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.
【０００２】[0002]
【従来の技術】薄膜トランジスタは、低電圧、低消費電
力、軽量および高画質を実現することができるという長
所のために、活性マトリックス液晶表示装置の素子とし
てよく用いられている。2. Description of the Related Art A thin film transistor is often used as an element of an active matrix liquid crystal display device because of its advantages of low voltage, low power consumption, light weight and high image quality.
【０００３】一般に、この薄膜トランジスタの製造方法
においては、図２に示すように、ガラス基板１上にＩＴ
Ｏ（Indium Tin Oxide）をコーティング（coating ）し
た後、所定のマスクを用いてゲート電極２を形成し、こ
のゲート電極２上に化学反応気相装置［Plasma Enhance
ment Chemical Vapor Deposition(PECVD) ］を用いてゲ
ート絶縁層３を３０００オングストロームの厚さに蒸着
し、前記ゲート絶縁層３をエッチングして再び化学反応
気相装置を用いて１５００オングストロームの厚さに非
晶質半導体層４とｎ+ オーミック層５を順次蒸着した
後、透明導電膜である画素電極８をゲート絶縁層３上に
蒸着する。次いで、スパッタ装置を用いて４０００オン
グストローム程度の厚さに蒸着してソース電極６とドレ
イン電極７を形成する。Generally, in this method of manufacturing a thin film transistor, as shown in FIG.
After coating O (Indium Tin Oxide), a gate electrode 2 is formed using a predetermined mask, and a chemical reaction gas phase device [Plasma Enhance] is formed on the gate electrode 2.
Chemical Chemical Vapor Deposition (PECVD)] is used to deposit the gate insulating layer 3 to a thickness of 3000 angstroms, the gate insulating layer 3 is etched, and the thickness of the gate insulating layer 3 is set to 1500 angstroms again using a chemical reaction vapor phase apparatus. After the crystalline semiconductor layer 4 and the n + ohmic layer 5 are sequentially deposited, the pixel electrode 8 which is a transparent conductive film is deposited on the gate insulating layer 3. Then, the source electrode 6 and the drain electrode 7 are formed by vapor deposition to a thickness of about 4000 Å using a sputtering device.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記の
ように形成された薄膜トランジスタでは非晶質半導体層
４とソース／ドレイン電極６、７とのオーミック接触の
ためのオーミック層の形成の際、チャンネルの上部に残
っているｎ+ オーミック層５の残滓をエッチングで除去
する際に困難さがあり、汚れによる薄膜トランジスタの
破損が生ずるという問題点があり、さらに、この薄膜ト
ランジスタのオフ電流の減少に限界があった。However, in the thin film transistor formed as described above, when the ohmic layer for ohmic contact between the amorphous semiconductor layer 4 and the source / drain electrodes 6 and 7 is formed, a channel of the channel is formed. There is a problem in removing the residue of the n + ohmic layer 5 remaining on the upper part by etching, and there is a problem that the thin film transistor is damaged due to dirt, and further, there is a limit to reduction of the off current of the thin film transistor. It was
【０００５】本発明は前記のような点に鑑みてなされた
ものであり、その目的は、薄膜トランジスタの製造の際
に別途にｎ+ オーミック層を形成する必要がない方法を
提供するものである。The present invention has been made in view of the above points, and an object thereof is to provide a method in which it is not necessary to separately form an n + ohmic layer at the time of manufacturing a thin film transistor.
【０００６】[0006]
【問題点を解決するための手段】前記目的を達成するた
めに、請求項１に記載の本発明の薄膜トランジスタの製
造方法は、基板、ゲート電極、ゲート絶縁層、半導体と
ドレイン電極およびソース電極を有するＴＦＴの前記半
導体上にドレイン電極およびソース電極を形成する薄膜
トランジスタの製造方法において、前記半導体上にＡｒ
とＰＨ3 を所定の比率に混合して、前記半導体層とオー
ミック接触するように第１の金属層を所定の厚さに蒸着
形成する段階と、前記蒸着された第１の金属層上に第２
の金属層を所定の時間前記蒸着形成する段階を備えて、
前記第１および第２金属層がドレイン電極あるいはソー
ス電極を形成することを特徴とする。In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention according to claim 1 comprises a substrate, a gate electrode, a gate insulating layer, a semiconductor and a drain electrode, and a source electrode. In a method of manufacturing a thin film transistor, in which a drain electrode and a source electrode are formed on the semiconductor of the TFT having, Ar on the semiconductor is provided.
And PH 3 are mixed in a predetermined ratio to form a first metal layer with a predetermined thickness by vapor deposition so as to make ohmic contact with the semiconductor layer, and a first metal layer is formed on the deposited first metal layer. Two
The step of depositing the metal layer for a predetermined period of time,
The first and second metal layers form a drain electrode or a source electrode.
【０００７】また、請求項２に記載の本発明の薄膜トラ
ンジスタの製造方法は、第１の金属層の形成段階におい
てＡｒとＰＨ3 のガス混合比率は９９：１であることを
特徴とする。The method of manufacturing a thin film transistor according to the second aspect of the present invention is characterized in that the gas mixture ratio of Ar and PH 3 is 99: 1 in the step of forming the first metal layer.
【０００８】また、請求項３に記載の薄膜トランジスタ
の製造方法は、第１の金属層は、ＡｒとＰＨ3 の混合ガ
ス雰囲気下で、Ａｌ、Ｃｒ、Ｍｏ、Ｔｉの中でいずれか
の一つの金属材質で蒸着形成されることを特徴とする。In the method of manufacturing a thin film transistor according to a third aspect of the present invention, the first metal layer is formed of any one of Al, Cr, Mo and Ti in a mixed gas atmosphere of Ar and PH 3 . It is characterized in that it is formed by vapor deposition with a metal material.
【０００９】また、請求項４に記載の薄膜トランジスタ
の製造方法は、第２の金属層は、Ａｌ、Ｃｒ、Ｍｏ、Ｔ
ｉの中でいずれかの一つの金属材質で形成されることを
特徴とする。In the method of manufacturing a thin film transistor according to claim 4, the second metal layer is made of Al, Cr, Mo, T.
It is characterized in that it is formed of any one metal material in i.
【００１０】また、請求項５に記載の薄膜トランジスタ
の製造方法は、第１の金属層の厚さは、５００オングス
トローム乃至１０００オングストロームであることを特
徴とする、請求項１に記載の薄膜トランジスタの製造方
法。The method of manufacturing a thin film transistor according to claim 5 is characterized in that the thickness of the first metal layer is 500 angstroms to 1000 angstroms. .
【００１１】また、請求項６に記載の薄膜トランジスタ
の製造方法は、第２の金属層の厚さは、３０００オング
ストローム乃至５０００オングストロームであることを
特徴とする。The method of manufacturing a thin film transistor according to claim 6 is characterized in that the thickness of the second metal layer is 3000 angstroms to 5000 angstroms.
【００１２】また、請求項７に記載の薄膜トランジスタ
の製造方法は、第２の金属層の厚さは、第１の金属層の
厚さより厚く形成されることを特徴とする。The method of manufacturing a thin film transistor according to claim 7 is characterized in that the second metal layer is formed to be thicker than the first metal layer.
【００１３】また、請求項８に記載の薄膜トランジスタ
の製造方法は、形成された金属層の全厚さは、３５００
オングストローム乃至６０００オングストロームである
ことを特徴とする。Further, in the method of manufacturing a thin film transistor according to claim 8, the total thickness of the formed metal layer is 3500.
It is characterized in that it is from angstrom to 6000 angstrom.
【００１４】[0014]
【作用】本発明によれば、ＰＨ3 およびＡｒガスを一定
の比率に混合した雰囲気中にて一定の厚さの第１の金属
層を蒸着してその第１の金属層に少量のＰＨ3 が含まれ
るようにし、次いでＡｒガス雰囲気下でその第１の金属
層上に一定の厚さの第２の金属層を蒸着するようにした
ので、ソースおよびドレイン電極ｎ+ オーミック層の役
割を同時にすることができる。According to the present invention, a first metal layer having a constant thickness is vapor-deposited in an atmosphere in which PH 3 and Ar gas are mixed at a constant ratio, and a small amount of PH 3 is deposited on the first metal layer. And then depositing a second metal layer of a certain thickness on the first metal layer under Ar gas atmosphere, so that the role of the source and drain electrode n + ohmic layer can be achieved at the same time. can do.
【００１５】[0015]
【実施例】以下、本発明の好ましい実施例を図１を参照
して詳細に説明する。図１において、従来と同一部分に
は同一符号を付してある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to FIG. In FIG. 1, the same parts as those of the related art are designated by the same reference numerals.
【００１６】図１は、本発明が適用された薄膜トランジ
スタの一実施を示す断面図であって、ガラス基板１上に
ＩＴＯをコーティングした後、所定のマスクを用いてゲ
ート電極２を形成し、このゲート電極２上に化学反応気
相装置を用いてゲート絶縁層３を３０００オングストロ
ームの厚さに蒸着し、前記ゲート絶縁層３をエッチング
して再び化学反応気相装置を用いて１５００オングスト
ロームの厚さに例えば水素化アモルファスＳｉからなる
非晶質半導体層４を蒸着し、透明導電膜である画素電極
８をゲート絶縁層３上に蒸着する。FIG. 1 is a cross-sectional view showing an embodiment of a thin film transistor to which the present invention is applied. After a glass substrate 1 is coated with ITO, a gate electrode 2 is formed by using a predetermined mask. A gate insulating layer 3 is deposited on the gate electrode 2 to a thickness of 3000 Å using a chemical reaction vapor deposition apparatus, the gate insulating layer 3 is etched, and a thickness of 1500 Å is applied again using a chemical reaction vapor deposition apparatus. Then, an amorphous semiconductor layer 4 made of , for example, hydrogenated amorphous Si is deposited, and a pixel electrode 8 which is a transparent conductive film is deposited on the gate insulating layer 3.
【００１７】次いで、スパッタ装置のミキシングチャン
バで、Ａｒ９９％とＰＨ3 １％を混合したガス雰囲気中
で、前記のように形成された非晶質半導体層４上に一定
時間第１の金属層を蒸着（deposition）して、５００オ
ングストローム〜１０００オングストローム程度の厚さ
に保持する。この第１の金属層の材質としては、ゲート
絶縁層３との間で電子の移動を可能とするものであれば
よく、例えば次の第２の金属層と同様のＡｌ、Ｃｒ、Ｍ
ｏ、Ｔｉ等を用いることができる。また、Ａｒに対する
ＰＨ 3 の割合は、前記１％以外でもよく、この割合を変
化させることにより、前記第１の金属層のオーミック層
として作用する部分の状態を調整することができる。そ
の後、Ａｌ、Ｃｒ、Ｍｏ、Ｔｉ等の金属ターゲットを用
いて、Ａｒ雰囲気中で第２の金属層を一定時間蒸着して
３０００オングストローム〜５０００オングストローム
の厚さを有するようにする。同時に形成されるこの金属
層の断面は第１および第２の金属層の区分なしに図面に
示されている。このとき、第１の金属層は通常の金属電
極材質にＰＨ3 が少量含まれた層として形成され、第２
の金属層は通常の金属層と同様な型である。したがっ
て、第１の金属層はオーミック層のような効果を有する
ために、従来のようにｎ+ オーミック層の形成のために
別途の工程が必要ではない。Then, a first metal layer is formed on the amorphous semiconductor layer 4 formed as described above for a certain period of time in a gas atmosphere in which Ar 99% and PH 3 1% are mixed in a mixing chamber of a sputtering apparatus. Deposition is performed and the thickness is maintained at about 500 Å to 1000 Å . The material of the first metal layer is a gate
If it is possible to move electrons between the insulating layer 3 and
Well, for example, Al, Cr, M similar to the following second metal layer
O, Ti, etc. can be used. Also, for Ar
The proportion of PH 3 may be other than the above-mentioned 1%.
To be an ohmic layer of the first metal layer
The state of the part acting as can be adjusted. So
After, Al, Cr, Mo, using a metal target such as Ti, with a certain time depositing a second metal layer in an Ar atmosphere to have a thickness of 3000 Angstroms to 5000 Angstroms. The cross-section of this simultaneously formed metal layer is shown in the drawing without the division of the first and second metal layers. At this time, the first metal layer is formed as a layer in which a small amount of PH 3 is included in a normal metal electrode material,
The metal layer is of the same type as a normal metal layer. Therefore, since the first metal layer has an effect similar to that of the ohmic layer, a separate process is not required to form the n + ohmic layer as in the conventional case.
【００１８】このように、本発明によるとｎ+ オーミッ
ク層を別途に形成する必要なくソース電極６とドレイン
電極７だけを形成することにより、半導体層と金属層と
のオーミック接触の効果が得られる。また、本発明によ
ると、非晶質半導体層４とソース電極６およびドレイン
電極７とのオーミック接触特性が向上され、カットオフ
電流が大きく減少され（１０-12 オングストローム以
下）、従来のｎ+ オーミック層の形成に従う汚染により
薄膜トランジスタが破損されることを防止することがで
きる。As described above, according to the present invention, the effect of ohmic contact between the semiconductor layer and the metal layer is obtained by forming only the source electrode 6 and the drain electrode 7 without the need to separately form the n + ohmic layer. . Further, according to the present invention, the ohmic contact characteristics between the amorphous semiconductor layer 4 and the source electrode 6 and the drain electrode 7 are improved, the cut-off current is greatly reduced (10 -12 Å or less), and the conventional n + ohmic contact is achieved. It is possible to prevent the thin film transistor from being damaged by the contamination due to the formation of the layer.
【００１９】本発明は、半導体層とドレイン電極、ソー
ス電極とオーミック層を有するすべての薄膜トランジス
タに適用できるものであって、特許請求の範囲を逸脱し
ない範囲内で前記した実施例の外のすべての修正例を含
めることができる。The present invention can be applied to all thin film transistors having a semiconductor layer and a drain electrode, and a source electrode and an ohmic layer, and can be applied to all the embodiments other than the above-mentioned embodiments within the scope of the claims. Modifications can be included.
【００２０】[0020]
【発明の効果】このように本発明の薄膜トランジスタの
製造方法は構成され作用するものであるから、薄膜トラ
ンジスタの製造の際に、別途にｎ+ オーミック層を形成
する手段を設けることなく前記ｎ+ オーミック層を形成
することができる等の効果を奏する。[Effect of the Invention] Since a method of manufacturing a thin film transistor according to the present invention in this way is to act configured, in the production of a thin film transistor, said n + ohmic without providing means for forming a separately n + ohmic layer The effect that a layer can be formed is produced.
【図１】本発明による薄膜トランジスタの構成を示す断
面図FIG. 1 is a sectional view showing a structure of a thin film transistor according to the present invention.
【図２】従来による薄膜トランジスタの構成を示す断面
図FIG. 2 is a sectional view showing the structure of a conventional thin film transistor.
１ ガラス基板 ２ ゲート電極 ３ ゲート絶縁層 ４ 非晶質半導体 ５ ｎ+ オーミック層 ６ ソース電極 ７ ドレイン電極 ８ 画素電極1 glass substrate 2 gate electrode 3 gate insulating layer 4 amorphous semiconductor 5 n + ohmic layer 6 source electrode 7 drain electrode 8 pixel electrode
Claims (8)
体とドレイン電極およびソース電極を有するＴＦＴの前
記半導体上にドレイン電極およびソース電極を形成する
薄膜トランジスタの製造方法において、前記半導体上に
ＡｒとＰＨ3を所定の比率に混合して、前記半導体層と
オーミック接触するように第１の金属層を所定の厚さに
蒸着形成する段階と、前記蒸着された第１の金属層上に
第２の金属層を所定の時間前記蒸着形成する段階を備え
て、前記第１および第２金属層がドレイン電極あるいは
ソース電極を形成することを特徴とする薄膜トランジス
タの製造方法。1. A method of manufacturing a thin film transistor, wherein a drain electrode and a source electrode are formed on the semiconductor of a TFT having a substrate, a gate electrode, a gate insulating layer, a semiconductor and a drain electrode, and a source electrode, wherein Ar and PH are formed on the semiconductor. 3 is mixed in a predetermined ratio to form a first metal layer by vapor deposition to have an ohmic contact with the semiconductor layer, and a second metal layer is formed on the vapor-deposited first metal layer. A method of manufacturing a thin film transistor, comprising the step of forming a metal layer by vapor deposition for a predetermined time, wherein the first and second metal layers form a drain electrode or a source electrode.
ＰＨ3 のガス混合比率は９９：１であることを特徴とす
る、請求項１に記載の薄膜トランジスタの製造方法。2. The method of manufacturing a thin film transistor according to claim 1, wherein the gas mixing ratio of Ar and PH 3 is 99: 1 in the step of forming the first metal layer.
ス雰囲気下で、Ａｌ、Ｃｒ、Ｍｏ、Ｔｉの中でいずれか
の一つの金属材質で蒸着形成されることを特徴とする、
請求項１または請求項２に記載の薄膜トランジスタの製
造方法。3. The first metal layer is formed by vapor deposition of one of Al, Cr, Mo, and Ti in a mixed gas atmosphere of Ar and PH 3. ,
A method of manufacturing a thin film transistor according to claim 1 or 2.
ｉの中でいずれかの一つの金属材質で形成されることを
特徴とする請求項１に記載の薄膜トランジスタの製造方
法。4. The second metal layer comprises Al, Cr, Mo, T
2. The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistor is formed of any one of i.
トローム乃至１０００オングストロームであることを特
徴とする、請求項１に記載の薄膜トランジスタの製造方
法。5. The method of manufacturing a thin film transistor according to claim 1, wherein the thickness of the first metal layer is 500 angstroms to 1000 angstroms.
ストローム乃至５０００オングストロームであることを
特徴とする請求項１に記載の薄膜トランジスタの製造方
法。6. The method of claim 1, wherein the second metal layer has a thickness of 3000 angstroms to 5000 angstroms.
厚さより厚く形成されることを特徴とする請求項１に記
載の薄膜トランジスタの製造方法。7. The method of manufacturing a thin film transistor according to claim 1, wherein the second metal layer is formed to be thicker than the first metal layer.
オングストローム乃至６０００オングストロームである
ことを特徴とする請求項１に記載の薄膜トランジスタの
製造方法。8. The total thickness of the formed metal layer is 3500.
The method of manufacturing a thin film transistor according to claim 1, wherein the thickness is from angstrom to 6000 angstrom.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1990-11417 | 1990-07-27 | ||
| KR1019900011417A KR930001901B1 (en) | 1990-07-27 | 1990-07-27 | Manufacturing method of tft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04233738A JPH04233738A (en) | 1992-08-21 |
| JP2505662B2 true JP2505662B2 (en) | 1996-06-12 |
Family
ID=19301689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3174186A Expired - Lifetime JP2505662B2 (en) | 1990-07-27 | 1991-07-15 | Method for manufacturing thin film transistor |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2505662B2 (en) |
| KR (1) | KR930001901B1 (en) |
| FR (1) | FR2665300B1 (en) |
| NL (1) | NL9100051A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335336A (en) * | 1992-06-02 | 1993-12-17 | Nec Corp | Manufacture of thin-film transistor |
| TW406317B (en) * | 1997-06-27 | 2000-09-21 | Siemens Ag | Method to produce a barrier-layer in a semiconductor-body and semiconductor component with such a barrier-layer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2044994B (en) * | 1979-03-22 | 1983-06-15 | Philips Electronic Associated | Thin film transistors |
| JPS59124162A (en) * | 1982-12-29 | 1984-07-18 | Sharp Corp | Thin film transistor |
| JPS60183770A (en) * | 1984-03-01 | 1985-09-19 | Asahi Glass Co Ltd | Thin film transistor |
| JPS60211982A (en) * | 1984-04-06 | 1985-10-24 | Hitachi Ltd | Thin film transistor |
| JPS6281057A (en) * | 1985-10-04 | 1987-04-14 | Hosiden Electronics Co Ltd | Transparent conductive film |
-
1990
- 1990-07-27 KR KR1019900011417A patent/KR930001901B1/en not_active IP Right Cessation
-
1991
- 1991-01-11 NL NL9100051A patent/NL9100051A/en active Search and Examination
- 1991-01-24 FR FR9100807A patent/FR2665300B1/en not_active Expired - Fee Related
- 1991-07-15 JP JP3174186A patent/JP2505662B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2665300A1 (en) | 1992-01-31 |
| KR920003534A (en) | 1992-02-29 |
| KR930001901B1 (en) | 1993-03-19 |
| JPH04233738A (en) | 1992-08-21 |
| FR2665300B1 (en) | 1997-09-05 |
| NL9100051A (en) | 1992-02-17 |
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